Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 2 | register "power_limits_config" = "{ |
| 3 | .tdp_pl1_override = 15, |
| 4 | .tdp_pl2_override = 51, |
| 5 | }" |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 6 | |
| 7 | # Auto-switch between X4 NVMe and X2 NVMe. |
| 8 | register "TetonGlacierMode" = "1" |
| 9 | |
| 10 | register "SerialIoDevMode" = "{ |
| 11 | [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| 12 | [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| 13 | [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| 14 | [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| 15 | [PchSerialIoIndexI2C4] = PchSerialIoPci, |
Matt DeVillier | 8facfa8 | 2024-01-21 20:48:26 -0600 | [diff] [blame^] | 16 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 17 | [PchSerialIoIndexSPI0] = PchSerialIoPci, |
Matt DeVillier | 8facfa8 | 2024-01-21 20:48:26 -0600 | [diff] [blame^] | 18 | [PchSerialIoIndexSPI1] = PchSerialIoDisabled, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 19 | [PchSerialIoIndexSPI2] = PchSerialIoDisabled, |
| 20 | [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| 21 | [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| 22 | [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| 23 | }" |
| 24 | |
| 25 | # USB configuration |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 26 | register "usb2_ports[0]" = "{ |
| 27 | .enable = 1, |
| 28 | .ocpin = OC2, |
| 29 | .tx_bias = USB2_BIAS_0MV, |
| 30 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 31 | .pre_emp_bias = USB2_BIAS_11P25MV, |
| 32 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 33 | }" # Type-A Port 2 |
Edward O'Callaghan | 0490f5a | 2020-06-12 12:17:33 +1000 | [diff] [blame] | 34 | register "usb2_ports[1]" = "{ |
| 35 | .enable = 1, |
| 36 | .ocpin = OC1, |
| 37 | .tx_bias = USB2_BIAS_0MV, |
| 38 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 39 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 40 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 41 | }" # Type-A Port 1 |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 42 | register "usb2_ports[2]" = "{ |
| 43 | .enable = 1, |
| 44 | .ocpin = OC3, |
| 45 | .tx_bias = USB2_BIAS_0MV, |
| 46 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 47 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 48 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 49 | }" # Type-A Port 3 |
Edward O'Callaghan | 0490f5a | 2020-06-12 12:17:33 +1000 | [diff] [blame] | 50 | register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 51 | register "usb2_ports[5]" = "{ |
| 52 | .enable = 1, |
| 53 | .ocpin = OC0, |
| 54 | .tx_bias = USB2_BIAS_0MV, |
| 55 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 56 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 57 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 58 | }" # Type-A port 0 |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 59 | register "usb2_ports[9]" = "{ |
| 60 | .enable = 1, |
| 61 | .ocpin = OC_SKIP, |
| 62 | .tx_bias = USB2_BIAS_0MV, |
| 63 | .tx_emp_enable = USB2_PRE_EMP_ON, |
| 64 | .pre_emp_bias = USB2_BIAS_28P15MV, |
| 65 | .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, |
| 66 | }" # BT |
| 67 | |
| 68 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 |
| 69 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 |
| 70 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 |
| 71 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C |
| 72 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 73 | |
Edward O'Callaghan | 8056c91 | 2020-07-01 18:49:13 +1000 | [diff] [blame] | 74 | # Bitmap for Wake Enable on USB attach/detach |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 75 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 76 | USB_PORT_WAKE_ENABLE(2) | |
| 77 | USB_PORT_WAKE_ENABLE(3) | |
Edward O'Callaghan | 8056c91 | 2020-07-01 18:49:13 +1000 | [diff] [blame] | 78 | USB_PORT_WAKE_ENABLE(6)" |
Felix Singer | 21b5a9a | 2023-10-23 07:26:28 +0200 | [diff] [blame] | 79 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | |
| 80 | USB_PORT_WAKE_ENABLE(2) | |
| 81 | USB_PORT_WAKE_ENABLE(3) | |
Edward O'Callaghan | 8056c91 | 2020-07-01 18:49:13 +1000 | [diff] [blame] | 82 | USB_PORT_WAKE_ENABLE(5)" |
| 83 | |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 84 | # Enable eMMC HS400 |
| 85 | register "ScsEmmcHs400Enabled" = "1" |
| 86 | |
| 87 | # EMMC Tx CMD Delay |
| 88 | # Refer to EDS-Vol2-14.3.7. |
| 89 | # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. |
| 90 | # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. |
| 91 | register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" |
| 92 | |
| 93 | # EMMC TX DATA Delay 1 |
| 94 | # Refer to EDS-Vol2-14.3.8. |
| 95 | # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. |
| 96 | # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. |
| 97 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911" |
| 98 | |
| 99 | # EMMC TX DATA Delay 2 |
| 100 | # Refer to EDS-Vol2-14.3.9. |
| 101 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. |
| 102 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 103 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. |
| 104 | # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. |
| 105 | register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828" |
| 106 | |
| 107 | # EMMC RX CMD/DATA Delay 1 |
| 108 | # Refer to EDS-Vol2-14.3.10. |
| 109 | # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. |
| 110 | # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. |
| 111 | # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. |
| 112 | # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. |
| 113 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b" |
| 114 | |
| 115 | # EMMC RX CMD/DATA Delay 2 |
| 116 | # Refer to EDS-Vol2-14.3.12. |
| 117 | # [17:16] stands for Rx Clock before Output Buffer, |
| 118 | # 00: Rx clock after output buffer, |
| 119 | # 01: Rx clock before output buffer, |
| 120 | # 10: Automatic selection based on working mode. |
| 121 | # 11: Reserved |
| 122 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. |
| 123 | # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. |
| 124 | register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D" |
| 125 | |
| 126 | # EMMC Rx Strobe Delay |
| 127 | # Refer to EDS-Vol2-14.3.11. |
| 128 | # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. |
| 129 | # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. |
| 130 | register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" |
| 131 | |
Edward O'Callaghan | 0490f5a | 2020-06-12 12:17:33 +1000 | [diff] [blame] | 132 | # Intel HDA - disable I2S Audio SSP1 and DMIC0 as noibat variant does not have them. |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 133 | register "PchHdaAudioLinkSsp1" = "0" |
| 134 | register "PchHdaAudioLinkDmic0" = "0" |
| 135 | |
| 136 | # Intel Common SoC Config |
| 137 | #+-------------------+---------------------------+ |
| 138 | #| Field | Value | |
| 139 | #+-------------------+---------------------------+ |
| 140 | #| GSPI0 | cr50 TPM. Early init is | |
| 141 | #| | required to set up a BAR | |
| 142 | #| | for TPM communication | |
| 143 | #| | before memory is up | |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 144 | #| I2C2 | PS175 | |
| 145 | #| I2C3 | MST | |
| 146 | #| I2C4 | Audio | |
| 147 | #+-------------------+---------------------------+ |
| 148 | register "common_soc_config" = "{ |
| 149 | .gspi[0] = { |
| 150 | .speed_mhz = 1, |
| 151 | .early_init = 1, |
| 152 | }, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 153 | .i2c[2] = { |
| 154 | .speed = I2C_SPEED_FAST, |
Sam McNally | e36733b | 2020-06-11 16:18:20 +1000 | [diff] [blame] | 155 | .rise_time_ns = 60, |
| 156 | .fall_time_ns = 60, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 157 | }, |
| 158 | .i2c[3] = { |
| 159 | .speed = I2C_SPEED_FAST, |
Sam McNally | e36733b | 2020-06-11 16:18:20 +1000 | [diff] [blame] | 160 | .rise_time_ns = 60, |
| 161 | .fall_time_ns = 60, |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 162 | }, |
| 163 | .i2c[4] = { |
| 164 | .speed = I2C_SPEED_FAST, |
| 165 | .rise_time_ns = 60, |
| 166 | .fall_time_ns = 60, |
| 167 | }, |
| 168 | }" |
| 169 | |
| 170 | # PCIe port 7 for LAN |
| 171 | register "PcieRpEnable[6]" = "1" |
| 172 | register "PcieRpLtrEnable[6]" = "1" |
| 173 | # PCIe port 11 (x2) for NVMe hybrid storage devices |
| 174 | register "PcieRpEnable[10]" = "1" |
| 175 | register "PcieRpLtrEnable[10]" = "1" |
| 176 | # Uses CLK SRC 0 |
| 177 | register "PcieClkSrcUsage[0]" = "6" |
| 178 | register "PcieClkSrcClkReq[0]" = "0" |
| 179 | |
| 180 | # GPIO for SD card detect |
| 181 | register "sdcard_cd_gpio" = "vSD3_CD_B" |
| 182 | |
| 183 | # SATA port 1 Gen3 Strength |
| 184 | # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB |
| 185 | register "sata_port[1].TxGen3DeEmphEnable" = "1" |
| 186 | register "sata_port[1].TxGen3DeEmph" = "0x20" |
| 187 | |
| 188 | device domain 0 on |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 189 | device ref dptf on |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 190 | chip drivers/intel/dptf |
| 191 | ## Active Policy |
| 192 | register "policies.active[0]" = "{.target=DPTF_CPU, |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 193 | .thresholds={TEMP_PCT(94, 0),}}" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 194 | register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 195 | .thresholds={TEMP_PCT(65, 90), |
| 196 | TEMP_PCT(52, 80), |
| 197 | TEMP_PCT(50, 70), |
| 198 | TEMP_PCT(48, 60), |
| 199 | TEMP_PCT(46, 50), |
| 200 | TEMP_PCT(44, 40), |
| 201 | TEMP_PCT(42, 0),}}" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 202 | |
| 203 | ## Passive Policy |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 204 | register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" |
| 205 | register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 206 | |
| 207 | ## Critical Policy |
| 208 | register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 209 | register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)" |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 210 | |
| 211 | ## Power Limits Control |
| 212 | # PL1 is fixed at 15W, avg over 28-32s interval |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 213 | # 15-51W PL2 in 1000mW increments, avg over 28-32s interval |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 214 | register "controls.power_limits.pl1" = "{ |
| 215 | .min_power = 15000, |
| 216 | .max_power = 15000, |
| 217 | .time_window_min = 28 * MSECS_PER_SEC, |
| 218 | .time_window_max = 32 * MSECS_PER_SEC, |
| 219 | .granularity = 200,}" |
| 220 | register "controls.power_limits.pl2" = "{ |
Wisley Chen | 32c2649 | 2020-09-02 14:08:22 +0800 | [diff] [blame] | 221 | .min_power = 15000, |
| 222 | .max_power = 51000, |
Edward O'Callaghan | b7a68d5 | 2020-08-28 20:14:50 +1000 | [diff] [blame] | 223 | .time_window_min = 28 * MSECS_PER_SEC, |
| 224 | .time_window_max = 32 * MSECS_PER_SEC, |
| 225 | .granularity = 1000,}" |
| 226 | |
| 227 | ## Charger Performance Control (Control, mA) |
| 228 | register "controls.charger_perf[0]" = "{ 255, 1700 }" |
| 229 | register "controls.charger_perf[1]" = "{ 24, 1500 }" |
| 230 | register "controls.charger_perf[2]" = "{ 16, 1000 }" |
| 231 | register "controls.charger_perf[3]" = "{ 8, 500 }" |
| 232 | |
| 233 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 234 | register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" |
| 235 | register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" |
| 236 | register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" |
| 237 | register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" |
| 238 | register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" |
| 239 | register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" |
| 240 | register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" |
| 241 | register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" |
| 242 | register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" |
| 243 | register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" |
| 244 | |
| 245 | # Fan options |
| 246 | register "options.fan.fine_grained_control" = "1" |
| 247 | register "options.fan.step_size" = "2" |
| 248 | |
| 249 | device generic 0 on end |
| 250 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 251 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 252 | device ref xhci on |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 253 | chip drivers/usb/acpi |
| 254 | device usb 0.0 on |
| 255 | chip drivers/usb/acpi |
| 256 | register "desc" = ""USB2 Type-A Front Left"" |
| 257 | register "type" = "UPC_TYPE_A" |
| 258 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 259 | device usb 2.0 on end |
| 260 | end |
| 261 | chip drivers/usb/acpi |
| 262 | register "desc" = ""USB2 Type-C Port Rear"" |
| 263 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 264 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 265 | device usb 2.1 on end |
| 266 | end |
| 267 | chip drivers/usb/acpi |
| 268 | register "desc" = ""USB2 Type-A Front Right"" |
| 269 | register "type" = "UPC_TYPE_A" |
| 270 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 271 | device usb 2.2 on end |
| 272 | end |
| 273 | chip drivers/usb/acpi |
| 274 | register "desc" = ""USB2 Type-A Rear Right"" |
| 275 | register "type" = "UPC_TYPE_A" |
| 276 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 277 | device usb 2.3 on end |
| 278 | end |
| 279 | chip drivers/usb/acpi |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 280 | register "desc" = ""USB2 Type-A Rear Left"" |
| 281 | register "type" = "UPC_TYPE_A" |
| 282 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 283 | device usb 2.5 on end |
| 284 | end |
| 285 | chip drivers/usb/acpi |
| 286 | device usb 2.6 off end |
| 287 | end |
| 288 | chip drivers/usb/acpi |
| 289 | register "desc" = ""USB3 Type-A Front Left"" |
| 290 | register "type" = "UPC_TYPE_USB3_A" |
| 291 | register "group" = "ACPI_PLD_GROUP(0, 0)" |
| 292 | device usb 3.0 on end |
| 293 | end |
| 294 | chip drivers/usb/acpi |
| 295 | register "desc" = ""USB3 Type-A Front Right"" |
| 296 | register "type" = "UPC_TYPE_USB3_A" |
| 297 | register "group" = "ACPI_PLD_GROUP(0, 1)" |
| 298 | device usb 3.1 on end |
| 299 | end |
| 300 | chip drivers/usb/acpi |
| 301 | register "desc" = ""USB3 Type-A Rear Right"" |
| 302 | register "type" = "UPC_TYPE_USB3_A" |
| 303 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 304 | device usb 3.2 on end |
| 305 | end |
| 306 | chip drivers/usb/acpi |
| 307 | register "desc" = ""USB3 Type-C Rear"" |
| 308 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 309 | register "group" = "ACPI_PLD_GROUP(1, 3)" |
| 310 | device usb 3.3 on end |
| 311 | end |
| 312 | chip drivers/usb/acpi |
| 313 | register "desc" = ""USB3 Type-A Rear Left"" |
| 314 | register "type" = "UPC_TYPE_USB3_A" |
| 315 | register "group" = "ACPI_PLD_GROUP(1, 0)" |
| 316 | device usb 3.4 on end |
| 317 | end |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 318 | end |
| 319 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 320 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 321 | device ref i2c2 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 322 | # PCON PS175 |
Shiyu Sun | aeacf8b | 2020-06-15 02:58:53 +1000 | [diff] [blame] | 323 | chip drivers/i2c/generic |
| 324 | register "hid" = ""1AF80175"" |
| 325 | register "name" = ""PS17"" |
| 326 | register "desc" = ""Parade PS175"" |
| 327 | device i2c 4a on end |
| 328 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 329 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 330 | device ref i2c3 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 331 | # Realtek RTD2142 |
Shiyu Sun | aeacf8b | 2020-06-15 02:58:53 +1000 | [diff] [blame] | 332 | chip drivers/i2c/generic |
| 333 | register "hid" = ""10EC2142"" |
| 334 | register "name" = ""RTD2"" |
| 335 | register "desc" = ""Realtek RTD2142"" |
| 336 | device i2c 4a on end |
| 337 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 338 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 339 | device ref i2c4 on |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 340 | chip drivers/i2c/generic |
| 341 | register "hid" = ""10EC5682"" |
| 342 | register "name" = ""RT58"" |
| 343 | register "desc" = ""Realtek RT5682"" |
| 344 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" |
| 345 | register "property_count" = "1" |
| 346 | # Set the jd_src to RT5668_JD1 for jack detection |
| 347 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 348 | register "property_list[0].name" = ""realtek,jd-src"" |
| 349 | register "property_list[0].integer" = "1" |
| 350 | device i2c 1a on end |
| 351 | end |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 352 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 353 | device ref emmc on end |
| 354 | device ref pcie_rp7 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 355 | # RTL8111H Ethernet NIC |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 356 | chip drivers/net |
| 357 | register "customized_leds" = "0x05af" |
| 358 | register "wake" = "GPE0_DW1_07" # GPP_C7 |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 359 | register "device_index" = "0" |
Alexis Savery | 8ba64cd | 2023-08-30 20:11:34 +0000 | [diff] [blame] | 360 | register "enable_aspm_l1_2" = "1" |
Matt DeVillier | f03b8fc | 2023-11-19 16:12:56 -0600 | [diff] [blame] | 361 | device pci 00.0 on end |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 362 | end |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 363 | register "PcieRpSlotImplemented[6]" = "1" |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 364 | end |
Matt DeVillier | 3f4c830 | 2024-01-21 20:39:03 -0600 | [diff] [blame] | 365 | device ref pcie_rp11 on |
Felix Singer | d571ea2 | 2024-01-17 21:51:07 +0100 | [diff] [blame] | 366 | # X2 NVMe |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 367 | register "PcieRpSlotImplemented[10]" = "1" |
| 368 | end |
Edward O'Callaghan | a81be27d | 2020-05-29 14:13:08 +1000 | [diff] [blame] | 369 | end |
| 370 | |
| 371 | # VR Settings Configuration for 4 Domains |
| 372 | #+----------------+-------+-------+-------+-------+ |
| 373 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 374 | #+----------------+-------+-------+-------+-------+ |
| 375 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 376 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 377 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 378 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 379 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 380 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 381 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 382 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 383 | #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 384 | #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 | |
| 385 | #+----------------+-------+-------+-------+-------+ |
| 386 | #Note: IccMax settings are moved to SoC code |
| 387 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 388 | .vr_config_enable = 1, |
| 389 | .psi1threshold = VR_CFG_AMP(20), |
| 390 | .psi2threshold = VR_CFG_AMP(5), |
| 391 | .psi3threshold = VR_CFG_AMP(1), |
| 392 | .psi3enable = 1, |
| 393 | .psi4enable = 1, |
| 394 | .imon_slope = 0x0, |
| 395 | .imon_offset = 0x0, |
| 396 | .icc_max = 0, |
| 397 | .voltage_limit = 1520, |
| 398 | .ac_loadline = 1004, |
| 399 | .dc_loadline = 1004, |
| 400 | }" |
| 401 | |
| 402 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 403 | .vr_config_enable = 1, |
| 404 | .psi1threshold = VR_CFG_AMP(20), |
| 405 | .psi2threshold = VR_CFG_AMP(5), |
| 406 | .psi3threshold = VR_CFG_AMP(1), |
| 407 | .psi3enable = 1, |
| 408 | .psi4enable = 1, |
| 409 | .imon_slope = 0x0, |
| 410 | .imon_offset = 0x0, |
| 411 | .icc_max = 0, |
| 412 | .voltage_limit = 1520, |
| 413 | .ac_loadline = 181, |
| 414 | .dc_loadline = 181, |
| 415 | }" |
| 416 | |
| 417 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 418 | .vr_config_enable = 1, |
| 419 | .psi1threshold = VR_CFG_AMP(20), |
| 420 | .psi2threshold = VR_CFG_AMP(5), |
| 421 | .psi3threshold = VR_CFG_AMP(1), |
| 422 | .psi3enable = 1, |
| 423 | .psi4enable = 1, |
| 424 | .imon_slope = 0x0, |
| 425 | .imon_offset = 0x0, |
| 426 | .icc_max = 0, |
| 427 | .voltage_limit = 1520, |
| 428 | .ac_loadline = 319, |
| 429 | .dc_loadline = 319, |
| 430 | }" |
| 431 | |
| 432 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 433 | .vr_config_enable = 1, |
| 434 | .psi1threshold = VR_CFG_AMP(20), |
| 435 | .psi2threshold = VR_CFG_AMP(5), |
| 436 | .psi3threshold = VR_CFG_AMP(1), |
| 437 | .psi3enable = 1, |
| 438 | .psi4enable = 1, |
| 439 | .imon_slope = 0x0, |
| 440 | .imon_offset = 0x0, |
| 441 | .icc_max = 0, |
| 442 | .voltage_limit = 1520, |
| 443 | .ac_loadline = 319, |
| 444 | .dc_loadline = 319, |
| 445 | }" |
| 446 | |
| 447 | end |