Martin Roth | 33906d2 | 2017-06-07 12:09:41 -0600 | [diff] [blame] | 1 | # Applies to unbuffered DIMM types |
| 2 | # UDIMM, SO-DIMM, Micro-DIMM, Micro-UDIMM, |
| 3 | # 72b-SO-UDIMM, 16b-SO-UDIMM, 32b-SO-UDIMM |
| 4 | |
| 5 | |
| 6 | # 4_01_02_11R24.pdf |
| 7 | # |
| 8 | # JEDEC Standard No. 21-C |
| 9 | # Page 4.1.2.11 - 1 |
| 10 | # Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules |
| 11 | # DDR3 SPD |
| 12 | # Document Release 6 |
| 13 | # UDIMM Revision 1.3 |
| 14 | # RDIMM Revision 1.3 |
| 15 | # CDIMM Revision 1.3 |
| 16 | # LRDIMM Revision 1.2 |
| 17 | |
| 18 | { |
| 19 | # Byte 0: Number of Bytes Used / Number of Bytes in SPD Device / |
| 20 | # CRC Coverage |
| 21 | "SPD_Bytes_Used" : 4, |
| 22 | "SPD_Bytes_Total" : 3, |
| 23 | "CRC_Coverage" : 1, |
| 24 | |
| 25 | # Byte 1: SPD Revision |
| 26 | "SPD_Revision" : 8, |
| 27 | |
| 28 | # Byte 2: Key Byte / DRAM Device Type |
| 29 | "DRAM_Device_Type" : 8, |
| 30 | |
| 31 | # Byte 3: Key Byte / Module Type |
| 32 | "Module_Type" : 4, |
| 33 | "Byte_3_reserved" : 4, |
| 34 | |
| 35 | # Byte 4: SDRAM Density and Banks |
| 36 | "SDRAM_Capacity" : 4, |
| 37 | "Bank_Address_Bits" : 3, |
| 38 | "Byte_4_reserved" : 1, |
| 39 | |
| 40 | # Byte 5: SDRAM Addressing |
| 41 | "Column_Address_Bits" : 3, |
| 42 | "Row_Address_Bits" : 3, |
| 43 | "Byte_5_reserved" : 2, |
| 44 | |
| 45 | # Byte 6: Module Nominal Voltage, VDD |
| 46 | "NOT_1.5_V_Operable" : 1, |
| 47 | "1.35_V_Operable" : 1, |
| 48 | "1.25_V_Operable" : 1, |
| 49 | "Byte_6_reserved" : 5, |
| 50 | |
| 51 | # Byte 7: Module Organization |
| 52 | "SDRAM_Device_Width" : 3, |
| 53 | "Number_of_Ranks" : 3, |
| 54 | "Byte_7_reserved" : 2, |
| 55 | |
| 56 | # Byte 8: Module Memory Bus Width |
| 57 | "Primary_Bus_Width" : 3, |
| 58 | "Bus_Width_Extension" : 3, |
| 59 | "Byte_8_reserved" : 2, |
| 60 | |
| 61 | # Byte 9: Fine Timebase (FTB) Dividend / Divisor |
| 62 | "Fine_Timebase_Divisor" : 4, |
| 63 | "Fine_Timebase_Dividend" : 4, |
| 64 | |
| 65 | # Bytes 10 / 11: Medium Timebase (MTB) Dividend / Divisor |
| 66 | "Medium_Timebase_Dividend" : 8, |
| 67 | "Medium_Timebase_Divisor" : 8, |
| 68 | |
| 69 | # Byte 12: SDRAM Minimum Cycle Time (t CK min) |
| 70 | "Minimum_SDRAM_Cycle_Time" : 8, |
| 71 | |
| 72 | # Byte 13: Reserved |
| 73 | "Byte_13_Reserved" : 8, |
| 74 | |
| 75 | # Bytes 14 / 15: CAS Latencies Supported |
| 76 | "CL_4_Supported" : 1, |
| 77 | "CL_5_Supported" : 1, |
| 78 | "CL_6_Supported" : 1, |
| 79 | "CL_7_Supported" : 1, |
| 80 | "CL_8_Supported" : 1, |
| 81 | "CL_9_Supported" : 1, |
| 82 | "CL_10_Supported" : 1, |
| 83 | "CL_11_Supported" : 1, |
| 84 | |
| 85 | "CL_12_Supported" : 1, |
| 86 | "CL_13_Supported" : 1, |
| 87 | "CL_14_Supported" : 1, |
| 88 | "CL_15_Supported" : 1, |
| 89 | "CL_16_Supported" : 1, |
| 90 | "CL_17_Supported" : 1, |
| 91 | "CL_18_Supported" : 1, |
| 92 | "Byte_15_Reserved" : 1, |
| 93 | |
| 94 | # Byte 16: Minimum CAS Latency Time (tAAmin) |
| 95 | "tAAmin" : 8, |
| 96 | |
| 97 | # Byte 17: Minimum Write Recovery Time (tWRmin) |
| 98 | "tWRmin" : 8, |
| 99 | |
| 100 | # Byte 18: Minimum RAS to CAS Delay Time (tRCDmin) |
| 101 | "tRCDmin" : 8, |
| 102 | |
| 103 | # Byte 19: Minimum Row Active to Row Active Delay Time (tRRDmin) |
| 104 | "tRRDmin" : 8, |
| 105 | |
| 106 | # Byte 20: Minimum Row Precharge Delay Time (tRPmin) |
| 107 | "tRPmin" : 8, |
| 108 | |
| 109 | # Bytes 21 - 23: Minimum Active to Precharge Delay Time (tRASmin) |
| 110 | # / Minimum Active to Active/Refresh Delay Time |
| 111 | # (tRCmin) |
| 112 | "tRASmin_Most_Significant Nibble" : 4, |
| 113 | "tRCmin_Most_Significant Nibble" : 4, |
| 114 | "tRASmin_LSB" : 8, |
| 115 | "tRCmin_LSB" : 8, |
| 116 | |
| 117 | # Bytes 24 - 25: Minimum Refresh Recovery Delay Time (tRFCmin) |
| 118 | "tRFCmin LSB" : 8, |
| 119 | "tRFCmin MSB" : 8, |
| 120 | |
| 121 | # Byte 26: Minimum Internal Write to Read Command Delay Time |
| 122 | "tWTRmin" : 8, |
| 123 | |
| 124 | # Byte 27: Minimum Internal Read to Precharge Command Delay Time |
| 125 | # (tRTPmin) |
| 126 | "tRTPmin" : 8, |
| 127 | |
| 128 | # Byte 28 - 29: Minimum Four Activate Window Delay Time |
| 129 | # (tFAWmin) |
| 130 | "tFAWmin Most Significant Nibble" : 4, |
| 131 | "Byte_28_Reserved" : 4, |
| 132 | "tFAWmin Most Significant Byte" : 8, |
| 133 | |
| 134 | # Byte 30: SDRAM Optional Features |
| 135 | "RQZ_Div_6_Supported" : 1, |
| 136 | "RQZ_Div_7_Supported" : 1, |
| 137 | "Byte_30_Reserved" : 5, |
| 138 | "DLL_Off_Mode_Supported" : 1, |
| 139 | |
| 140 | # Byte 31: SDRAM Thermal and Refresh |
| 141 | # Options |
| 142 | "Extended_Temp_range_supported" : 1, |
| 143 | "Extended_Temp_Refresh_1x_Refresh" : 1, |
| 144 | "Auto_Self_Refresh_Supported" : 1, |
| 145 | "On-Die_Thermal_Sensor" : 1, |
| 146 | "Byte_31_Reserved" : 3, |
| 147 | "Partial_Array_Self_Refresh_Supported" : 1, |
| 148 | |
| 149 | # Byte 32: Module Thermal Sensor |
| 150 | "Thermal_Sensor_Accuracy" : 7, |
| 151 | "Thermal_Sensor_incorporated" : 1, |
| 152 | |
| 153 | # Byte 33: SDRAM Device Type |
| 154 | "Signal_Loading" : 2, |
| 155 | "Byte_33_Reserved" : 2, |
| 156 | "Die_Count" : 3, |
| 157 | "SDRAM_Device_Type" : 1, |
| 158 | |
| 159 | # Byte 34: Fine Offset for SDRAM Minimum |
| 160 | # Cycle Time (tCKmin) |
| 161 | "tCKmin_Fine_Offset" : 8, |
| 162 | |
| 163 | #Byte 35: Fine Offset for Minimum CAS Latency Time (tAAmin) |
| 164 | "tAAmin_Fine_Offset" : 8, |
| 165 | |
| 166 | # Byte 36: Fine Offset for Minimum RAS to CAS Delay Time |
| 167 | # (tRCDmin) |
| 168 | "tRCDmin_Fine_Offset" : 8, |
| 169 | |
| 170 | #Byte 37: Fine Offset for Minimum Row Precharge Delay Time |
| 171 | # (tRPmin) |
| 172 | "tRPmin_Fine_Offset" : 8, |
| 173 | |
| 174 | # Byte 38: Fine Offset for Minimum Active to Active/Refresh |
| 175 | # Delay Time (tRCmin) |
| 176 | "tRCmin_Fine_Offset" : 8, |
| 177 | |
| 178 | # Bytes 39 / 40: Reserved |
| 179 | "Byte_39_Reserved" : 8, |
| 180 | "Byte_40_Reserved" : 8, |
| 181 | |
| 182 | # Byte 41: SDRAM Maximum Active Count (MAC) Value |
| 183 | "Maximum_Activate_Count" : 4, |
| 184 | "Maximum_Activate_Window" : 2, |
| 185 | "Byte_41_Reserved" : 2, |
| 186 | |
| 187 | # Bytes 42 - 59: Reserved |
| 188 | "Reserved_bytes_42_to_59_" [18] : 8, |
| 189 | |
| 190 | # Module-Specific Section: Bytes 60 - 116 for Unbuffered DIMMS |
| 191 | |
| 192 | # Byte 60 (Unbuffered): Raw Card Extension, Module Nominal Height |
| 193 | "Module_Nominal_Height" : 5, |
| 194 | "Raw_Card_Estension" : 3, |
| 195 | |
| 196 | # Byte 61 (Unbuffered): Module Maximum Thickness |
| 197 | "Module_Thickness_Front" : 4, |
| 198 | "Module_Thickness_Back" : 4, |
| 199 | |
| 200 | # Byte 62 (Unbuffered): Reference Raw Card Used |
| 201 | "Reference_Raw_Card" : 5, |
| 202 | "Reference_Raw_Card_Revision" : 2, |
| 203 | "Reference_Raw_Card_Extension" : 1, |
| 204 | |
| 205 | # Byte 63: Address Mapping from Edge Connector to DRAM |
| 206 | "Rank_1_Mapping_Mirrored" : 1, |
| 207 | "Byte_63_Reserved" : 7, |
| 208 | |
| 209 | # Bytes 64 -116 (Unbuffered): Reserved |
| 210 | "Module_Specific_Byte_Reserved_"[53] : 8, |
| 211 | |
| 212 | # Bytes 117 - 118: Module ID: Module Manufacturers JEDEC ID Code |
| 213 | "Module_Manufacturer_JEDEC_ID_Code" : 16, |
| 214 | |
| 215 | # Byte 119: Module ID: Module Manufacturing Location |
| 216 | "Module_Manufacturing_Location" : 8, |
| 217 | |
| 218 | # Bytes 120 - 121: Module ID: Module Manufacturing Date |
| 219 | "Module_Manufacturing_Date" : 16, |
| 220 | |
| 221 | # Bytes 122 - 125: Module ID: Module Serial Number |
| 222 | "Module_Serial_Number" : 32, |
| 223 | |
| 224 | # Bytes 126 - 127: Cyclical Redundancy Code |
| 225 | "Module_CRC" : 16, |
| 226 | |
| 227 | # Bytes 128 - 145: Module Part Number |
| 228 | "Module_Part_Number"[18] : 8, |
| 229 | |
| 230 | # Bytes 146 - 147: Module Revision Code |
| 231 | "Module_Revision_Code" : 16, |
| 232 | |
| 233 | # Bytes 148 - 149: DRAM Manufacturers JEDEC ID Code |
| 234 | "DRAM_Manufacturer_JEDEC_ID_Code" : 16, |
| 235 | |
| 236 | # Bytes 150 - 175: Manufacturers Specific Data |
| 237 | "Manufacturer_Specific_Data_byte_" [26] : 8, |
| 238 | |
| 239 | # Bytes 176 - 255: Open for customer use |
| 240 | "Customer_use_byte_" [80] : 8 |
| 241 | } |