Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Martin Roth | 933ca5b | 2017-08-17 15:15:55 -0600 | [diff] [blame] | 3 | #ifndef __STONEYRIDGE_CHIP_H__ |
| 4 | #define __STONEYRIDGE_CHIP_H__ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 6 | #include <stddef.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 7 | #include <stdint.h> |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 8 | #include <commonlib/helpers.h> |
Justin TerAvest | 13101a7 | 2018-01-24 14:23:12 -0700 | [diff] [blame] | 9 | #include <drivers/i2c/designware/dw_i2c.h> |
Felix Held | d8bcad5 | 2022-01-10 22:27:29 +0100 | [diff] [blame] | 10 | #include <gpio.h> |
Marshall Dawson | f42344a | 2019-05-02 12:53:00 -0600 | [diff] [blame] | 11 | #include <soc/i2c.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 12 | #include <acpi/acpi_device.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 13 | |
Marshall Dawson | 5bb0d75 | 2017-09-25 10:00:47 -0600 | [diff] [blame] | 14 | #define MAX_NODES 1 |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 15 | #if CONFIG(AMD_APU_MERLINFALCON) |
Richard Spiegel | 9247e86 | 2019-06-28 09:18:47 -0700 | [diff] [blame] | 16 | #define MAX_DRAM_CH 2 |
| 17 | #define MAX_DIMMS_PER_CH 2 |
Marshall Dawson | e1988f5 | 2019-11-25 11:15:35 -0700 | [diff] [blame] | 18 | #else /* AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON */ |
Marshall Dawson | 5bb0d75 | 2017-09-25 10:00:47 -0600 | [diff] [blame] | 19 | #define MAX_DRAM_CH 1 |
| 20 | #define MAX_DIMMS_PER_CH 2 |
Richard Spiegel | 9247e86 | 2019-06-28 09:18:47 -0700 | [diff] [blame] | 21 | #endif |
Marshall Dawson | 5bb0d75 | 2017-09-25 10:00:47 -0600 | [diff] [blame] | 22 | |
Justin TerAvest | 13101a7 | 2018-01-24 14:23:12 -0700 | [diff] [blame] | 23 | #define STONEY_I2C_DEV_MAX 4 |
| 24 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 25 | struct soc_amd_stoneyridge_config { |
Marc Jones | afd03d8 | 2017-11-16 10:01:08 -0700 | [diff] [blame] | 26 | u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 27 | enum { |
| 28 | DRAM_CONTENTS_KEEP, |
| 29 | DRAM_CONTENTS_CLEAR |
| 30 | } dram_clear_on_reset; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 31 | |
| 32 | enum { |
| 33 | /* Do not enable UMA in the system. */ |
| 34 | UMAMODE_NONE, |
| 35 | /* Enable UMA with a specific size. */ |
| 36 | UMAMODE_SPECIFIED_SIZE, |
| 37 | /* Let AGESA determine the proper size. Non-legacy requires |
| 38 | * the resolution to be specified PLATFORM_CONFIGURATION */ |
| 39 | UMAMODE_AUTO_LEGACY, |
| 40 | UMAMODE_AUTO_NON_LEGACY, |
| 41 | } uma_mode; |
| 42 | |
| 43 | /* Used if UMAMODE_SPECIFIED_SIZE is set. */ |
| 44 | size_t uma_size; |
Justin TerAvest | 13101a7 | 2018-01-24 14:23:12 -0700 | [diff] [blame] | 45 | |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 46 | /* |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 47 | * If sb_reset_i2c_peripherals() is called, this devicetree register |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 48 | * defines which I2C SCL will be toggled 9 times at 100 KHz. |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 49 | * For example, should we need I2C0 and I2C3 have their peripheral |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 50 | * devices reset by toggling SCL, use: |
Richard Spiegel | 5401aa2 | 2018-09-11 11:36:38 -0700 | [diff] [blame] | 51 | * |
| 52 | * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) |
| 53 | */ |
| 54 | u8 i2c_scl_reset; |
Justin TerAvest | 13101a7 | 2018-01-24 14:23:12 -0700 | [diff] [blame] | 55 | struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX]; |
Richard Spiegel | c703beb | 2018-09-10 13:42:00 -0700 | [diff] [blame] | 56 | u8 stapm_percent; |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 57 | u32 stapm_time_ms; |
| 58 | u32 stapm_power_mw; |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 59 | /* |
| 60 | * This specifies the LVDS/eDP power-up sequence time for the delay |
| 61 | * between VaryBL and BLON. |
| 62 | * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. |
| 63 | * n - Values other than zero specify a setting of (4 * n) milliseconds |
| 64 | * time delay. |
| 65 | */ |
| 66 | u8 lvds_poseq_varybl_to_blon; |
| 67 | u8 lvds_poseq_blon_to_varybl; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 68 | }; |
| 69 | |
Martin Roth | 933ca5b | 2017-08-17 15:15:55 -0600 | [diff] [blame] | 70 | #endif /* __STONEYRIDGE_CHIP_H__ */ |