Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* TODO: Update for Glinda */ |
| 4 | |
| 5 | #include <amdblocks/acpimmio.h> |
| 6 | #include <amdblocks/aoac.h> |
| 7 | #include <amdblocks/espi.h> |
| 8 | #include <amdblocks/i2c.h> |
| 9 | #include <amdblocks/lpc.h> |
| 10 | #include <amdblocks/pmlib.h> |
| 11 | #include <amdblocks/smbus.h> |
| 12 | #include <amdblocks/uart.h> |
| 13 | #include <soc/i2c.h> |
| 14 | #include <soc/southbridge.h> |
| 15 | #include <soc/uart.h> |
| 16 | |
| 17 | #include "chip.h" |
| 18 | |
| 19 | /* Before console init */ |
| 20 | void fch_pre_init(void) |
| 21 | { |
Felix Held | 8336c72 | 2023-07-14 18:41:23 +0200 | [diff] [blame] | 22 | /* |
| 23 | * PM_04_ACPIMMIO_DECODE_EN which enables the ACPIMMIO decode is already set after |
| 24 | * reset. Since the IO port based indirect PM register space access isn't implemented |
| 25 | * in Phoenix any more, don't call enable_acpimmio_decode_pm04() which uses the |
| 26 | * indirect PM register space access via the IO ports that aren't implemented any more. |
| 27 | */ |
Martin Roth | f95a11e | 2022-10-21 16:43:08 -0600 | [diff] [blame] | 28 | /* Setup SPI base by calling lpc_early_init before setting up eSPI. */ |
| 29 | lpc_early_init(); |
| 30 | |
| 31 | /* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI |
| 32 | interface hasn't already been set up in verstage on PSP */ |
| 33 | if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) |
| 34 | configure_espi_with_mb_hook(); |
| 35 | |
| 36 | fch_spi_early_init(); |
| 37 | fch_smbus_init(); |
| 38 | fch_enable_cf9_io(); |
| 39 | fch_enable_legacy_io(); |
| 40 | fch_disable_legacy_dma_io(); |
| 41 | enable_aoac_devices(); |
| 42 | |
| 43 | /* |
| 44 | * On reset Range_0 defaults to enabled. We want to start with a clean |
| 45 | * slate to not have things unexpectedly enabled. |
| 46 | */ |
| 47 | clear_uart_legacy_config(); |
| 48 | |
| 49 | if (CONFIG(AMD_SOC_CONSOLE_UART)) |
| 50 | set_uart_config(CONFIG_UART_FOR_CONSOLE); |
| 51 | |
| 52 | /* disable the keyboard reset function before mainboard GPIO setup */ |
| 53 | if (CONFIG(DISABLE_KEYBOARD_RESET_PIN)) |
| 54 | fch_disable_kb_rst(); |
| 55 | } |
| 56 | |
| 57 | /* After console init */ |
| 58 | void fch_early_init(void) |
| 59 | { |
| 60 | reset_i2c_peripherals(); |
| 61 | pm_set_power_failure_state(); |
| 62 | fch_print_pmxc0_status(); |
| 63 | i2c_soc_early_init(); |
| 64 | show_spi_speeds_and_modes(); |
| 65 | |
| 66 | if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING)) |
| 67 | lpc_disable_spi_rom_sharing(); |
| 68 | } |