Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | 72b7891 | 2021-04-13 00:08:33 +0200 | [diff] [blame] | 3 | #include <amdblocks/acpi.h> |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 4 | #include <amdblocks/acpimmio.h> |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 5 | #include <amdblocks/amd_pci_util.h> |
Robert Zieba | 5a040d6 | 2022-10-03 14:27:16 -0600 | [diff] [blame] | 6 | #include <amdblocks/pci_clk_req.h> |
Martin Roth | 440c823 | 2023-02-01 14:27:18 -0700 | [diff] [blame] | 7 | #include <amdblocks/reset.h> |
Felix Held | dea4e0f | 2021-09-22 20:05:53 +0200 | [diff] [blame] | 8 | #include <amdblocks/gpio.h> |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 9 | #include <amdblocks/i2c.h> |
Felix Held | e094b1f | 2021-02-09 22:55:04 +0100 | [diff] [blame] | 10 | #include <amdblocks/smi.h> |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 11 | #include <assert.h> |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 12 | #include <bootstate.h> |
Felix Held | e094b1f | 2021-02-09 22:55:04 +0100 | [diff] [blame] | 13 | #include <cpu/x86/smm.h> |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 14 | #include <device/device.h> |
| 15 | #include <device/pci.h> |
| 16 | #include <device/pci_ids.h> |
| 17 | #include <fw_config.h> |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 18 | #include <soc/amd_pci_int_defs.h> |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 19 | #include <soc/iomap.h> |
Zheng Bao | 7b13e4e | 2021-03-16 16:13:56 +0800 | [diff] [blame] | 20 | #include <soc/i2c.h> |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 21 | #include <soc/platform_descriptors.h> |
Felix Held | e094b1f | 2021-02-09 22:55:04 +0100 | [diff] [blame] | 22 | #include <soc/smi.h> |
Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 23 | #include <soc/southbridge.h> |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 24 | #include "chip.h" |
Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 25 | |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 26 | /* |
| 27 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
| 28 | * provides a visible association with the index, therefore helping |
| 29 | * maintainability of table. If a new index/name is defined in |
| 30 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 31 | * Order is not important. |
| 32 | */ |
Elyes Haouas | 2476942 | 2023-01-12 06:21:42 +0100 | [diff] [blame] | 33 | static const struct irq_idx_name irq_association[] = { |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 34 | { PIRQ_A, "INTA#" }, |
| 35 | { PIRQ_B, "INTB#" }, |
| 36 | { PIRQ_C, "INTC#" }, |
| 37 | { PIRQ_D, "INTD#" }, |
| 38 | { PIRQ_E, "INTE#" }, |
| 39 | { PIRQ_F, "INTF#/GENINT2" }, |
| 40 | { PIRQ_G, "INTG#" }, |
| 41 | { PIRQ_H, "INTH#" }, |
| 42 | { PIRQ_MISC, "Misc" }, |
| 43 | { PIRQ_MISC0, "Misc0" }, |
| 44 | { PIRQ_HPET_L, "HPET_L" }, |
| 45 | { PIRQ_HPET_H, "HPET_H" }, |
| 46 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 47 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 48 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 49 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
| 50 | { PIRQ_SCI, "SCI" }, |
| 51 | { PIRQ_SMBUS, "SMBUS" }, |
| 52 | { PIRQ_ASF, "ASF" }, |
| 53 | { PIRQ_PMON, "PerMon" }, |
| 54 | { PIRQ_SD, "SD" }, |
| 55 | { PIRQ_SDIO, "SDIO" }, |
| 56 | { PIRQ_CIR, "CIR" }, |
| 57 | { PIRQ_GPIOA, "GPIOa" }, |
| 58 | { PIRQ_GPIOB, "GPIOb" }, |
| 59 | { PIRQ_GPIOC, "GPIOc" }, |
| 60 | { PIRQ_SATA, "SATA" }, |
| 61 | { PIRQ_EMMC, "eMMC" }, |
| 62 | { PIRQ_GPP0, "GPP0" }, |
| 63 | { PIRQ_GPP1, "GPP1" }, |
| 64 | { PIRQ_GPP2, "GPP2" }, |
| 65 | { PIRQ_GPP3, "GPP3" }, |
| 66 | { PIRQ_GPIO, "GPIO" }, |
| 67 | { PIRQ_I2C0, "I2C0" }, |
| 68 | { PIRQ_I2C1, "I2C1" }, |
| 69 | { PIRQ_I2C2, "I2C2" }, |
| 70 | { PIRQ_I2C3, "I2C3" }, |
| 71 | { PIRQ_UART0, "UART0" }, |
| 72 | { PIRQ_UART1, "UART1" }, |
| 73 | { PIRQ_I2C4, "I2C4" }, |
| 74 | { PIRQ_I2C5, "I2C5" }, |
| 75 | }; |
| 76 | |
| 77 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 78 | { |
| 79 | *size = ARRAY_SIZE(irq_association); |
| 80 | return irq_association; |
| 81 | } |
| 82 | |
Felix Held | fd2982e | 2021-07-22 17:41:38 +0200 | [diff] [blame] | 83 | static void fch_clk_output_48Mhz(void) |
| 84 | { |
| 85 | uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); |
| 86 | /* Enable BP_X48M0 Clock Output */ |
| 87 | ctrl |= BP_X48M0_OUTPUT_EN; |
Felix Held | bad64c8 | 2021-12-15 00:30:10 +0100 | [diff] [blame] | 88 | /* Disable clock output in S0i3 */ |
| 89 | ctrl |= BP_X48M0_S0I3_DIS; |
Felix Held | fd2982e | 2021-07-22 17:41:38 +0200 | [diff] [blame] | 90 | misc_write32(MISC_CLK_CNTL0, ctrl); |
| 91 | } |
| 92 | |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 93 | static void fch_init_acpi_ports(void) |
| 94 | { |
Felix Held | e094b1f | 2021-02-09 22:55:04 +0100 | [diff] [blame] | 95 | u32 reg; |
| 96 | |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 97 | /* We use some of these ports in SMM regardless of whether or not |
| 98 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 99 | */ |
| 100 | |
| 101 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 102 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 103 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 104 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 105 | |
| 106 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Felix Held | e094b1f | 2021-02-09 22:55:04 +0100 | [diff] [blame] | 107 | /* APMC - SMI Command Port */ |
| 108 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
| 109 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
| 110 | |
| 111 | /* SMI on SlpTyp requires sending SMI before completion |
| 112 | response of the I/O write. */ |
| 113 | reg = pm_read32(PM_PCI_CTRL); |
| 114 | reg |= FORCE_SLPSTATE_RETRY; |
| 115 | pm_write32(PM_PCI_CTRL, reg); |
| 116 | |
| 117 | /* Disable SlpTyp feature */ |
| 118 | reg = pm_read8(PM_RST_CTRL1); |
| 119 | reg &= ~SLPTYPE_CONTROL_EN; |
| 120 | pm_write8(PM_RST_CTRL1, reg); |
| 121 | |
| 122 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 123 | } else { |
| 124 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 125 | } |
| 126 | |
| 127 | /* Decode ACPI registers and enable standard features */ |
| 128 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 129 | PM_ACPI_GLOBAL_EN | |
| 130 | PM_ACPI_RTC_EN_EN | |
| 131 | PM_ACPI_TIMER_EN_EN); |
| 132 | } |
| 133 | |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 134 | /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 135 | static void gpp_clk_setup(void) |
| 136 | { |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 137 | struct soc_amd_cezanne_config *cfg = config_of_soc(); |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 138 | |
| 139 | /* look-up table to be able to iterate over the PCIe clock output settings */ |
| 140 | const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { |
| 141 | GPP_CLK0_REQ_SHIFT, |
| 142 | GPP_CLK1_REQ_SHIFT, |
| 143 | GPP_CLK2_REQ_SHIFT, |
| 144 | GPP_CLK3_REQ_SHIFT, |
| 145 | GPP_CLK4_REQ_SHIFT, |
| 146 | GPP_CLK5_REQ_SHIFT, |
| 147 | GPP_CLK6_REQ_SHIFT, |
| 148 | }; |
| 149 | |
| 150 | uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); |
| 151 | |
Robert Zieba | 956432c | 2022-10-25 10:30:14 -0600 | [diff] [blame] | 152 | pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], |
| 153 | ARRAY_SIZE(cfg->gpp_clk_config)); |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 154 | for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { |
| 155 | gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); |
Robert Zieba | e2bde83 | 2022-01-19 14:15:24 -0700 | [diff] [blame] | 156 | |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 157 | /* |
| 158 | * The remapping of values is done so that the default of the enum used for the |
| 159 | * devicetree settings is the clock being enabled, so that a missing devicetree |
| 160 | * configuration for this will result in an always active clock and not an |
| 161 | * inactive PCIe clock output. |
| 162 | */ |
| 163 | switch (cfg->gpp_clk_config[i]) { |
| 164 | case GPP_CLK_REQ: |
| 165 | gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); |
| 166 | break; |
| 167 | case GPP_CLK_OFF: |
| 168 | gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); |
| 169 | break; |
| 170 | case GPP_CLK_ON: |
| 171 | default: |
| 172 | gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); |
| 173 | } |
| 174 | } |
| 175 | |
| 176 | misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); |
| 177 | } |
| 178 | |
Julian Schroeder | 5412a81 | 2021-10-12 10:58:49 -0500 | [diff] [blame] | 179 | static void cgpll_clock_gate_init(void) |
| 180 | { |
| 181 | uint32_t t; |
| 182 | |
| 183 | t = misc_read32(MISC_CLKGATEDCNTL); |
| 184 | t |= ALINKCLK_GATEOFFEN; |
| 185 | t |= BLINKCLK_GATEOFFEN; |
| 186 | t |= XTAL_PAD_S3_TURNOFF_EN; |
| 187 | t |= XTAL_PAD_S5_TURNOFF_EN; |
| 188 | misc_write32(MISC_CLKGATEDCNTL, t); |
| 189 | |
| 190 | t = misc_read32(MISC_CGPLL_CONFIGURATION0); |
| 191 | t |= USB_PHY_CMCLK_S3_DIS; |
| 192 | t |= USB_PHY_CMCLK_S0I3_DIS; |
| 193 | t |= USB_PHY_CMCLK_S5_DIS; |
| 194 | misc_write32(MISC_CGPLL_CONFIGURATION0, t); |
| 195 | |
| 196 | t = pm_read32(PM_ISACONTROL); |
| 197 | t |= ABCLKGATEEN; |
| 198 | pm_write32(PM_ISACONTROL, t); |
| 199 | } |
| 200 | |
Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 201 | void fch_init(void *chip_info) |
| 202 | { |
Martin Roth | 440c823 | 2023-02-01 14:27:18 -0700 | [diff] [blame] | 203 | set_resets_to_cold(); |
Zheng Bao | 7b13e4e | 2021-03-16 16:13:56 +0800 | [diff] [blame] | 204 | i2c_soc_init(); |
Felix Held | 7e703d7 | 2021-02-03 21:38:14 +0100 | [diff] [blame] | 205 | fch_init_acpi_ports(); |
Felix Held | 72b7891 | 2021-04-13 00:08:33 +0200 | [diff] [blame] | 206 | |
| 207 | acpi_pm_gpe_add_events_print_events(); |
| 208 | gpio_add_events(); |
Felix Held | 224b578 | 2021-05-18 01:25:51 +0200 | [diff] [blame] | 209 | |
| 210 | gpp_clk_setup(); |
Felix Held | fd2982e | 2021-07-22 17:41:38 +0200 | [diff] [blame] | 211 | fch_clk_output_48Mhz(); |
Julian Schroeder | 5412a81 | 2021-10-12 10:58:49 -0500 | [diff] [blame] | 212 | cgpll_clock_gate_init(); |
Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | void fch_final(void *chip_info) |
| 216 | { |
| 217 | } |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 218 | |
| 219 | static void set_pci_irqs(void *unused) |
| 220 | { |
| 221 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 222 | write_pci_int_table(); |
Raul E Rangel | fd7ed87 | 2021-05-04 15:42:09 -0600 | [diff] [blame] | 223 | |
| 224 | /* pirq_data is consumed by `write_pci_cfg_irqs` */ |
| 225 | populate_pirq_data(); |
| 226 | |
| 227 | /* Write IRQs for all devicetree enabled devices */ |
| 228 | write_pci_cfg_irqs(); |
Raul E Rangel | a6529e7 | 2021-02-09 14:38:36 -0700 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | /* |
| 232 | * Hook this function into the PCI state machine |
| 233 | * on entry into BS_DEV_ENABLE. |
| 234 | */ |
| 235 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |