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Eric Biedermanc84c1902004-10-14 20:13:01 +00001#ifndef CPU_X86_TSC_H
2#define CPU_X86_TSC_H
3
Stefan Reinauer0db68202012-08-07 14:44:51 -07004#if CONFIG_TSC_SYNC_MFENCE
5#define TSC_SYNC "mfence\n"
6#elif CONFIG_TSC_SYNC_LFENCE
7#define TSC_SYNC "lfence\n"
8#else
9#define TSC_SYNC
10#endif
11
Eric Biedermanc84c1902004-10-14 20:13:01 +000012struct tsc_struct {
13 unsigned lo;
14 unsigned hi;
15};
16typedef struct tsc_struct tsc_t;
17
Stefan Reinauer348a1ba2010-03-17 01:51:11 +000018static inline tsc_t rdtsc(void)
Eric Biedermanc84c1902004-10-14 20:13:01 +000019{
20 tsc_t res;
Stefan Reinauer0db68202012-08-07 14:44:51 -070021 asm volatile (
22 TSC_SYNC
Eric Biedermanc84c1902004-10-14 20:13:01 +000023 "rdtsc"
24 : "=a" (res.lo), "=d"(res.hi) /* outputs */
Stefan Reinauer0db68202012-08-07 14:44:51 -070025 );
Eric Biedermanc84c1902004-10-14 20:13:01 +000026 return res;
27}
28
Stefan Reinauer35b6bbb2010-03-28 21:26:54 +000029#if !defined(__ROMCC__)
30/* Too many registers for ROMCC */
Eric Biedermanc84c1902004-10-14 20:13:01 +000031static inline unsigned long long rdtscll(void)
32{
33 unsigned long long val;
Stefan Reinauer0db68202012-08-07 14:44:51 -070034 asm volatile (
35 TSC_SYNC
36 "rdtsc"
37 : "=A" (val)
38 );
Eric Biedermanc84c1902004-10-14 20:13:01 +000039 return val;
40}
Eric Biedermanc84c1902004-10-14 20:13:01 +000041#endif
42
Aaron Durbin8e73b5d2013-05-01 15:27:09 -050043#if CONFIG_TSC_CONSTANT_RATE
44unsigned long tsc_freq_mhz(void);
45#endif
46
Eric Biedermanc84c1902004-10-14 20:13:01 +000047#endif /* CPU_X86_TSC_H */