Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
York Yang | fc1c1b5 | 2014-11-04 17:04:37 -0700 | [diff] [blame] | 5 | * Copyright (C) 2014 Intel Corporation |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <types.h> |
| 22 | #include <string.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <bootstate.h> |
| 25 | #include <cbmem.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <baytrail/pci_devs.h> |
| 29 | #include <drivers/intel/fsp/fsp_util.h> |
| 30 | #include "../chip.h" |
Mohan D'Costa | ed0c838 | 2014-09-18 15:57:06 +0900 | [diff] [blame] | 31 | #include <arch/io.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 32 | #include <baytrail/reset.h> |
Mohan D'Costa | ed0c838 | 2014-09-18 15:57:06 +0900 | [diff] [blame] | 33 | #include <baytrail/pmc.h> |
| 34 | #include <baytrail/acpi.h> |
| 35 | #include <baytrail/iomap.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 36 | |
| 37 | #ifdef __PRE_RAM__ |
| 38 | #include <baytrail/romstage.h> |
| 39 | #endif |
| 40 | |
| 41 | #ifdef __PRE_RAM__ |
| 42 | |
| 43 | /* Copy the default UPD region and settings to a buffer for modification */ |
| 44 | static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) |
| 45 | { |
| 46 | VPD_DATA_REGION *VpdDataRgnPtr; |
| 47 | UPD_DATA_REGION *UpdDataRgnPtr; |
| 48 | VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase); |
| 49 | UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); |
| 50 | memcpy((void*)UpdData, (void*)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); |
| 51 | } |
| 52 | |
| 53 | /* default to just enabling HDMI audio */ |
| 54 | const PCH_AZALIA_CONFIG mAzaliaConfig = { |
| 55 | .Pme = 1, |
| 56 | .DS = 1, |
| 57 | .DA = 0, |
| 58 | .HdmiCodec = 1, |
| 59 | .AzaliaVCi = 1, |
| 60 | .Rsvdbits = 0, |
| 61 | .AzaliaVerbTableNum = 0, |
| 62 | .AzaliaVerbTable = NULL, |
| 63 | .ResetWaitTimer = 300 |
| 64 | }; |
| 65 | |
| 66 | typedef struct soc_intel_fsp_baytrail_config config_t; |
| 67 | |
| 68 | /** |
| 69 | * Update the UPD data based on values from devicetree.cb |
| 70 | * |
| 71 | * @param UpdData Pointer to the UPD Data structure |
| 72 | */ |
York Yang | fc1c1b5 | 2014-11-04 17:04:37 -0700 | [diff] [blame] | 73 | static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 74 | { |
| 75 | ROMSTAGE_CONST struct device *dev; |
| 76 | ROMSTAGE_CONST config_t *config; |
| 77 | printk(BIOS_DEBUG, "Configure Default UPD Data\n"); |
| 78 | |
| 79 | dev = dev_find_slot(0, SOC_DEV_FUNC); |
| 80 | config = dev->chip_info; |
| 81 | |
| 82 | /* Set up default verb tables - Just HDMI audio */ |
| 83 | UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig; |
| 84 | |
| 85 | /* Set SPD addresses */ |
Martin Roth | 8d936ce | 2014-11-16 20:07:16 -0700 | [diff] [blame^] | 86 | UPD_SPD_CHECK(PcdMrcInitSPDAddr1); |
| 87 | UPD_SPD_CHECK(PcdMrcInitSPDAddr2); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 88 | |
Martin Roth | e8d1901 | 2014-11-16 20:06:23 -0700 | [diff] [blame] | 89 | UPD_DEFAULT_CHECK(PcdSataMode); |
| 90 | UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode); |
| 91 | UPD_DEFAULT_CHECK(PcdMrcInitMmioSize); |
| 92 | UPD_DEFAULT_CHECK(PcdIgdDvmt50PreAlloc); |
| 93 | UPD_DEFAULT_CHECK(PcdApertureSize); |
| 94 | UPD_DEFAULT_CHECK(PcdGttSize); |
| 95 | UPD_DEFAULT_CHECK(SerialDebugPortAddress); |
| 96 | UPD_DEFAULT_CHECK(SerialDebugPortType); |
| 97 | UPD_DEFAULT_CHECK(PcdMrcDebugMsg); |
| 98 | UPD_DEFAULT_CHECK(PcdSccEnablePciMode); |
| 99 | UPD_DEFAULT_CHECK(IgdRenderStandby); |
| 100 | UPD_DEFAULT_CHECK(TxeUmaEnable); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 101 | |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 102 | if ((config->PcdeMMCBootMode != EMMC_USE_DEFAULT) || |
| 103 | (config->PcdeMMCBootMode != EMMC_FOLLOWS_DEVICETREE)) |
| 104 | UpdData->PcdeMMCBootMode = config->PcdeMMCBootMode; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 105 | |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 106 | if (config->PcdMrcInitTsegSize != TSEG_SIZE_DEFAULT) |
Martin Roth | e8d1901 | 2014-11-16 20:06:23 -0700 | [diff] [blame] | 107 | UpdData->PcdMrcInitTsegSize = config->PcdMrcInitTsegSize - 1; |
| 108 | |
| 109 | printk(BIOS_DEBUG, "GTT Size:\t\t%d MB\n", UpdData->PcdGttSize); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 110 | printk(BIOS_DEBUG, "Tseg Size:\t\t%d MB\n", UpdData->PcdMrcInitTsegSize); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 111 | printk(BIOS_DEBUG, "Aperture Size:\t\t%d MB\n", |
| 112 | APERTURE_SIZE_BASE << UpdData->PcdApertureSize); |
Martin Roth | e8d1901 | 2014-11-16 20:06:23 -0700 | [diff] [blame] | 113 | printk(BIOS_DEBUG, "IGD Memory Size:\t%d MB\n", |
| 114 | UpdData->PcdIgdDvmt50PreAlloc * IGD_MEMSIZE_MULTIPLIER); |
| 115 | printk(BIOS_DEBUG, "MMIO Size:\t\t%d MB\n", UpdData->PcdMrcInitMmioSize); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 116 | |
| 117 | /* Advance dev to PCI device 0.0 */ |
| 118 | for (dev = &dev_root; dev; dev = dev_find_next_pci_device(dev)){ |
| 119 | if (dev->path.type != DEVICE_PATH_PCI) |
| 120 | continue; |
| 121 | if (dev->path.pci.devfn == PCI_DEVFN(0x0,0)) |
| 122 | break; |
| 123 | } |
| 124 | |
| 125 | /* |
| 126 | * Loop through all the SOC devices in the devicetree |
| 127 | * enabling and disabling them as requested. |
| 128 | */ |
| 129 | for (; dev; dev = dev->sibling) { |
| 130 | |
| 131 | if (dev->path.type != DEVICE_PATH_PCI) |
| 132 | continue; |
| 133 | |
| 134 | switch (dev->path.pci.devfn) { |
| 135 | case MIPI_DEV_FUNC: /* Camera / Image Signal Processing */ |
York Yang | fc1c1b5 | 2014-11-04 17:04:37 -0700 | [diff] [blame] | 136 | if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { |
| 137 | UpdData->ISPEnable = dev->enabled; |
| 138 | } else { |
| 139 | /* Gold2 and earlier FSP: ISPEnable is the filed */ |
| 140 | /* next to PcdGttSize in UPD_DATA_REGION struct */ |
| 141 | *(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled; |
| 142 | printk (BIOS_DEBUG, |
| 143 | "Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n"); |
| 144 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 145 | printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n", |
| 146 | UpdData->PcdEnableSdio?"Enabled":"Disabled"); |
| 147 | break; |
| 148 | case EMMC_DEV_FUNC: /* EMMC 4.1*/ |
| 149 | if ((dev->enabled) && |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 150 | (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 151 | UpdData->PcdeMMCBootMode = EMMC_4_1 - EMMC_DISABLED; |
| 152 | break; |
| 153 | case SDIO_DEV_FUNC: |
| 154 | UpdData->PcdEnableSdio = dev->enabled; |
| 155 | printk(BIOS_DEBUG, "Sdio:\t\t\t%s\n", |
| 156 | UpdData->PcdEnableSdio?"Enabled":"Disabled"); |
| 157 | break; |
| 158 | case SD_DEV_FUNC: |
| 159 | UpdData->PcdEnableSdcard = dev->enabled; |
| 160 | printk(BIOS_DEBUG, "Sdcard:\t\t\t%s\n", |
| 161 | UpdData->PcdEnableSdcard?"Enabled":"Disabled"); |
| 162 | break; |
| 163 | case SATA_DEV_FUNC: |
| 164 | UpdData->PcdEnableSata = dev->enabled; |
| 165 | printk(BIOS_DEBUG, "Sata:\t\t\t%s\n", |
| 166 | UpdData->PcdEnableSata?"Enabled":"Disabled"); |
| 167 | if (UpdData->PcdEnableSata) |
| 168 | printk(BIOS_DEBUG, "SATA Mode:\t\t%s\n", |
| 169 | UpdData->PcdSataMode?"AHCI":"IDE"); |
| 170 | break; |
| 171 | case XHCI_DEV_FUNC: |
| 172 | UpdData->PcdEnableXhci = dev->enabled; |
| 173 | break; |
| 174 | case LPE_DEV_FUNC: |
| 175 | if (dev->enabled && config->LpeAcpiModeEnable == |
| 176 | LPE_ACPI_MODE_ENABLED) |
| 177 | UpdData->PcdEnableLpe = LPE_ACPI_MODE_ENABLED; |
| 178 | else |
| 179 | UpdData->PcdEnableLpe = dev->enabled; |
| 180 | printk(BIOS_DEBUG, "Lpe:\t\t\t%s\n", |
| 181 | UpdData->PcdEnableLpe?"Enabled":"Disabled"); |
| 182 | printk(BIOS_DEBUG, "Lpe mode:\t\t%s\n", |
| 183 | UpdData->PcdEnableLpe == LPE_ACPI_MODE_ENABLED? |
| 184 | "ACPI":"PCI"); |
| 185 | break; |
| 186 | case MMC45_DEV_FUNC: /* MMC 4.5*/ |
| 187 | if ((dev->enabled) && |
Martin Roth | e55a7c5 | 2014-11-16 17:09:15 -0700 | [diff] [blame] | 188 | (config->PcdeMMCBootMode == EMMC_FOLLOWS_DEVICETREE)) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 189 | UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED; |
| 190 | break; |
| 191 | case SIO_DMA1_DEV_FUNC: |
| 192 | UpdData->PcdEnableDma0 = dev->enabled; |
| 193 | printk(BIOS_DEBUG, "SIO Dma 0:\t\t%s\n", |
| 194 | UpdData->PcdEnableDma0?"Enabled":"Disabled"); |
| 195 | break; |
| 196 | case I2C1_DEV_FUNC: |
| 197 | UpdData->PcdEnableI2C0 = dev->enabled; |
| 198 | printk(BIOS_DEBUG, "SIO I2C0:\t\t%s\n", |
| 199 | UpdData->PcdEnableI2C0?"Enabled":"Disabled"); |
| 200 | break; |
| 201 | case I2C2_DEV_FUNC: |
| 202 | UpdData->PcdEnableI2C1 = dev->enabled; |
| 203 | printk(BIOS_DEBUG, "SIO I2C1:\t\t%s\n", |
| 204 | UpdData->PcdEnableI2C1?"Enabled":"Disabled"); |
| 205 | break; |
| 206 | case I2C3_DEV_FUNC: |
| 207 | UpdData->PcdEnableI2C2 = dev->enabled; |
| 208 | printk(BIOS_DEBUG, "SIO I2C2:\t\t%s\n", |
| 209 | UpdData->PcdEnableI2C2?"Enabled":"Disabled"); |
| 210 | break; |
| 211 | case I2C4_DEV_FUNC: |
| 212 | UpdData->PcdEnableI2C3 = dev->enabled; |
| 213 | printk(BIOS_DEBUG, "SIO I2C3:\t\t%s\n", |
| 214 | UpdData->PcdEnableI2C3?"Enabled":"Disabled"); |
| 215 | break; |
| 216 | case I2C5_DEV_FUNC: |
| 217 | UpdData->PcdEnableI2C4 = dev->enabled; |
| 218 | printk(BIOS_DEBUG, "SIO I2C4:\t\t%s\n", |
| 219 | UpdData->PcdEnableI2C4?"Enabled":"Disabled"); |
| 220 | break; |
| 221 | case I2C6_DEV_FUNC: |
| 222 | UpdData->PcdEnableI2C5 = dev->enabled; |
| 223 | printk(BIOS_DEBUG, "SIO I2C5:\t\t%s\n", |
| 224 | UpdData->PcdEnableI2C5?"Enabled":"Disabled"); |
| 225 | break; |
| 226 | case I2C7_DEV_FUNC: |
| 227 | UpdData->PcdEnableI2C6 = dev->enabled; |
| 228 | printk(BIOS_DEBUG, "SIO I2C6:\t\t%s\n", |
| 229 | UpdData->PcdEnableI2C6?"Enabled":"Disabled"); |
| 230 | break; |
| 231 | case TXE_DEV_FUNC: /* TXE */ |
| 232 | break; |
| 233 | case HDA_DEV_FUNC: |
| 234 | if (config->AzaliaAutoEnable) { |
| 235 | UpdData->PcdEnableAzalia = 2; |
| 236 | printk(BIOS_DEBUG, "Azalia:\t\t\tAuto\n"); |
| 237 | } else { |
| 238 | UpdData->PcdEnableAzalia = dev->enabled; |
| 239 | printk(BIOS_DEBUG, "Azalia:\t\t\t%s\n", |
| 240 | UpdData->PcdEnableAzalia?"Enabled":"Disabled"); |
| 241 | } |
| 242 | break; |
| 243 | case PCIE_PORT1_DEV_FUNC: |
| 244 | case PCIE_PORT2_DEV_FUNC: |
| 245 | case PCIE_PORT3_DEV_FUNC: |
| 246 | case PCIE_PORT4_DEV_FUNC: |
| 247 | break; |
| 248 | case EHCI_DEV_FUNC: |
| 249 | UpdData->PcdEnableXhci = !(dev->enabled); |
| 250 | break; |
| 251 | case SIO_DMA2_DEV_FUNC: |
| 252 | UpdData->PcdEnableDma1 = dev->enabled; |
| 253 | printk(BIOS_DEBUG, "SIO Dma1:\t\t%s\n", |
| 254 | UpdData->PcdEnableDma1?"Enabled":"Disabled"); |
| 255 | break; |
| 256 | case PWM1_DEV_FUNC: |
| 257 | UpdData->PcdEnablePwm0 = dev->enabled; |
| 258 | printk(BIOS_DEBUG, "Pwm0\t\t\t%s\n", |
| 259 | UpdData->PcdEnablePwm0?"Enabled":"Disabled"); |
| 260 | break; |
| 261 | case PWM2_DEV_FUNC: |
| 262 | UpdData->PcdEnablePwm1 = dev->enabled; |
| 263 | printk(BIOS_DEBUG, "Pwm1:\t\t\t%s\n", |
| 264 | UpdData->PcdEnablePwm1?"Enabled":"Disabled"); |
| 265 | break; |
| 266 | case HSUART1_DEV_FUNC: |
| 267 | UpdData->PcdEnableHsuart0 = dev->enabled; |
| 268 | printk(BIOS_DEBUG, "Hsuart0:\t\t%s\n", |
| 269 | UpdData->PcdEnableHsuart0?"Enabled":"Disabled"); |
| 270 | break; |
| 271 | case HSUART2_DEV_FUNC: |
| 272 | UpdData->PcdEnableHsuart1 = dev->enabled; |
| 273 | printk(BIOS_DEBUG, "Hsuart1:\t\t%s\n", |
| 274 | UpdData->PcdEnableHsuart1?"Enabled":"Disabled"); |
| 275 | break; |
| 276 | case SPI_DEV_FUNC: |
| 277 | UpdData->PcdEnableSpi = dev->enabled; |
| 278 | printk(BIOS_DEBUG, "Spi:\t\t\t%s\n", |
| 279 | UpdData->PcdEnableSpi?"Enabled":"Disabled"); |
| 280 | break; |
| 281 | case LPC_DEV_FUNC: /* LPC */ |
| 282 | break; |
| 283 | case SMBUS_DEV_FUNC: |
| 284 | break; |
| 285 | } |
| 286 | } |
| 287 | |
| 288 | if(UpdData->PcdeMMCBootMode == EMMC_AUTO - EMMC_DISABLED) { |
| 289 | printk(BIOS_DEBUG, "eMMC Mode:\t\tAuto"); |
| 290 | } else { |
| 291 | printk(BIOS_DEBUG, "eMMC 4.1:\t\t%s\n", |
| 292 | UpdData->PcdeMMCBootMode == EMMC_4_1 - EMMC_DISABLED? |
| 293 | "Enabled":"Disabled"); |
| 294 | printk(BIOS_DEBUG, "eMMC 4.5:\t\t%s\n", |
| 295 | UpdData->PcdeMMCBootMode == EMMC_4_5 - EMMC_DISABLED? |
| 296 | "Enabled":"Disabled"); |
| 297 | } |
| 298 | printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n", |
| 299 | UpdData->PcdEnableXhci?"Enabled":"Disabled"); |
| 300 | |
York Yang | fc1c1b5 | 2014-11-04 17:04:37 -0700 | [diff] [blame] | 301 | /* set memory down parameters */ |
| 302 | if (config->EnableMemoryDown != MEMORY_DOWN_DEFAULT) { |
| 303 | UpdData->PcdMemoryParameters.EnableMemoryDown |
| 304 | = config->EnableMemoryDown - MEMORY_DOWN_DISABLE; |
| 305 | |
| 306 | if (config->DRAMSpeed != DRAM_SPEED_DEFAULT) { |
| 307 | UpdData->PcdMemoryParameters.DRAMSpeed |
| 308 | = config->DRAMSpeed - DRAM_SPEED_800MHZ; |
| 309 | } |
| 310 | if (config->DRAMType != DRAM_TYPE_DEFAULT) { |
| 311 | UpdData->PcdMemoryParameters.DRAMType |
| 312 | = config->DRAMType - DRAM_TYPE_DDR3; |
| 313 | } |
| 314 | if (config->DIMM0Enable != DIMM0_ENABLE_DEFAULT) { |
| 315 | UpdData->PcdMemoryParameters.DIMM0Enable |
| 316 | = config->DIMM0Enable - DIMM0_DISABLE; |
| 317 | } |
| 318 | if (config->DIMM1Enable != DIMM1_ENABLE_DEFAULT) { |
| 319 | UpdData->PcdMemoryParameters.DIMM1Enable |
| 320 | = config->DIMM1Enable - DIMM1_DISABLE; |
| 321 | } |
| 322 | if (config->DIMMDWidth != DIMM_DWIDTH_DEFAULT) { |
| 323 | UpdData->PcdMemoryParameters.DIMMDWidth |
| 324 | = config->DIMMDWidth - DIMM_DWIDTH_X8; |
| 325 | } |
| 326 | if (config->DIMMDensity != DIMM_DENSITY_DEFAULT) { |
| 327 | UpdData->PcdMemoryParameters.DIMMDensity |
| 328 | = config->DIMMDensity - DIMM_DENSITY_1G_BIT; |
| 329 | } |
| 330 | if (config->DIMMBusWidth != DIMM_BUS_WIDTH_DEFAULT) { |
| 331 | UpdData->PcdMemoryParameters.DIMMBusWidth |
| 332 | = config->DIMMBusWidth - DIMM_BUS_WIDTH_8BIT; |
| 333 | } |
| 334 | if (config->DIMMSides != DIMM_SIDES_DEFAULT) { |
| 335 | UpdData->PcdMemoryParameters.DIMMSides |
| 336 | = config->DIMMSides - DIMM_SIDES_1RANK; |
| 337 | } |
| 338 | if (config->DIMMtCL != DIMM_TCL_DEFAULT) |
| 339 | UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL; |
| 340 | if (config->DIMMtRPtRCD != DIMM_TRP_TRCD_DEFAULT) |
| 341 | UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD; |
| 342 | if (config->DIMMtWR != DIMM_TWR_DEFAULT) |
| 343 | UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR; |
| 344 | if (config->DIMMtWTR != DIMM_TWTR_DEFAULT) |
| 345 | UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR; |
| 346 | if (config->DIMMtRRD != DIMM_TRRD_DEFAULT) |
| 347 | UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD; |
| 348 | if (config->DIMMtRTP != DIMM_TRTP_DEFAULT) |
| 349 | UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP; |
| 350 | if (config->DIMMtFAW != DIMM_TFAW_DEFAULT) |
| 351 | UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW; |
| 352 | |
| 353 | printk (BIOS_DEBUG, |
| 354 | "Memory Down Data Existed : %s\n"\ |
| 355 | "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ |
| 356 | "- Type (0: DDR3, 1: DDR3L) : %d\n"\ |
| 357 | "- DIMM0 : %s\n"\ |
| 358 | "- DIMM1 : %s\n"\ |
| 359 | "- Width : x%d\n"\ |
| 360 | "- Density : %dGbit\n" |
| 361 | "- BudWidth : %dbit\n"\ |
| 362 | "- Rank # : %d\n"\ |
| 363 | "- tCL : %02X\n"\ |
| 364 | "- tRPtRCD : %02X\n"\ |
| 365 | "- tWR : %02X\n"\ |
| 366 | "- tWTR : %02X\n"\ |
| 367 | "- tRRD : %02X\n"\ |
| 368 | "- tRTP : %02X\n"\ |
| 369 | "- tFAW : %02X\n" |
| 370 | , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" |
| 371 | , UpdData->PcdMemoryParameters.DRAMSpeed |
| 372 | , UpdData->PcdMemoryParameters.DRAMType |
| 373 | , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" |
| 374 | , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" |
| 375 | , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) |
| 376 | , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) |
| 377 | , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) |
| 378 | , (UpdData->PcdMemoryParameters.DIMMSides) + 1 |
| 379 | , UpdData->PcdMemoryParameters.DIMMtCL |
| 380 | , UpdData->PcdMemoryParameters.DIMMtRPtRCD |
| 381 | , UpdData->PcdMemoryParameters.DIMMtWR |
| 382 | , UpdData->PcdMemoryParameters.DIMMtWTR |
| 383 | , UpdData->PcdMemoryParameters.DIMMtRRD |
| 384 | , UpdData->PcdMemoryParameters.DIMMtRTP |
| 385 | , UpdData->PcdMemoryParameters.DIMMtFAW |
| 386 | ); |
| 387 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* Set up the Baytrail specific structures for the call into the FSP */ |
| 391 | void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, |
| 392 | FSP_INFO_HEADER *fsp_ptr) |
| 393 | { |
| 394 | FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; |
Mohan D'Costa | ed0c838 | 2014-09-18 15:57:06 +0900 | [diff] [blame] | 395 | uint32_t prev_sleep_state; |
| 396 | |
| 397 | /* Get previous sleep state but don't clear */ |
| 398 | prev_sleep_state = chipset_prev_sleep_state(0); |
| 399 | printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 400 | |
| 401 | /* Initialize the UPD Data */ |
| 402 | GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); |
York Yang | fc1c1b5 | 2014-11-04 17:04:37 -0700 | [diff] [blame] | 403 | ConfigureDefaultUpdData(fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 404 | pFspInitParams->NvsBufferPtr = NULL; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 405 | |
Mohan D'Costa | ed0c838 | 2014-09-18 15:57:06 +0900 | [diff] [blame] | 406 | #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 407 | /* Find the fastboot cache that was saved in the ROM */ |
| 408 | pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); |
| 409 | #endif |
| 410 | |
Mohan D'Costa | ed0c838 | 2014-09-18 15:57:06 +0900 | [diff] [blame] | 411 | if (prev_sleep_state == 3) { |
| 412 | /* S3 resume */ |
| 413 | if ( pFspInitParams->NvsBufferPtr == NULL) { |
| 414 | /* If waking from S3 and no cache then. */ |
| 415 | printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); |
| 416 | post_code(POST_RESUME_FAILURE); |
| 417 | /* Clear Sleep Type */ |
| 418 | outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & |
| 419 | ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); |
| 420 | /* Reboot */ |
| 421 | printk(BIOS_WARNING,"Rebooting..\n" ); |
| 422 | warm_reset(); |
| 423 | /* Should not reach here.. */ |
| 424 | die("Reboot System\n"); |
| 425 | } |
| 426 | pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; |
| 427 | } else { |
| 428 | /* Not S3 resume */ |
| 429 | pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; |
| 430 | } |
| 431 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 432 | return; |
| 433 | } |
| 434 | |
| 435 | /* The FSP returns here after the fsp_early_init call */ |
| 436 | void ChipsetFspReturnPoint(EFI_STATUS Status, |
| 437 | VOID *HobListPtr) |
| 438 | { |
| 439 | if (Status == 0xFFFFFFFF) { |
| 440 | warm_reset(); |
| 441 | } |
| 442 | romstage_main_continue(Status, HobListPtr); |
| 443 | } |
| 444 | |
| 445 | #endif /* __PRE_RAM__ */ |