zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mns3tn.c |
| 6 | * |
| 7 | * TN memory specific function to support S3 resume |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/TN) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | |
| 54 | #include "AGESA.h" |
| 55 | #include "AdvancedApi.h" |
| 56 | #include "amdlib.h" |
| 57 | #include "Ids.h" |
| 58 | #include "OptionMemory.h" |
| 59 | #include "mm.h" |
| 60 | #include "mn.h" |
| 61 | #include "S3.h" |
| 62 | #include "mfs3.h" |
| 63 | #include "mntn.h" |
| 64 | #include "cpuRegisters.h" |
| 65 | #include "cpuFamRegisters.h" |
| 66 | #include "cpuFamilyTranslation.h" |
| 67 | #include "mnS3tn.h" |
| 68 | #include "heapManager.h" |
| 69 | #include "Filecode.h" |
| 70 | CODE_GROUP (G3_DXE) |
| 71 | RDATA_GROUP (G3_DXE) |
| 72 | |
| 73 | #define FILECODE PROC_MEM_NB_TN_MNS3TN_FILECODE |
| 74 | #define DCT0_MEMPSTATE_MASK 0x10 |
| 75 | #define DCT1_MEMPSTATE_MASK 0x20 |
| 76 | #define DO_NOT_CARE 0 |
| 77 | /*---------------------------------------------------------------------------- |
| 78 | * TYPEDEFS AND STRUCTURES |
| 79 | * |
| 80 | *---------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | /*---------------------------------------------------------------------------- |
| 84 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 85 | * |
| 86 | *---------------------------------------------------------------------------- |
| 87 | */ |
| 88 | UINT16 |
| 89 | STATIC |
| 90 | MemNS3GetRegLstPtrTN ( |
| 91 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 92 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 93 | ); |
| 94 | |
| 95 | AGESA_STATUS |
| 96 | STATIC |
| 97 | MemNS3GetDeviceRegLstTN ( |
| 98 | IN UINT32 RegisterLstID, |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 99 | CONST OUT VOID **RegisterHeader |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 100 | ); |
| 101 | |
| 102 | VOID |
| 103 | STATIC |
| 104 | MemNS3SetDfltPhyRegTN ( |
| 105 | IN ACCESS_WIDTH AccessWidth, |
| 106 | IN PCI_ADDR Address, |
| 107 | IN VOID *Value, |
| 108 | IN OUT VOID *ConfigPtr |
| 109 | ); |
| 110 | |
| 111 | VOID |
| 112 | STATIC |
| 113 | MemNS3SetDynModeChangeTN ( |
| 114 | IN ACCESS_WIDTH AccessWidth, |
| 115 | IN PCI_ADDR Address, |
| 116 | IN OUT VOID *Value, |
| 117 | IN OUT VOID *ConfigPtr |
| 118 | ); |
| 119 | |
| 120 | VOID |
| 121 | STATIC |
| 122 | MemNS3SetPhyStatusRegTN ( |
| 123 | IN ACCESS_WIDTH AccessWidth, |
| 124 | IN PCI_ADDR Address, |
| 125 | IN OUT VOID *Value, |
| 126 | IN OUT VOID *ConfigPtr |
| 127 | ); |
| 128 | |
| 129 | VOID |
| 130 | STATIC |
| 131 | MemNS3DisableChannelTN ( |
| 132 | IN ACCESS_WIDTH AccessWidth, |
| 133 | IN PCI_ADDR Address, |
| 134 | IN OUT VOID *Value, |
| 135 | IN OUT VOID *ConfigPtr |
| 136 | ); |
| 137 | |
| 138 | VOID |
| 139 | STATIC |
| 140 | MemNS3GetConPCIMaskTN ( |
| 141 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 142 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 143 | ); |
| 144 | |
| 145 | VOID |
| 146 | STATIC |
| 147 | MemNS3ChangeMemPStateContextAndFlowNb ( |
| 148 | IN ACCESS_WIDTH AccessWidth, |
| 149 | IN PCI_ADDR Address, |
| 150 | IN OUT VOID *Value, |
| 151 | IN OUT VOID *ConfigPtr |
| 152 | ); |
| 153 | |
| 154 | VOID |
| 155 | STATIC |
| 156 | MemNS3GetCSRTN ( |
| 157 | IN ACCESS_WIDTH AccessWidth, |
| 158 | IN PCI_ADDR Address, |
| 159 | IN VOID *Value, |
| 160 | IN OUT VOID *ConfigPtr |
| 161 | ); |
| 162 | |
| 163 | VOID |
| 164 | STATIC |
| 165 | MemNS3SetCSRTN ( |
| 166 | IN ACCESS_WIDTH AccessWidth, |
| 167 | IN PCI_ADDR Address, |
| 168 | IN OUT VOID *Value, |
| 169 | IN OUT VOID *ConfigPtr |
| 170 | ); |
| 171 | |
| 172 | VOID |
| 173 | STATIC |
| 174 | MemNS3SetPhyFenceTN ( |
| 175 | IN ACCESS_WIDTH AccessWidth, |
| 176 | IN PCI_ADDR Address, |
| 177 | IN VOID *Value, |
| 178 | IN OUT VOID *ConfigPtr |
| 179 | ); |
| 180 | BOOLEAN |
| 181 | MemS3ResumeConstructNBBlockTN ( |
| 182 | IN OUT VOID *S3NBPtr, |
| 183 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 184 | IN UINT8 NodeID |
| 185 | ); |
| 186 | |
| 187 | /*---------------------------------------------------------------------------- |
| 188 | * DEFINITIONS AND MACROS |
| 189 | * |
| 190 | *---------------------------------------------------------------------------- |
| 191 | */ |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 192 | CONST PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 193 | {MemNS3GetCSRTN, MemNS3SetCSRTN}, |
| 194 | {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, |
| 195 | {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, |
| 196 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPhyRegTN}, |
| 197 | {MemNS3ChangeMemPStateContextAndFlowNb, MemNS3ChangeMemPStateContextAndFlowNb}, |
| 198 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeTN}, |
| 199 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3DisableChannelTN}, |
| 200 | {MemNS3SaveNBRegiserUnb, MemNS3RestoreNBRegiserUnb}, |
| 201 | {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb}, |
| 202 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegTN}, |
| 203 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb}, |
| 204 | {MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb}, |
| 205 | {MemNS3GetBitFieldNb, MemNS3SetPhyFenceTN}, |
| 206 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb}, |
| 207 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb} |
| 208 | }; |
| 209 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 210 | CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 211 | {{14,3, 1}, DO_NOT_CARE, 0, 0}, |
| 212 | {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7}, |
| 213 | {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, |
| 214 | {{0, 1, 0}, FUNC_1, 0x140, 0x000000FF}, |
| 215 | {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707}, |
| 216 | {{0, 1, 0}, FUNC_1, 0x144, 0x000000FF}, |
| 217 | {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF87}, |
| 218 | {{0, 0, 0}, FUNC_1, 0x120, 0x00FFFFFF}, |
| 219 | {{0, 0, 0}, FUNC_1, 0x124, 0x00FFFFFF}, |
| 220 | {{0, 0, 0}, FUNC_2, 0x10C, 0x07F3FBF9}, |
| 221 | {{0, 0, 0}, FUNC_2, 0x114, 0xFFFFFE00}, |
| 222 | {{0, 0, 0}, FUNC_2, 0x118, 0xFF73FFFF}, |
| 223 | {{0, 0, 0}, FUNC_2, 0x11C, 0xAFFFFFFF}, |
| 224 | {{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F}, |
| 225 | {{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF}, |
| 226 | {{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900}, |
| 227 | }; |
| 228 | |
| 229 | CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = { |
| 230 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 231 | ARRAY_SIZE(S3PciPreSelfRefDescriptorTN), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 232 | S3PciPreSelfRefDescriptorTN, |
| 233 | PciSpecialCaseFuncTN |
| 234 | }; |
| 235 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 236 | CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 237 | // DCT 0 |
| 238 | {{7, 0, 1}, DCT0, 0x40, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 239 | {{7, 0, 1}, DCT0, 0x44, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 240 | {{7, 0, 1}, DCT0, 0x48, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 241 | {{7, 0, 1}, DCT0, 0x4C, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 242 | {{7, 0, 1}, DCT0, 0x50, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 243 | {{7, 0, 1}, DCT0, 0x54, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 244 | {{7, 0, 1}, DCT0, 0x58, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 245 | {{7, 0, 1}, DCT0, 0x5C, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 246 | {{7, 0, 1}, DCT0, 0x60, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 247 | {{7, 0, 1}, DCT0, 0x64, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 248 | {{7, 0, 1}, DCT0, 0x68, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 249 | {{7, 0, 1}, DCT0, 0x6C, 0x7FF8FFE0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 250 | {{7, 0, 1}, DCT0, 0x78, 0x00020000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 251 | {{7, 2, 1}, DCT0, 0x80, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 252 | {{7, 0, 1}, DCT0, 0x84, 0x00800003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 253 | {{7, 0, 1}, DCT0, 0x88, 0x3F000000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 254 | {{7, 0, 1}, DCT0, 0x8C, 0x00070000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 255 | {{7, 0, 1}, DCT0, 0x90, 0x0BF70000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 256 | {{7, 0, 1}, DCT0, 0xA8, 0xBC730024, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 257 | {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 258 | {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 259 | {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 260 | {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 261 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 262 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 263 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 264 | {{2, 0, 1}, DCT0, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT0_NBPSTATE_SUPPORT_MASK, DCT0_ANY_DIMM_MASK}, |
| 265 | {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 266 | {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 267 | {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 268 | {{7, 2, 1}, DCT0, 0x220, 0x00001F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 269 | {{7, 2, 1}, DCT0, 0x224, 0x0000070F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 270 | {{7, 0, 1}, DCT0, 0x228, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 271 | {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 272 | {{7, 0, 1}, DCT0, 0x230, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 273 | {{7, 0, 1}, DCT0, 0x234, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 274 | {{7, 0, 1}, DCT0, 0x238, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 275 | {{7, 0, 1}, DCT0, 0x23C, 0x0F0F0F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 276 | {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 277 | {{7, 1, 1}, DCT0, 0x244, 0x0000000F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 278 | {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 279 | {{7, 0, 1}, DCT0, 0x24C, 0x3F3F3F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 280 | {{7, 0, 1}, DCT0, 0x2E0, 0x5F700000, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 281 | {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 282 | {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 283 | {{7, 1, 1}, DCT0, 0x2F0, 0x00000001, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 284 | {{7, 2, 1}, DCT0, 0x400, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 285 | {{7, 2, 1}, DCT0, 0x404, 0x0000FFFF, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 286 | {{7, 1, 1}, DCT0, 0x408, 0x00000003, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 287 | {{7, 2, 1}, DCT0, 0x420, 0x00000F0F, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 288 | |
| 289 | // DCT 1 |
| 290 | {{7, 0, 1}, DCT1, 0x40, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 291 | {{7, 0, 1}, DCT1, 0x44, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 292 | {{7, 0, 1}, DCT1, 0x48, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 293 | {{7, 0, 1}, DCT1, 0x4C, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 294 | {{7, 0, 1}, DCT1, 0x50, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 295 | {{7, 0, 1}, DCT1, 0x54, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 296 | {{7, 0, 1}, DCT1, 0x58, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 297 | {{7, 0, 1}, DCT1, 0x5C, 0x7FF8FFED, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 298 | {{7, 0, 1}, DCT1, 0x60, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 299 | {{7, 0, 1}, DCT1, 0x64, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 300 | {{7, 0, 1}, DCT1, 0x68, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 301 | {{7, 0, 1}, DCT1, 0x6C, 0x7FF8FFE0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 302 | {{7, 0, 1}, DCT1, 0x78, 0x00020000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 303 | {{7, 2, 1}, DCT1, 0x80, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 304 | {{7, 0, 1}, DCT1, 0x84, 0x00800003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 305 | {{7, 0, 1}, DCT1, 0x88, 0x3F000000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 306 | {{7, 0, 1}, DCT1, 0x8C, 0x00070000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 307 | {{7, 0, 1}, DCT1, 0x90, 0x0BF70000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 308 | {{7, 0, 1}, DCT1, 0xA8, 0xBC730024, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 309 | {{7, 0, 1}, DCT1, 0x200, 0x3F1F1F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 310 | {{7, 0, 1}, DCT1, 0x204, 0x0F3F0F3F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 311 | {{7, 0, 1}, DCT1, 0x208, 0x07070707, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 312 | {{7, 0, 1}, DCT1, 0x20C, 0x00030F1F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 313 | {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 0), 0xFFC7000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 314 | {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 1), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, |
| 315 | {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 2), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, |
| 316 | {{2, 0, 1}, DCT1, SET_S3_NB_PSTATE_OFFSET (0x210, 3), 0xFFC7000F, DCT1_NBPSTATE_SUPPORT_MASK, DCT1_ANY_DIMM_MASK}, |
| 317 | {{7, 0, 1}, DCT1, 0x214, 0x000F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 318 | {{7, 0, 1}, DCT1, 0x218, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 319 | {{7, 0, 1}, DCT1, 0x21C, 0x001F1F00, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 320 | {{7, 2, 1}, DCT1, 0x220, 0x00001F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 321 | {{7, 2, 1}, DCT1, 0x224, 0x0000070F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 322 | {{7, 0, 1}, DCT1, 0x228, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 323 | {{7, 1, 1}, DCT1, 0x22C, 0x0000001F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 324 | {{7, 0, 1}, DCT1, 0x230, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 325 | {{7, 0, 1}, DCT1, 0x234, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 326 | {{7, 0, 1}, DCT1, 0x238, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 327 | {{7, 0, 1}, DCT1, 0x23C, 0x0F0F0F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 328 | {{7, 2, 1}, DCT1, 0x240, 0x000077FF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 329 | {{7, 1, 1}, DCT1, 0x244, 0x0000000F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 330 | {{7, 0, 1}, DCT1, 0x248, 0xBF3F1F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 331 | {{7, 0, 1}, DCT1, 0x24C, 0x3F3F3F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 332 | {{7, 0, 1}, DCT1, 0x2E0, 0x5F700000, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 333 | {{7, 0, 1}, DCT1, 0x2E8, 0xFFFFFFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 334 | {{7, 2, 1}, DCT1, 0x2EC, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 335 | {{7, 1, 1}, DCT1, 0x2F0, 0x00000001, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 336 | {{7, 2, 1}, DCT1, 0x400, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 337 | {{7, 2, 1}, DCT1, 0x404, 0x0000FFFF, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 338 | {{7, 1, 1}, DCT1, 0x408, 0x00000003, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 339 | {{7, 2, 1}, DCT1, 0x420, 0x00000F0F, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 340 | |
| 341 | // Phy Initialization |
| 342 | // 1. Program D18F2x9C_x0D0F_E013_dct[1:0] = 0118h. |
| 343 | {{1, 2, 1}, DCT0, BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 344 | {{1, 2, 1}, DCT1, BFPllRegWaitTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 345 | // 2. Force the phy to M0 with the following sequence: |
| 346 | // A. Program D18F2x9C_x0D0F_E006_dct[1:0][PllLockTime] = 190h. |
| 347 | {{3, 3, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 348 | {{3, 3, 1}, DCT1, BFPllLockTime, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 349 | // B. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80800000h. |
| 350 | {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 351 | {{9, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 352 | // C. Program D18F2x9C_x0D0F_E018_dct[0][PhyPSMasterChannel] = 0. |
| 353 | {{3, 3, 1}, DCT0, BFPhyPSMasterChannel, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 354 | // D. Program D18F2x9C_x0000_000B_dct[0] = 40000000h. |
| 355 | // E. For each DCT: Program D18F2x9C_x0000_000B_dct[1:0] = 80000000h |
| 356 | {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 357 | {{5, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0B), 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 358 | |
| 359 | // 3. Phy voltage related |
| 360 | {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 361 | {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 362 | {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000, DCT0_MASK, ANY_DIMM_MASK}, |
| 363 | {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 364 | {{1, 1, 1}, DCT0, BFCsrComparator, 0x0000000C, DCT0_MASK, ANY_DIMM_MASK}, |
| 365 | {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018, DCT0_MASK, ANY_DIMM_MASK}, |
| 366 | {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, |
| 367 | {{1, 1, 1}, DCT1, BFClkRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, |
| 368 | {{1, 2, 1}, DCT1, BFCmpVioLvl, 0x0000C000, DCT1_MASK, ANY_DIMM_MASK}, |
| 369 | {{1, 1, 1}, DCT1, BFCmdRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, |
| 370 | {{1, 1, 1}, DCT1, BFAddrRxVioLvl, 0x00000018, DCT1_MASK, ANY_DIMM_MASK}, |
| 371 | |
| 372 | // 4. Frequency Change |
| 373 | // Check if a channel needs to be disabled |
| 374 | {{1, 1, 1}, DCT0, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 375 | {{6, 3, 1}, DCT0, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 376 | {{1, 1, 1}, DCT1, BFCKETri, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 377 | {{6, 3, 1}, DCT1, 0, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 378 | {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 379 | {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 380 | {{1, 1, 1}, DCT1, BFPhyClkConfig0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 381 | {{1, 1, 1}, DCT1, BFPhyClkConfig1, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 382 | |
| 383 | {{7, 0, 1}, DCT0, 0x94, 0x9FF9CC1F, DCT0_MASK, ANY_DIMM_MASK}, |
| 384 | {{7, 0, 1}, DCT1, 0x94, 0x9FF9CC1F, DCT1_MASK, ANY_DIMM_MASK}, |
| 385 | |
| 386 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, |
| 387 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, |
| 388 | {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 389 | {{1, 2, 1}, DCT1, BFProcOdtAdv, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 390 | {{1, 2, 1}, DCT0, BFSkewMemClk, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 391 | {{1, 2, 1}, DCT1, BFSkewMemClk, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 392 | |
| 393 | // Enable MemClk |
| 394 | {{10, 0, 1}, DCT0, 0x94, 0, DCT0_MASK, DCT0_ANY_DIMM_MASK}, |
| 395 | {{10, 0, 1}, DCT1, 0x94, 0, DCT1_MASK, DCT1_ANY_DIMM_MASK}, |
| 396 | {{1, 2, 1}, DCT0, BFPllLockTime, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 397 | {{1, 2, 1}, DCT1, BFPllLockTime, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 398 | |
| 399 | // DCT 0 |
| 400 | // 5. Phy Fence |
| 401 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 402 | {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 403 | {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MASK, ANY_DIMM_MASK}, |
| 404 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MASK, ANY_DIMM_MASK}, |
| 405 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MASK, ANY_DIMM_MASK}, |
| 406 | // 6. Phy Compensation Init |
| 407 | {{3, 3, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 408 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 409 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 410 | {{8, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 411 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 412 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 413 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 414 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 415 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 416 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 417 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 418 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 419 | {{8, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 420 | {{8, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 421 | {{8, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 422 | {{8, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 423 | {{8, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 424 | {{8, 2, 1}, DCT0, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 425 | |
| 426 | // DCT 1 |
| 427 | // 5. Phy Fence |
| 428 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MASK, ANY_DIMM_MASK}, |
| 429 | {{1, 2, 1}, DCT1, BFDataFence2, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 430 | {{1, 2, 1}, DCT1, BFFence2, 0x00007C1F, DCT1_MASK, ANY_DIMM_MASK}, |
| 431 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MASK, ANY_DIMM_MASK}, |
| 432 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MASK, ANY_DIMM_MASK}, |
| 433 | // 6. Phy Compensation Init |
| 434 | {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 435 | {{1, 2, 1}, DCT1, BFDataByteTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 436 | {{8, 2, 1}, DCT1, BFDataByteTxPreDriverCal, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 437 | {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 438 | {{1, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 439 | {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 440 | {{1, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 441 | {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad1, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 442 | {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad2, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 443 | {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad3, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 444 | {{1, 2, 1}, DCT1, BFAddrTxPreDriverCal2Pad4, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 445 | {{8, 2, 1}, DCT1, BFCmdAddr0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 446 | {{8, 2, 1}, DCT1, BFCmdAddr1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 447 | {{8, 2, 1}, DCT1, BFAddrTxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 448 | {{8, 2, 1}, DCT1, BFClock0TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 449 | {{8, 2, 1}, DCT1, BFClock1TxPreDriverCalPad0, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 450 | {{8, 2, 1}, DCT1, BFClock2TxPreDriverCalPad0, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 451 | |
| 452 | {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MASK + DCT1_MASK, ANY_DIMM_MASK}, |
| 453 | |
| 454 | // Program MemPstate 1 registers |
| 455 | // Switch to MemPstate context 1 |
| 456 | {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 457 | {{1, 1, 1}, DCT0, BFRate, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 458 | {{1, 1, 1}, DCT1, BFRate, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 459 | {{1, 2, 1}, DCT0, BFProcOdtAdv, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 460 | {{1, 2, 1}, DCT1, BFProcOdtAdv, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 461 | {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 462 | {{1, 1, 1}, DCT1, BFDataRxVioLvl, 0x00000018, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 463 | {{7, 0, 1}, DCT0, 0x200, 0x3F1F1F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 464 | {{7, 0, 1}, DCT0, 0x204, 0x0F3F0F3F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 465 | {{7, 0, 1}, DCT0, 0x208, 0x07070707, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 466 | {{7, 0, 1}, DCT0, 0x20C, 0x00030F1F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 467 | {{7, 0, 1}, DCT0, 0x214, 0x000F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 468 | {{7, 0, 1}, DCT0, 0x218, 0x0F0F0F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 469 | {{7, 0, 1}, DCT0, 0x21C, 0x001F1F00, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 470 | {{7, 1, 1}, DCT0, 0x22C, 0x0000001F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 471 | {{7, 2, 1}, DCT0, 0x240, 0x000077FF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 472 | {{7, 0, 1}, DCT0, 0x248, 0xBF3F1F0F, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 473 | {{7, 0, 1}, DCT0, 0x2E8, 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 474 | {{7, 2, 1}, DCT0, 0x2EC, 0x0000FFFF, DCT0_MEMPSTATE_MASK, DCT0_ANY_DIMM_MASK}, |
| 475 | {{7, 0, 1}, DCT1, 0x200, 0x3F1F1F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 476 | {{7, 0, 1}, DCT1, 0x204, 0x0F3F0F3F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 477 | {{7, 0, 1}, DCT1, 0x208, 0x07070707, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 478 | {{7, 0, 1}, DCT1, 0x20C, 0x00030F1F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 479 | {{7, 0, 1}, DCT1, 0x214, 0x000F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 480 | {{7, 0, 1}, DCT1, 0x218, 0x0F0F0F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 481 | {{7, 0, 1}, DCT1, 0x21C, 0x001F1F00, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 482 | {{7, 1, 1}, DCT1, 0x22C, 0x0000001F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 483 | {{7, 2, 1}, DCT1, 0x240, 0x000077FF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 484 | {{7, 0, 1}, DCT1, 0x248, 0xBF3F1F0F, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 485 | {{7, 0, 1}, DCT1, 0x2E8, 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 486 | {{7, 2, 1}, DCT1, 0x2EC, 0x0000FFFF, DCT1_MEMPSTATE_MASK, DCT1_ANY_DIMM_MASK}, |
| 487 | // Compute Phy fence for MemPstate 1 |
| 488 | // DCT 0 |
| 489 | {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 490 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 491 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 492 | // DCT 1 |
| 493 | {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 494 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x04), 0x003F3F3F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 495 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x00), 0x70777777, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 496 | |
| 497 | {{1, 1, 1}, DCT0, BFDisablePredriverCal, 0, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 498 | // Switch back to MemPstate context 0 |
| 499 | {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 500 | |
| 501 | // Set Fence back to Fence of M0 to prepare for fine delay restore for M0 |
| 502 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 503 | {{1, 2, 1}, DCT0, BFDataFence2, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 504 | {{1, 2, 1}, DCT0, BFFence2, 0x00007C1F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 505 | |
| 506 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0C), 0x7FFF0FFF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 507 | {{1, 2, 1}, DCT1, BFDataFence2, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 508 | {{1, 2, 1}, DCT1, BFFence2, 0x00007C1F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK} |
| 509 | }; |
| 510 | |
| 511 | CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = { |
| 512 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 513 | ARRAY_SIZE(S3CPciPreSelfDescriptorTN), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 514 | S3CPciPreSelfDescriptorTN, |
| 515 | PciSpecialCaseFuncTN |
| 516 | }; |
| 517 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 518 | CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 519 | // DCT0 |
| 520 | {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 521 | {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 522 | {{1, 1, 1}, DCT0, BFRxBypass3rd4thStg, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 523 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 524 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 525 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 526 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 527 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 528 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 529 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 530 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 531 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 532 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01}, |
| 533 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 534 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MASK, 0x04}, |
| 535 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 536 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MASK, 0x10}, |
| 537 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 538 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40}, |
| 539 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
| 540 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
| 541 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
| 542 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
| 543 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10}, |
| 544 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10}, |
| 545 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40}, |
| 546 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40}, |
| 547 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 548 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 549 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 550 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 551 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MASK, 0x10}, |
| 552 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MASK, 0x10}, |
| 553 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MASK, 0x40}, |
| 554 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40}, |
| 555 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 556 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 557 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 558 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 559 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 560 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 561 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 562 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 563 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 564 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01}, |
| 565 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 566 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MASK, 0x04}, |
| 567 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 568 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MASK, 0x10}, |
| 569 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 570 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MASK, 0x40}, |
| 571 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, |
| 572 | {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, |
| 573 | {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 574 | {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 575 | {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 576 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 577 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 578 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 579 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 580 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 581 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 582 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 583 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MASK, ANY_DIMM_MASK}, |
| 584 | |
| 585 | // DCT1 |
| 586 | {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 587 | {{1, 2, 1}, DCT1, BFRx4thStgEn, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 588 | {{1, 1, 1}, DCT1, BFRxBypass3rd4thStg, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 589 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x03FF03FF, DCT1_MASK, 0x02}, |
| 590 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x03FF03FF, DCT1_MASK, 0x02}, |
| 591 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x03FF03FF, DCT1_MASK, 0x08}, |
| 592 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x03FF03FF, DCT1_MASK, 0x08}, |
| 593 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x03FF03FF, DCT1_MASK, 0x20}, |
| 594 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x03FF03FF, DCT1_MASK, 0x20}, |
| 595 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x03FF03FF, DCT1_MASK, 0x80}, |
| 596 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x03FF03FF, DCT1_MASK, 0x80}, |
| 597 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x03FF03FF, DCT1_MASK, 0x02}, |
| 598 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x03FF03FF, DCT1_MASK, 0x02}, |
| 599 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x03FF03FF, DCT1_MASK, 0x08}, |
| 600 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x03FF03FF, DCT1_MASK, 0x08}, |
| 601 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x03FF03FF, DCT1_MASK, 0x20}, |
| 602 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x03FF03FF, DCT1_MASK, 0x20}, |
| 603 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x03FF03FF, DCT1_MASK, 0x80}, |
| 604 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x03FF03FF, DCT1_MASK, 0x80}, |
| 605 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MASK, 0x02}, |
| 606 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MASK, 0x02}, |
| 607 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MASK, 0x08}, |
| 608 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MASK, 0x08}, |
| 609 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MASK, 0x20}, |
| 610 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MASK, 0x20}, |
| 611 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MASK, 0x80}, |
| 612 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MASK, 0x80}, |
| 613 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MASK, 0x02}, |
| 614 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MASK, 0x02}, |
| 615 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MASK, 0x08}, |
| 616 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MASK, 0x08}, |
| 617 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MASK, 0x20}, |
| 618 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MASK, 0x20}, |
| 619 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MASK, 0x80}, |
| 620 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MASK, 0x80}, |
| 621 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_MASK, 0x02}, |
| 622 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_MASK, 0x02}, |
| 623 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_MASK, 0x08}, |
| 624 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_MASK, 0x08}, |
| 625 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_MASK, 0x20}, |
| 626 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_MASK, 0x20}, |
| 627 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_MASK, 0x80}, |
| 628 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_MASK, 0x80}, |
| 629 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_MASK, 0x02}, |
| 630 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_MASK, 0x02}, |
| 631 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_MASK, 0x08}, |
| 632 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_MASK, 0x08}, |
| 633 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_MASK, 0x20}, |
| 634 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_MASK, 0x20}, |
| 635 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_MASK, 0x80}, |
| 636 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_MASK, 0x80}, |
| 637 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MASK, ANY_DIMM_MASK}, |
| 638 | {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13, 0x00000083, DCT1_MASK, ANY_DIMM_MASK}, |
| 639 | {{1, 2, 1}, DCT1, BFRxSsbMntClkEn, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 640 | {{1, 2, 1}, DCT1, BFLowPowerDrvStrengthEn, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 641 | {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 642 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 643 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 644 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 645 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 646 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 647 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 648 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 649 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MASK, ANY_DIMM_MASK}, |
| 650 | |
| 651 | {{11, 3, 1}, DO_NOT_CARE, 1, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 652 | |
| 653 | // DCT0 |
| 654 | {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 655 | {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 656 | {{1, 1, 1}, DCT0, BFRxBypass3rd4thStg, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 657 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 658 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 659 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 660 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 661 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 662 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 663 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 664 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 665 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 666 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 667 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 668 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 669 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x26), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 670 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x27), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 671 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x29), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 672 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 673 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 674 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 675 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 676 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 677 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 678 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 679 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 680 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 681 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, |
| 682 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01}, |
| 683 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, |
| 684 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04}, |
| 685 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x205), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, |
| 686 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x206), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x10}, |
| 687 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x305), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, |
| 688 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40}, |
| 689 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 690 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 691 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 692 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 693 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 694 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 695 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 696 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 697 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 698 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01}, |
| 699 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 700 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04}, |
| 701 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x46), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 702 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x47), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10}, |
| 703 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x49), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 704 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x4A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40}, |
| 705 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 706 | {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13, 0x00000083, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 707 | {{1, 2, 1}, DCT0, BFRxSsbMntClkEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 708 | {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 709 | {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 710 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 711 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 712 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 713 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 714 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 715 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 716 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 717 | {{1, 2, 1}, DCT0, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 718 | |
| 719 | // DCT1 |
| 720 | {{12, 2, 1}, DCT1, BFChBM1FenceSave, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 721 | {{1, 2, 1}, DCT1, BFRx4thStgEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 722 | {{1, 1, 1}, DCT1, BFRxBypass3rd4thStg, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 723 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x10), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 724 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x11), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 725 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x13), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 726 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x14), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 727 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x16), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 728 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x17), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 729 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x19), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 730 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x1A), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 731 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x20), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 732 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x21), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 733 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x23), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 734 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x24), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 735 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x26), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 736 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x27), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 737 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x29), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 738 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x2A), 0x03FF03FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 739 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x01), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 740 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x02), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 741 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x101), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 742 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x102), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 743 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x201), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 744 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x202), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 745 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x301), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 746 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x302), 0xFFFFFFFF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 747 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x05), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02}, |
| 748 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x06), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x02}, |
| 749 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x105), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08}, |
| 750 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x106), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x08}, |
| 751 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x205), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20}, |
| 752 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x206), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x20}, |
| 753 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x305), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80}, |
| 754 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x306), 0x3E3E3E3E, DCT1_MEMPSTATE_MASK, 0x80}, |
| 755 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x30), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 756 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x31), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 757 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x33), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 758 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x34), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 759 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x36), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 760 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x37), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 761 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x39), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 762 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x3A), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 763 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x40), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 764 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x41), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x02}, |
| 765 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x43), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 766 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x44), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x08}, |
| 767 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x46), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 768 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x47), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x20}, |
| 769 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x49), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 770 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x4A), 0x00FF00FF, DCT1_MEMPSTATE_MASK, 0x80}, |
| 771 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 1, 0x0D), 0x037F037F, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 772 | {{1, 1, 1}, DCT1, BFPhy0x0D0F0F13, 0x00000083, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 773 | {{1, 2, 1}, DCT1, BFRxSsbMntClkEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 774 | {{1, 2, 1}, DCT1, BFLowPowerDrvStrengthEn, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 775 | {{1, 2, 1}, DCT1, BFEnRxPadStandby, 0, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 776 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte0, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 777 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte1, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 778 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte2, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 779 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte3, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 780 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte4, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 781 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte5, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 782 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte6, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 783 | {{1, 2, 1}, DCT1, BFDataByteDllPowerMgnByte7, 0xBFBF, DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 784 | |
| 785 | {{11, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, DCT0_MEMPSTATE_MASK + DCT1_MEMPSTATE_MASK, ANY_DIMM_MASK}, |
| 786 | |
| 787 | {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000A1, DCT0_MASK, ANY_DIMM_MASK}, |
| 788 | {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0, DCT0_MASK, ANY_DIMM_MASK}, |
| 789 | {{1, 1, 1}, DCT1, BFAddrCmdTri, 0x0000000A1, DCT1_MASK, ANY_DIMM_MASK}, |
| 790 | {{1, 1, 1}, DCT1, BFDisDllShutdownSR, 0, DCT1_MASK, ANY_DIMM_MASK}, |
| 791 | |
| 792 | {{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 793 | {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK}, |
| 794 | |
| 795 | {{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK} |
| 796 | }; |
| 797 | |
| 798 | CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = { |
| 799 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 800 | ARRAY_SIZE(S3CPciPostSelfDescriptorTN), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 801 | S3CPciPostSelfDescriptorTN, |
| 802 | PciSpecialCaseFuncTN |
| 803 | }; |
| 804 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 805 | CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 806 | {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, |
| 807 | {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, |
| 808 | {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, |
| 809 | {{0, 0, 0}, 0xC001001F, 0x0044601080000600} |
| 810 | }; |
| 811 | |
| 812 | CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = { |
| 813 | 0, |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 814 | ARRAY_SIZE(S3MSRPreSelfRefDescriptorTN), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 815 | S3MSRPreSelfRefDescriptorTN, |
| 816 | NULL |
| 817 | }; |
| 818 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 819 | CONST VOID * CONST MemS3RegListTN[] = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 820 | (VOID *)&S3PciPreSelfRefTN, |
| 821 | NULL, |
| 822 | (VOID *)&S3CPciPreSelfRefTN, |
| 823 | (VOID *)&S3CPciPostSelfRefTN, |
| 824 | (VOID *)&S3MSRPreSelfRefTN, |
| 825 | NULL, |
| 826 | NULL, |
| 827 | NULL |
| 828 | }; |
| 829 | |
| 830 | /*---------------------------------------------------------------------------- |
| 831 | * EXPORTED FUNCTIONS |
| 832 | * |
| 833 | *---------------------------------------------------------------------------- |
| 834 | */ |
| 835 | /* -----------------------------------------------------------------------------*/ |
| 836 | /** |
| 837 | * |
| 838 | * |
| 839 | * This function initializes the northbridge block for S3 resume |
| 840 | * |
| 841 | * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. |
| 842 | * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. |
| 843 | * @param[in] NodeID - Node ID of the target node. |
| 844 | * |
| 845 | * @return BOOLEAN |
| 846 | * TRUE - This is the correct constructor for the targeted node. |
| 847 | * FALSE - This isn't the correct constructor for the targeted node. |
| 848 | */ |
| 849 | BOOLEAN |
| 850 | MemS3ResumeConstructNBBlockTN ( |
| 851 | IN OUT VOID *S3NBPtr, |
| 852 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 853 | IN UINT8 NodeID |
| 854 | ) |
| 855 | { |
| 856 | INT32 i; |
| 857 | MEM_NB_BLOCK *NBPtr; |
| 858 | |
| 859 | NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; |
| 860 | |
| 861 | // |
| 862 | // Determine if this is the expected NB Type |
| 863 | // |
| 864 | GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); |
| 865 | if (!MemNIsIdSupportedTN (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { |
| 866 | return FALSE; |
| 867 | } |
| 868 | |
| 869 | NBPtr->MemPtr = MemPtr; |
| 870 | NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); |
| 871 | NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; |
| 872 | MemNInitNBRegTableTN (NBPtr, NBPtr->NBRegTable); |
| 873 | NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; |
| 874 | NBPtr->Dct = 0; |
| 875 | NBPtr->Channel = 0; |
| 876 | NBPtr->Ganged = FALSE; |
| 877 | NBPtr->NodeCount = MAX_NODES_SUPPORTED_TN; |
| 878 | NBPtr->DctCount = MAX_DCTS_PER_NODE_TN; |
| 879 | NBPtr->MemPstate = MEMORY_PSTATE0; |
| 880 | NBPtr->MemPstateStage = 0; |
| 881 | NBPtr->NbPsCtlReg = 0; |
| 882 | |
| 883 | NBPtr->IsSupported[SetDllShutDown] = TRUE; |
| 884 | |
| 885 | for (i = 0; i < EnumSize; i++) { |
| 886 | NBPtr->IsSupported[i] = FALSE; |
| 887 | } |
| 888 | |
| 889 | for (i = 0; i < NumberOfHooks; i++) { |
| 890 | NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; |
| 891 | } |
| 892 | |
| 893 | LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); |
| 894 | |
| 895 | NBPtr->SwitchDCT = MemNSwitchDCTNb; |
| 896 | NBPtr->SwitchChannel = MemNSwitchChannelNb; |
| 897 | NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldTN; |
| 898 | NBPtr->GetBitField = MemNGetBitFieldNb; |
| 899 | NBPtr->SetBitField = MemNSetBitFieldNb; |
| 900 | NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedTN; |
| 901 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; |
| 902 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskTN; |
| 903 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; |
| 904 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeUNb; |
| 905 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet; |
| 906 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrTN; |
| 907 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstTN; |
| 908 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; |
| 909 | NBPtr->FamilySpecificHook[DCTSelectSwitch] = MemNS3DctCfgSelectUnb; |
| 910 | |
| 911 | MemNSetBitFieldNb (NBPtr, BFDctCfgSel, 0); |
| 912 | MemNSwitchDCTNb (NBPtr, 0); |
| 913 | MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0); |
| 914 | |
| 915 | if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) != 1) { |
| 916 | NBPtr->MemPstateStage = MEMORY_PSTATE_S3_STAGE; |
| 917 | MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0); |
| 918 | } |
| 919 | |
| 920 | return TRUE; |
| 921 | } |
| 922 | |
| 923 | /*---------------------------------------------------------------------------- |
| 924 | * LOCAL FUNCTIONS |
| 925 | * |
| 926 | *----------------------------------------------------------------------------*/ |
| 927 | |
| 928 | /* -----------------------------------------------------------------------------*/ |
| 929 | /** |
| 930 | * |
| 931 | * |
| 932 | * This function returns the register list for each device for TN |
| 933 | * |
| 934 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 935 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 936 | * @return UINT16 - size of the device descriptor on the target node. |
| 937 | */ |
| 938 | UINT16 |
| 939 | STATIC |
| 940 | MemNS3GetRegLstPtrTN ( |
| 941 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 942 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 943 | ) |
| 944 | { |
| 945 | UINT8 i; |
| 946 | UINT16 Size; |
| 947 | Size = 0; |
| 948 | for (i = PRESELFREF; i <= POSTSELFREF; i ++) { |
| 949 | DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); |
| 950 | DescriptPtr->PCIDevice[i].Node = NBPtr->Node; |
| 951 | DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 952 | if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[PCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { |
| 953 | DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_TN + i; |
| 954 | Size += sizeof (PCI_DEVICE_DESCRIPTOR); |
| 955 | } |
| 956 | DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); |
| 957 | DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; |
| 958 | DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 959 | if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CPCI_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { |
| 960 | DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_TN + i; |
| 961 | Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); |
| 962 | } |
| 963 | DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); |
| 964 | DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 965 | if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[MSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { |
| 966 | DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_TN + i; |
| 967 | Size += sizeof (MSR_DEVICE_DESCRIPTOR); |
| 968 | } |
| 969 | DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); |
| 970 | DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 971 | if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListTN[CMSR_LST_ESR_TN - PCI_LST_ESR_TN + i] != NULL) { |
| 972 | DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_TN + i; |
| 973 | Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); |
| 974 | } |
| 975 | } |
| 976 | return Size; |
| 977 | } |
| 978 | |
| 979 | /* -----------------------------------------------------------------------------*/ |
| 980 | /** |
| 981 | * |
| 982 | * |
| 983 | * This function return the register list according to the register ID. |
| 984 | * |
| 985 | * @param[in] RegisterLstID - value of the Register list ID. |
| 986 | * @param[out] **RegisterHeader - pointer to the address of the register list. |
| 987 | * @return AGESA_STATUS |
| 988 | * - AGESA_FATAL |
| 989 | * - AGESA_SUCCESS |
| 990 | */ |
| 991 | AGESA_STATUS |
| 992 | STATIC |
| 993 | MemNS3GetDeviceRegLstTN ( |
| 994 | IN UINT32 RegisterLstID, |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 995 | CONST OUT VOID **RegisterHeader |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 996 | ) |
| 997 | { |
| 998 | if (RegisterLstID >= (sizeof (MemS3RegListTN) / sizeof (VOID *))) { |
| 999 | ASSERT(FALSE); // RegisterListID exceeded size of Register list |
| 1000 | return AGESA_FATAL; |
| 1001 | } |
| 1002 | if (MemS3RegListTN[RegisterLstID] != NULL) { |
| 1003 | *RegisterHeader = MemS3RegListTN[RegisterLstID]; |
| 1004 | return AGESA_SUCCESS; |
| 1005 | } |
| 1006 | ASSERT(FALSE); // Device register list error |
| 1007 | return AGESA_FATAL; |
| 1008 | } |
| 1009 | |
| 1010 | /* -----------------------------------------------------------------------------*/ |
| 1011 | /** |
| 1012 | * |
| 1013 | * |
| 1014 | * This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation. |
| 1015 | * |
| 1016 | * @param[in] AccessWidth - Access width of the register. |
| 1017 | * @param[in] Address - address in PCI_ADDR format. |
| 1018 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1019 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1020 | * @return none |
| 1021 | */ |
| 1022 | VOID |
| 1023 | STATIC |
| 1024 | MemNS3SetDfltPhyRegTN ( |
| 1025 | IN ACCESS_WIDTH AccessWidth, |
| 1026 | IN PCI_ADDR Address, |
| 1027 | IN VOID *Value, |
| 1028 | IN OUT VOID *ConfigPtr |
| 1029 | ) |
| 1030 | { |
| 1031 | UINT16 RegValue; |
| 1032 | BIT_FIELD_NAME BitField; |
| 1033 | |
| 1034 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 1035 | BitField = (BIT_FIELD_NAME) Address.Address.Register; |
| 1036 | RegValue = 0; |
| 1037 | |
| 1038 | if (BitField == BFPllLockTime) { |
| 1039 | RegValue = 0x190; |
| 1040 | } else if (BitField == BFPhyPSMasterChannel) { |
| 1041 | } else if (BitField == BFDisablePredriverCal) { |
| 1042 | RegValue = 3; |
| 1043 | } else { |
| 1044 | ASSERT (FALSE); |
| 1045 | } |
| 1046 | MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); |
| 1047 | } |
| 1048 | } |
| 1049 | |
| 1050 | /* -----------------------------------------------------------------------------*/ |
| 1051 | /** |
| 1052 | * |
| 1053 | * |
| 1054 | * This function sets bit 31 [DynModeChange] of F2x9C_xB |
| 1055 | * |
| 1056 | * @param[in] AccessWidth - Access width of the register. |
| 1057 | * @param[in] Address - address in PCI_ADDR format. |
| 1058 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1059 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1060 | * @return none |
| 1061 | */ |
| 1062 | VOID |
| 1063 | STATIC |
| 1064 | MemNS3SetDynModeChangeTN ( |
| 1065 | IN ACCESS_WIDTH AccessWidth, |
| 1066 | IN PCI_ADDR Address, |
| 1067 | IN OUT VOID *Value, |
| 1068 | IN OUT VOID *ConfigPtr |
| 1069 | ) |
| 1070 | { |
| 1071 | UINT32 RegValue; |
| 1072 | |
| 1073 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 1074 | if ((Address.Address.Register & 0x400) == 0) { |
| 1075 | RegValue = 0x40000000; |
| 1076 | MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 1077 | } |
| 1078 | RegValue = 0x80000000; |
| 1079 | MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 1080 | } |
| 1081 | } |
| 1082 | |
| 1083 | /* -----------------------------------------------------------------------------*/ |
| 1084 | /** |
| 1085 | * |
| 1086 | * |
| 1087 | * This function sets F2x9C_xB to 0x80800000 |
| 1088 | * |
| 1089 | * @param[in] AccessWidth - Access width of the register. |
| 1090 | * @param[in] Address - address in PCI_ADDR format. |
| 1091 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1092 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1093 | * @return none |
| 1094 | */ |
| 1095 | VOID |
| 1096 | STATIC |
| 1097 | MemNS3SetPhyStatusRegTN ( |
| 1098 | IN ACCESS_WIDTH AccessWidth, |
| 1099 | IN PCI_ADDR Address, |
| 1100 | IN OUT VOID *Value, |
| 1101 | IN OUT VOID *ConfigPtr |
| 1102 | ) |
| 1103 | { |
| 1104 | UINT32 RegValue; |
| 1105 | |
| 1106 | IDS_SKIP_HOOK (IDS_BEFORE_S3_SPECIAL, &Address, ConfigPtr) { |
| 1107 | RegValue = 0x80800000; |
| 1108 | MemNS3SetCSRTN (AccessS3SaveWidth32, Address, &RegValue, ConfigPtr); |
| 1109 | } |
| 1110 | } |
| 1111 | |
| 1112 | /* -----------------------------------------------------------------------------*/ |
| 1113 | /** |
| 1114 | * |
| 1115 | * |
| 1116 | * This function does the channel disable sequence |
| 1117 | * |
| 1118 | * @param[in] AccessWidth - Access width of the register. |
| 1119 | * @param[in] Address - address in PCI_ADDR format. |
| 1120 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1121 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1122 | * @return none |
| 1123 | */ |
| 1124 | VOID |
| 1125 | STATIC |
| 1126 | MemNS3DisableChannelTN ( |
| 1127 | IN ACCESS_WIDTH AccessWidth, |
| 1128 | IN PCI_ADDR Address, |
| 1129 | IN OUT VOID *Value, |
| 1130 | IN OUT VOID *ConfigPtr |
| 1131 | ) |
| 1132 | { |
| 1133 | MEM_NB_BLOCK *NBPtr; |
| 1134 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 1135 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 1136 | UINT32 RegValue; |
| 1137 | UINT8 Die; |
| 1138 | |
| 1139 | // See which Node should be accessed |
| 1140 | Die = (UINT8) (Address.Address.Device - 24); |
| 1141 | |
| 1142 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 1143 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 1144 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 1145 | NBPtr = S3NBPtr[Die].NBPtr; |
| 1146 | |
| 1147 | // Function field contains the DCT number |
| 1148 | NBPtr->SwitchDCT (NBPtr, (UINT8) Address.Address.Function); |
| 1149 | RegValue = MemNGetBitFieldNb (NBPtr, BFCKETri); |
| 1150 | // if CKETri is 0b1111, this channel is disabled |
| 1151 | if (RegValue == 0xF) { |
| 1152 | //Wait for 24 MEMCLKs, which is 60ns under 400MHz |
| 1153 | MemFS3Wait10ns (6, NBPtr->MemPtr); |
| 1154 | MemNSetBitFieldNb (NBPtr, BFMemClkDis, 0xFF); |
| 1155 | MemNSetBitFieldNb (NBPtr, BFDisDramInterface, 1); |
| 1156 | if (NBPtr->Dct == 0) { |
| 1157 | MemNSetBitFieldNb (NBPtr, BFPhyPSMasterChannel, 0x100); |
| 1158 | } |
| 1159 | } |
| 1160 | } |
| 1161 | } |
| 1162 | |
| 1163 | /* -----------------------------------------------------------------------------*/ |
| 1164 | /** |
| 1165 | * |
| 1166 | * |
| 1167 | * This function changes memory Pstate context |
| 1168 | * |
| 1169 | * @param[in] AccessWidth - Access width of the register. |
| 1170 | * @param[in] Address - address in PCI_ADDR format. |
| 1171 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1172 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1173 | * |
| 1174 | * @return TRUE |
| 1175 | * ---------------------------------------------------------------------------- |
| 1176 | */ |
| 1177 | VOID |
| 1178 | STATIC |
| 1179 | MemNS3ChangeMemPStateContextAndFlowNb ( |
| 1180 | IN ACCESS_WIDTH AccessWidth, |
| 1181 | IN PCI_ADDR Address, |
| 1182 | IN OUT VOID *Value, |
| 1183 | IN OUT VOID *ConfigPtr |
| 1184 | ) |
| 1185 | { |
| 1186 | MEM_NB_BLOCK *NBPtr; |
| 1187 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 1188 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 1189 | UINT8 Die; |
| 1190 | |
| 1191 | // See which Node should be accessed |
| 1192 | Die = (UINT8) (Address.Address.Device - 24); |
| 1193 | |
| 1194 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 1195 | |
| 1196 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 1197 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 1198 | NBPtr = S3NBPtr[Die].NBPtr; |
| 1199 | if (NBPtr->MemPstate == MEMORY_PSTATE0) { |
| 1200 | // If MemoryPstate is not disabled, switch to MemPState 1 context, and reprocess the register list |
| 1201 | MemNChangeMemPStateContextNb (NBPtr, 1); |
| 1202 | *(UINT32 *) Value = RESTART_FROM_BEGINNING_LIST; |
| 1203 | } else { |
| 1204 | // Switch back to MemPstate0 Context |
| 1205 | MemNChangeMemPStateContextNb (NBPtr, 0); |
| 1206 | } |
| 1207 | } |
| 1208 | } |
| 1209 | |
| 1210 | /* -----------------------------------------------------------------------------*/ |
| 1211 | /** |
| 1212 | * |
| 1213 | * |
| 1214 | * This function returns the conditional PCI device mask |
| 1215 | * |
| 1216 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 1217 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 1218 | * @return none |
| 1219 | */ |
| 1220 | VOID |
| 1221 | STATIC |
| 1222 | MemNS3GetConPCIMaskTN ( |
| 1223 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 1224 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 1225 | ) |
| 1226 | { |
| 1227 | BIT_FIELD_NAME bitfield; |
| 1228 | UINT32 RegVal; |
| 1229 | UINT8 DCT; |
| 1230 | UINT8 DimmMask; |
| 1231 | UINT8 BadDimmMask; |
| 1232 | UINT8 NbPsCapMsk; |
| 1233 | UINT8 MemPstateMsk; |
| 1234 | UINT8 CsPerDelay; |
| 1235 | |
| 1236 | NbPsCapMsk = 0; |
| 1237 | MemPstateMsk = 0; |
| 1238 | DimmMask = 0; |
| 1239 | BadDimmMask = 0; |
| 1240 | CsPerDelay = 1; |
| 1241 | |
| 1242 | for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { |
| 1243 | MemNSwitchDCTNb (NBPtr, DCT); |
| 1244 | if (MemNGetBitFieldNb (NBPtr, BFMemClkFreqVal)) { |
| 1245 | if (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn) == 0) { |
| 1246 | CsPerDelay = 2; |
| 1247 | } |
| 1248 | for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr7Reg; bitfield ++) { |
| 1249 | RegVal = MemNGetBitFieldNb (NBPtr, bitfield); |
| 1250 | if (RegVal & 0x1) { |
| 1251 | DimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); |
| 1252 | } else if (RegVal & 0x4) { |
| 1253 | BadDimmMask |= (UINT8) (1 << ((((bitfield - BFCSBaseAddr0Reg) / CsPerDelay) << 1) + DCT)); |
| 1254 | } |
| 1255 | } |
| 1256 | } |
| 1257 | } |
| 1258 | // Check if the system is capable of doing NB Pstate change |
| 1259 | if (MemNGetBitFieldNb (NBPtr, BFNbPstateDis) == 0) { |
| 1260 | NbPsCapMsk = DCT0_NBPSTATE_SUPPORT_MASK; |
| 1261 | } |
| 1262 | if (MemNGetBitFieldNb (NBPtr, BFMemPstateDis) == 0) { |
| 1263 | MemPstateMsk = DCT0_MEMPSTATE_MASK; |
| 1264 | } |
| 1265 | |
| 1266 | MemNSwitchDCTNb (NBPtr, 0); |
| 1267 | // Set channel mask |
| 1268 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 0; |
| 1269 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 0; |
| 1270 | for (DCT = 0; DCT < NBPtr->DctCount; DCT ++) { |
| 1271 | if (DimmMask & (0x55 << DCT)) { |
| 1272 | // Set mask before exit self refresh |
| 1273 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; |
| 1274 | // Set mask after exit self refresh |
| 1275 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (NbPsCapMsk | MemPstateMsk | 1) << DCT; |
| 1276 | } else if (BadDimmMask & (0x55 << DCT)) { |
| 1277 | // Need to save function 2 registers for bad dimm |
| 1278 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 |= 1 << DCT; |
| 1279 | } |
| 1280 | } |
| 1281 | |
| 1282 | // Set dimm mask |
| 1283 | DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; |
| 1284 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; |
| 1285 | } |
| 1286 | |
| 1287 | /* -----------------------------------------------------------------------------*/ |
| 1288 | /** |
| 1289 | * |
| 1290 | * |
| 1291 | * This function read the value of CSR register. |
| 1292 | * |
| 1293 | * @param[in] AccessWidth - Access width of the register |
| 1294 | * @param[in] Address - address of the CSR register in PCI_ADDR format. |
| 1295 | * @param[in] *Value - Pointer to the value be read. |
| 1296 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1297 | * @return none |
| 1298 | */ |
| 1299 | VOID |
| 1300 | STATIC |
| 1301 | MemNS3GetCSRTN ( |
| 1302 | IN ACCESS_WIDTH AccessWidth, |
| 1303 | IN PCI_ADDR Address, |
| 1304 | IN VOID *Value, |
| 1305 | IN OUT VOID *ConfigPtr |
| 1306 | ) |
| 1307 | { |
| 1308 | UINT8 TempValue; |
| 1309 | UINT8 Dct; |
| 1310 | UINT32 ExtendOffset; |
| 1311 | UINT32 TempFunc; |
| 1312 | |
| 1313 | ExtendOffset = Address.Address.Register; |
| 1314 | TempFunc = Address.Address.Function; |
| 1315 | |
| 1316 | // Switch Dct |
| 1317 | Address.Address.Function = FUNC_1; |
| 1318 | Address.Address.Register = 0x10C; |
| 1319 | Dct = 0; |
| 1320 | if (ExtendOffset & 0x400) { |
| 1321 | Dct = 1; |
| 1322 | } |
| 1323 | LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1324 | TempValue = (TempValue & 0xFE) | Dct; |
| 1325 | LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1326 | Address.Address.Function = TempFunc; |
| 1327 | |
| 1328 | Address.Address.Register = 0x98; |
| 1329 | ExtendOffset &= 0x3FF; |
| 1330 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); |
| 1331 | IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); |
| 1332 | Address.Address.Register = 0x9C; |
| 1333 | LibAmdPciRead (AccessWidth, Address, Value, ConfigPtr); |
| 1334 | } |
| 1335 | |
| 1336 | /* -----------------------------------------------------------------------------*/ |
| 1337 | /** |
| 1338 | * |
| 1339 | * |
| 1340 | * This function write to a CSR register |
| 1341 | * |
| 1342 | * @param[in] AccessWidth - Access width of the register |
| 1343 | * @param[in] Address - address of the CSR register in PCI_ADDR format. |
| 1344 | * @param[in, out] *Value - Pointer to the value be read. |
| 1345 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1346 | * @return none |
| 1347 | */ |
| 1348 | VOID |
| 1349 | STATIC |
| 1350 | MemNS3SetCSRTN ( |
| 1351 | IN ACCESS_WIDTH AccessWidth, |
| 1352 | IN PCI_ADDR Address, |
| 1353 | IN OUT VOID *Value, |
| 1354 | IN OUT VOID *ConfigPtr |
| 1355 | ) |
| 1356 | { |
| 1357 | UINT8 TempValue; |
| 1358 | UINT8 Dct; |
| 1359 | UINT32 ExtendOffset; |
| 1360 | UINT32 ValueWrite; |
| 1361 | UINT32 TempFunc; |
| 1362 | |
| 1363 | ExtendOffset = Address.Address.Register; |
| 1364 | |
| 1365 | TempFunc = Address.Address.Function; |
| 1366 | // Switch Dct |
| 1367 | Address.Address.Function = FUNC_1; |
| 1368 | Address.Address.Register = 0x10C; |
| 1369 | Dct = 0; |
| 1370 | if (ExtendOffset & 0x400) { |
| 1371 | Dct = 1; |
| 1372 | } |
| 1373 | LibAmdPciRead (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1374 | TempValue = (TempValue & 0xFE) | Dct; |
| 1375 | LibAmdPciWrite (AccessS3SaveWidth8, Address, &TempValue, ConfigPtr); |
| 1376 | |
| 1377 | Address.Address.Function = TempFunc; |
| 1378 | Address.Address.Register = 0x9C; |
| 1379 | |
| 1380 | ExtendOffset &= 0x3FF; |
| 1381 | ExtendOffset |= 0x40000000; |
| 1382 | switch (AccessWidth) { |
| 1383 | case AccessS3SaveWidth8: |
| 1384 | ValueWrite = *(UINT8 *) Value; |
| 1385 | break; |
| 1386 | case AccessS3SaveWidth16: |
| 1387 | ValueWrite = *(UINT16 *) Value; |
| 1388 | break; |
| 1389 | case AccessS3SaveWidth32: |
| 1390 | ValueWrite = *(UINT32 *) Value; |
| 1391 | break; |
| 1392 | default: |
| 1393 | ASSERT (FALSE); |
| 1394 | } |
| 1395 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ValueWrite, ConfigPtr); |
| 1396 | Address.Address.Register = 0x98; |
| 1397 | LibAmdPciWrite (AccessS3SaveWidth32, Address, &ExtendOffset, ConfigPtr); |
| 1398 | IDS_OPTION_HOOK (IDS_AFTER_DCT_PHY_ACCESS, NULL, ConfigPtr); |
| 1399 | } |
| 1400 | |
| 1401 | /* -----------------------------------------------------------------------------*/ |
| 1402 | /** |
| 1403 | * |
| 1404 | * |
| 1405 | * This function that set PllLockTime or PhyPSMasterChannel or disable auto compensation. |
| 1406 | * |
| 1407 | * @param[in] AccessWidth - Access width of the register. |
| 1408 | * @param[in] Address - address in PCI_ADDR format. |
| 1409 | * @param[in, out] *Value - Pointer to the value to be written. |
| 1410 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 1411 | * @return none |
| 1412 | */ |
| 1413 | VOID |
| 1414 | STATIC |
| 1415 | MemNS3SetPhyFenceTN ( |
| 1416 | IN ACCESS_WIDTH AccessWidth, |
| 1417 | IN PCI_ADDR Address, |
| 1418 | IN VOID *Value, |
| 1419 | IN OUT VOID *ConfigPtr |
| 1420 | ) |
| 1421 | { |
| 1422 | UINT16 FenceValue; |
| 1423 | UINT16 Fence2Data; |
| 1424 | UINT16 Fence2Reg; |
| 1425 | BIT_FIELD_NAME BitField; |
| 1426 | MEM_NB_BLOCK *NBPtr; |
| 1427 | LOCATE_HEAP_PTR LocateBufferPtr; |
| 1428 | S3_MEM_NB_BLOCK *S3NBPtr; |
| 1429 | |
| 1430 | BitField = (BIT_FIELD_NAME) Address.Address.Register; |
| 1431 | FenceValue = *(UINT16 *) Value; |
| 1432 | // See which Node should be accessed |
| 1433 | |
| 1434 | LocateBufferPtr.BufferHandle = AMD_MEM_S3_NB_HANDLE; |
| 1435 | |
| 1436 | if (HeapLocateBuffer (&LocateBufferPtr, ConfigPtr) == AGESA_SUCCESS) { |
| 1437 | S3NBPtr = (S3_MEM_NB_BLOCK *) LocateBufferPtr.BufferPtr; |
| 1438 | NBPtr = S3NBPtr[0].NBPtr; |
| 1439 | |
| 1440 | // Do nothing if currently in memory pstate 0 context |
| 1441 | if (NBPtr->MemPstate == MEMORY_PSTATE0) { |
| 1442 | return; |
| 1443 | } |
| 1444 | |
| 1445 | if (BitField == BFChAM1FenceSave) { |
| 1446 | MemNSwitchDCTNb (NBPtr, 0); |
| 1447 | } else { |
| 1448 | MemNSwitchDCTNb (NBPtr, 1); |
| 1449 | } |
| 1450 | MAKE_TSEFO (NBPtr->NBRegTable, DCT_PHY_ACCESS, 0x0C, 30, 16, BFPhyFence); |
| 1451 | MemNSetBitFieldNb (NBPtr, BFPhyFence, FenceValue); |
| 1452 | |
| 1453 | // Program Fence 2 for MState 1 |
| 1454 | Fence2Data = 0; |
| 1455 | if ((FenceValue & 0x1F) < 16) { |
| 1456 | Fence2Data |= (FenceValue & 0x1F) | 0x10; |
| 1457 | } |
| 1458 | if (((FenceValue >> 5) & 0x1F) < 16) { |
| 1459 | Fence2Data |= (((FenceValue >> 5) & 0x1F) | 0x10) << 10; |
| 1460 | } |
| 1461 | if (((FenceValue >> 10) & 0x1F) < 16) { |
| 1462 | Fence2Data |= (((FenceValue >> 10) & 0x1F) | 0x10) << 5; |
| 1463 | } |
| 1464 | MemNSetBitFieldNb (NBPtr, BFDataFence2, Fence2Data); |
| 1465 | |
| 1466 | // Program another Fence 2 register for Mstate 1 |
| 1467 | Fence2Reg = (UINT16) MemNGetBitFieldNb (NBPtr, BFFence2); |
| 1468 | Fence2Reg = (Fence2Reg &~(UINT16) ((0x1F << 10) | 0x1F)) | (Fence2Data & 0x1F) | (((Fence2Data >> 5) & 0x1F) << 10); |
| 1469 | MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg); |
| 1470 | } |
| 1471 | } |