zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Family specific PCIe configuration data definition |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "Gnb.h" |
| 53 | #include "GnbPcie.h" |
| 54 | #include "GnbPcieFamServices.h" |
| 55 | #include "PcieComplexDataTN.h" |
| 56 | #include "Filecode.h" |
| 57 | #define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIECOMPLEXDATATN_FILECODE |
| 58 | /*---------------------------------------------------------------------------------------- |
| 59 | * D E F I N I T I O N S A N D M A C R O S |
| 60 | *---------------------------------------------------------------------------------------- |
| 61 | */ |
| 62 | |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * T Y P E D E F S A N D S T R U C T U R E S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
| 75 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 76 | CONST TN_COMPLEX_CONFIG ComplexDataTN = { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 77 | //Silicon |
| 78 | { |
| 79 | { |
| 80 | DESCRIPTOR_SILICON | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, |
| 81 | 0, |
| 82 | 0, |
| 83 | offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon) |
| 84 | }, |
| 85 | 0, |
| 86 | 0 |
| 87 | }, |
| 88 | //Gfx Wrapper |
| 89 | { |
| 90 | { |
| 91 | DESCRIPTOR_PCIE_WRAPPER | DESCRIPTOR_DDI_WRAPPER, |
| 92 | offsetof (TN_COMPLEX_CONFIG, GfxWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), |
| 93 | offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 94 | offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper) |
| 95 | }, |
| 96 | |
| 97 | GFX_WRAP_ID, |
| 98 | GFX_NUMBER_OF_PIFs, |
| 99 | GFX_START_PHY_LANE, |
| 100 | GFX_END_PHY_LANE, |
| 101 | GFX_CORE_ID, |
| 102 | GFX_CORE_ID, |
| 103 | 16, |
| 104 | { |
| 105 | 1, //PowerOffUnusedLanesEnabled, |
| 106 | 1, //PowerOffUnusedPllsEnabled |
| 107 | 1, //ClkGating |
| 108 | 1, //LclkGating |
| 109 | 1, //TxclkGatingPllPowerDown |
| 110 | 1, //PllOffInL1 |
| 111 | 0 //AccessEncoding |
| 112 | }, |
| 113 | }, |
| 114 | //Gpp Wrapper |
| 115 | { |
| 116 | { |
| 117 | DESCRIPTOR_PCIE_WRAPPER, |
| 118 | offsetof (TN_COMPLEX_CONFIG, GppWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), |
| 119 | offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 120 | offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper) |
| 121 | }, |
| 122 | GPP_WRAP_ID, |
| 123 | GPP_NUMBER_OF_PIFs, |
| 124 | GPP_START_PHY_LANE, |
| 125 | GPP_END_PHY_LANE, |
| 126 | GPP_CORE_ID, |
| 127 | GPP_CORE_ID, |
| 128 | 8, |
| 129 | { |
| 130 | 1, //PowerOffUnusedLanesEnabled, |
| 131 | 1, //PowerOffUnusedPllsEnabled |
| 132 | 1, //ClkGating |
| 133 | 1, //LclkGating |
| 134 | 1, //TxclkGatingPllPowerDown |
| 135 | 1, //PllOffInL1 |
| 136 | 0 //AccessEncoding |
| 137 | }, |
| 138 | }, |
| 139 | //DDI Wrapper |
| 140 | { |
| 141 | { |
| 142 | DESCRIPTOR_DDI_WRAPPER, |
| 143 | offsetof (TN_COMPLEX_CONFIG, DdiWrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), |
| 144 | offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), |
| 145 | offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper) |
| 146 | }, |
| 147 | DDI_WRAP_ID, |
| 148 | DDI_NUMBER_OF_PIFs, |
| 149 | DDI_START_PHY_LANE, |
| 150 | DDI_END_PHY_LANE, |
| 151 | 0xf, |
| 152 | 0x0, |
| 153 | 8, |
| 154 | { |
| 155 | 1, //PowerOffUnusedLanesEnabled, |
| 156 | 1, //PowerOffUnusedPllsEnabled |
| 157 | 1, //ClkGating |
| 158 | 1, //LclkGating |
| 159 | 1, //TxclkGatingPllPowerDown |
| 160 | 0, //PllOffInL1 |
| 161 | 0 //AccessEncoding |
| 162 | }, |
| 163 | }, |
| 164 | //DDI2 Wrapper |
| 165 | { |
| 166 | { |
| 167 | DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, |
| 168 | offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) - offsetof (TN_COMPLEX_CONFIG, Silicon), |
| 169 | 0, |
| 170 | offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper) |
| 171 | }, |
| 172 | DDI2_WRAP_ID, |
| 173 | DDI2_NUMBER_OF_PIFs, |
| 174 | DDI2_START_PHY_LANE, |
| 175 | DDI2_END_PHY_LANE, |
| 176 | 0xf, |
| 177 | 0x0, |
| 178 | 8, |
| 179 | { |
| 180 | 1, //PowerOffUnusedLanesEnabled, |
| 181 | 1, //PowerOffUnusedPllsEnabled |
| 182 | 1, //ClkGating |
| 183 | 1, //LclkGating |
| 184 | 1, //TxclkGatingPllPowerDown |
| 185 | 0, //PllOffInL1 |
| 186 | 0 //AccessEncoding |
| 187 | }, |
| 188 | }, |
| 189 | //Port 2 |
| 190 | { |
| 191 | { |
| 192 | DESCRIPTOR_PCIE_ENGINE, |
| 193 | offsetof (TN_COMPLEX_CONFIG, Port2) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 194 | offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, Port2), |
| 195 | 0 |
| 196 | }, |
| 197 | { PciePortEngine, 8, 23}, |
| 198 | 0, //Initialization Status |
| 199 | 0xFF, //Scratch |
| 200 | { |
| 201 | { |
| 202 | {0}, |
| 203 | 0, |
| 204 | 15, |
| 205 | 2, |
| 206 | 0, |
| 207 | GFX_CORE_ID, |
| 208 | 0, |
| 209 | {0}, |
| 210 | LinkStateResetExit, |
| 211 | 0, |
| 212 | 2, |
| 213 | 1 |
| 214 | }, |
| 215 | }, |
| 216 | }, |
| 217 | //Port 3 |
| 218 | { |
| 219 | { |
| 220 | DESCRIPTOR_PCIE_ENGINE, |
| 221 | offsetof (TN_COMPLEX_CONFIG, Port3) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 222 | offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, Port3), |
| 223 | 0 |
| 224 | }, |
| 225 | { PciePortEngine, UNUSED_LANE_ID, UNUSED_LANE_ID }, |
| 226 | 0, //Initialization Status |
| 227 | 0xFF, //Scratch |
| 228 | { |
| 229 | { |
| 230 | {0}, |
| 231 | UNUSED_LANE_ID, |
| 232 | UNUSED_LANE_ID, |
| 233 | 3, |
| 234 | 0, |
| 235 | GFX_CORE_ID, |
| 236 | 1, |
| 237 | {0}, |
| 238 | LinkStateResetExit, |
| 239 | 1, |
| 240 | 3, |
| 241 | 1 |
| 242 | }, |
| 243 | }, |
| 244 | }, |
| 245 | //DdiB |
| 246 | { |
| 247 | { |
| 248 | DESCRIPTOR_DDI_ENGINE, |
| 249 | offsetof (TN_COMPLEX_CONFIG, DpB) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 250 | offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, DpB), |
| 251 | 0 |
| 252 | }, |
| 253 | {PcieDdiEngine}, |
| 254 | 0, //Initialization Status |
| 255 | 0xFF //Scratch |
| 256 | }, |
| 257 | //DdiC |
| 258 | { |
| 259 | { |
| 260 | DESCRIPTOR_DDI_ENGINE, |
| 261 | offsetof (TN_COMPLEX_CONFIG, DpC) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 262 | offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, DpC), |
| 263 | 0 |
| 264 | }, |
| 265 | {PcieDdiEngine}, |
| 266 | 0, //Initialization Status |
| 267 | 0xFF //Scratch |
| 268 | }, |
| 269 | //DdiD |
| 270 | { |
| 271 | { |
| 272 | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, |
| 273 | offsetof (TN_COMPLEX_CONFIG, DpD) - offsetof (TN_COMPLEX_CONFIG, GfxWrapper), |
| 274 | offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, DpD), |
| 275 | 0 |
| 276 | }, |
| 277 | {PcieDdiEngine}, |
| 278 | 0, //Initialization Status |
| 279 | 0xFF //Scratch |
| 280 | }, |
| 281 | |
| 282 | //Port 4 |
| 283 | { |
| 284 | { |
| 285 | DESCRIPTOR_PCIE_ENGINE, |
| 286 | offsetof (TN_COMPLEX_CONFIG, Port4) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 287 | offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, Port4), |
| 288 | 0 |
| 289 | }, |
| 290 | { PciePortEngine, 4, 4}, |
| 291 | 0, //Initialization Status |
| 292 | 0xFF, //Scratch |
| 293 | { |
| 294 | { |
| 295 | {0}, |
| 296 | 4, |
| 297 | 4, |
| 298 | 4, |
| 299 | 0, |
| 300 | GPP_CORE_ID, |
| 301 | 1, |
| 302 | {0}, |
| 303 | LinkStateResetExit, |
| 304 | 2, |
| 305 | 0, |
| 306 | 0 |
| 307 | }, |
| 308 | }, |
| 309 | }, |
| 310 | //Port 5 |
| 311 | { |
| 312 | { |
| 313 | DESCRIPTOR_PCIE_ENGINE, |
| 314 | offsetof (TN_COMPLEX_CONFIG, Port5) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 315 | offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, Port5), |
| 316 | 0 |
| 317 | }, |
| 318 | { PciePortEngine, 5, 5}, |
| 319 | 0, //Initialization Status |
| 320 | 0xFF, //Scratch |
| 321 | { |
| 322 | { |
| 323 | {0}, |
| 324 | 5, |
| 325 | 5, |
| 326 | 5, |
| 327 | 0, |
| 328 | GPP_CORE_ID, |
| 329 | 2, |
| 330 | {0}, |
| 331 | LinkStateResetExit, |
| 332 | 3, |
| 333 | 0, |
| 334 | 0 |
| 335 | }, |
| 336 | }, |
| 337 | }, |
| 338 | //Port 6 |
| 339 | { |
| 340 | { |
| 341 | DESCRIPTOR_PCIE_ENGINE, |
| 342 | offsetof (TN_COMPLEX_CONFIG, Port6) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 343 | offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, Port6), |
| 344 | 0 |
| 345 | }, |
| 346 | { PciePortEngine, 6, 6 }, |
| 347 | 0, //Initialization Status |
| 348 | 0xFF, //Scratch |
| 349 | { |
| 350 | { |
| 351 | {0}, |
| 352 | 6, |
| 353 | 6, |
| 354 | 6, |
| 355 | 0, |
| 356 | GPP_CORE_ID, |
| 357 | 3, |
| 358 | {0}, |
| 359 | LinkStateResetExit, |
| 360 | 4, |
| 361 | 0, |
| 362 | 0 |
| 363 | }, |
| 364 | }, |
| 365 | }, |
| 366 | //Port 7 |
| 367 | { |
| 368 | { |
| 369 | DESCRIPTOR_PCIE_ENGINE, |
| 370 | offsetof (TN_COMPLEX_CONFIG, Port7) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 371 | offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, Port7), |
| 372 | 0 |
| 373 | }, |
| 374 | { PciePortEngine, 7, 7 }, |
| 375 | 0, //Initialization Status |
| 376 | 0xFF, //Scratch |
| 377 | { |
| 378 | { |
| 379 | {0}, |
| 380 | 7, |
| 381 | 7, |
| 382 | 7, |
| 383 | 0, |
| 384 | GPP_CORE_ID, |
| 385 | 4, |
| 386 | {0}, |
| 387 | LinkStateResetExit, |
| 388 | 5, |
| 389 | 0, |
| 390 | 0 |
| 391 | }, |
| 392 | }, |
| 393 | }, |
| 394 | //Port 8 |
| 395 | { |
| 396 | { |
| 397 | DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, |
| 398 | offsetof (TN_COMPLEX_CONFIG, Port8) - offsetof (TN_COMPLEX_CONFIG, GppWrapper), |
| 399 | offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, Port8), |
| 400 | 0 |
| 401 | }, |
| 402 | { PciePortEngine, 0, 3 }, |
| 403 | INIT_STATUS_PCIE_TRAINING_SUCCESS, //Initialization Status |
| 404 | 0xFF, //Scratch |
| 405 | { |
| 406 | { |
| 407 | {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, |
| 408 | 0, |
| 409 | 3, |
| 410 | 8, |
| 411 | 0, |
| 412 | GPP_CORE_ID, |
| 413 | 0, |
| 414 | {MAKE_SBDFO (0, 0, 8, 0, 0)}, |
| 415 | LinkStateTrainingSuccess, |
| 416 | 6, |
| 417 | 0, |
| 418 | 0 |
| 419 | }, |
| 420 | }, |
| 421 | }, |
| 422 | //DpE |
| 423 | { |
| 424 | { |
| 425 | DESCRIPTOR_DDI_ENGINE, |
| 426 | offsetof (TN_COMPLEX_CONFIG, DpE) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), |
| 427 | offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DpE), |
| 428 | 0 |
| 429 | }, |
| 430 | {PcieDdiEngine}, |
| 431 | 0, //Initialization Status |
| 432 | 0xFF //Scratch |
| 433 | }, |
| 434 | //DpF |
| 435 | { |
| 436 | { |
| 437 | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST, |
| 438 | offsetof (TN_COMPLEX_CONFIG, DpF) - offsetof (TN_COMPLEX_CONFIG, DdiWrapper), |
| 439 | offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, DpF), |
| 440 | 0 |
| 441 | }, |
| 442 | {PcieDdiEngine}, |
| 443 | 0, //Initialization Status |
| 444 | 0xFF //Scratch |
| 445 | }, |
| 446 | //DpA |
| 447 | { |
| 448 | { |
| 449 | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY, |
| 450 | offsetof (TN_COMPLEX_CONFIG, DpA) - offsetof (TN_COMPLEX_CONFIG, Ddi2Wrapper), |
| 451 | 0, |
| 452 | 0 |
| 453 | }, |
| 454 | {PcieDdiEngine}, |
| 455 | 0, //Initialization Status |
| 456 | 0xFF //Scratch |
| 457 | }, |
| 458 | //F12 specific Silicon |
| 459 | { |
| 460 | OscFuses, |
| 461 | {0, 0, 0, 0, 0, 0} |
| 462 | } |
| 463 | }; |