zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Family specific function translation |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "GnbPcieFamServices.h" |
| 56 | #include "GnbCommonLib.h" |
| 57 | #include "GnbPcieConfig.h" |
| 58 | #include "Filecode.h" |
| 59 | #define FILECODE PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE |
| 60 | /*---------------------------------------------------------------------------------------- |
| 61 | * D E F I N I T I O N S A N D M A C R O S |
| 62 | *---------------------------------------------------------------------------------------- |
| 63 | */ |
| 64 | |
| 65 | /*---------------------------------------------------------------------------------------- |
| 66 | * T Y P E D E F S A N D S T R U C T U R E S |
| 67 | *---------------------------------------------------------------------------------------- |
| 68 | */ |
| 69 | |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | /*----------------------------------------------------------------------------------------*/ |
| 76 | /** |
| 77 | * Configure engine list to support lane allocation according to configuration ID. |
| 78 | * |
| 79 | * |
| 80 | * |
| 81 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 82 | * @param[in] EngineType Engine Type |
| 83 | * @param[in] ConfigurationId Configuration ID |
| 84 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 85 | * @retval AGESA_UNSUPPORTED No more configuration available for given engine type |
| 86 | * @retval AGESA_ERROR Requested configuration not supported |
| 87 | */ |
| 88 | AGESA_STATUS |
| 89 | PcieFmConfigureEnginesLaneAllocation ( |
| 90 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 91 | IN PCIE_ENGINE_TYPE EngineType, |
| 92 | IN UINT8 ConfigurationId |
| 93 | ) |
| 94 | { |
| 95 | AGESA_STATUS Status; |
| 96 | PCIe_COMPLEX_CONFIG *Complex; |
| 97 | PCIe_PLATFORM_CONFIG *Pcie; |
| 98 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
| 99 | |
| 100 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); |
| 101 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 102 | Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 103 | ASSERT (Status == AGESA_SUCCESS); |
| 104 | if (Status == AGESA_SUCCESS) { |
| 105 | return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); |
| 106 | } |
| 107 | return AGESA_ERROR; |
| 108 | } |
| 109 | |
| 110 | /*----------------------------------------------------------------------------------------*/ |
| 111 | /** |
| 112 | * Get core configuration value |
| 113 | * |
| 114 | * |
| 115 | * |
| 116 | * @param[in] Wrapper Pointer to internal configuration data area |
| 117 | * @param[in] CoreId Core ID |
| 118 | * @param[in] ConfigurationSignature Configuration signature |
| 119 | * @param[out] ConfigurationValue Configuration value (for core configuration) |
| 120 | * @retval AGESA_SUCCESS Configuration successfully applied |
| 121 | * @retval AGESA_ERROR Core configuration value can not be determined |
| 122 | */ |
| 123 | AGESA_STATUS |
| 124 | PcieFmGetCoreConfigurationValue ( |
| 125 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 126 | IN UINT8 CoreId, |
| 127 | IN UINT64 ConfigurationSignature, |
| 128 | IN UINT8 *ConfigurationValue |
| 129 | ) |
| 130 | { |
| 131 | AGESA_STATUS Status; |
| 132 | PCIe_COMPLEX_CONFIG *Complex; |
| 133 | PCIe_PLATFORM_CONFIG *Pcie; |
| 134 | PCIe_FAM_INIT_SERVICES *PcieInitService; |
| 135 | |
| 136 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); |
| 137 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 138 | Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 139 | ASSERT (Status == AGESA_SUCCESS); |
| 140 | if (Status == AGESA_SUCCESS) { |
| 141 | return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); |
| 142 | } |
| 143 | return AGESA_ERROR; |
| 144 | } |
| 145 | |
| 146 | |
| 147 | /*----------------------------------------------------------------------------------------*/ |
| 148 | /** |
| 149 | * Check if engine can be remapped to Device/function number requested by user |
| 150 | * defined engine descriptor |
| 151 | * |
| 152 | * Function only called if requested device/function does not much native device/function |
| 153 | * |
| 154 | * @param[in] PortDescriptor Pointer to user defined engine descriptor |
| 155 | * @param[in] Engine Pointer engine configuration |
| 156 | * @retval TRUE Descriptor can be mapped to engine |
| 157 | * @retval FALSE Descriptor can NOT be mapped to engine |
| 158 | */ |
| 159 | |
| 160 | BOOLEAN |
| 161 | PcieFmCheckPortPciDeviceMapping ( |
| 162 | IN PCIe_PORT_DESCRIPTOR *PortDescriptor, |
| 163 | IN PCIe_ENGINE_CONFIG *Engine |
| 164 | ) |
| 165 | { |
| 166 | AGESA_STATUS Status; |
| 167 | PCIe_COMPLEX_CONFIG *Complex; |
| 168 | PCIe_PLATFORM_CONFIG *Pcie; |
| 169 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
| 170 | |
| 171 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
| 172 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 173 | Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 174 | ASSERT (Status == AGESA_SUCCESS); |
| 175 | if (Status == AGESA_SUCCESS) { |
| 176 | return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); |
| 177 | } |
| 178 | return FALSE; |
| 179 | } |
| 180 | |
| 181 | |
| 182 | /*----------------------------------------------------------------------------------------*/ |
| 183 | /** |
| 184 | * Get core configuration string |
| 185 | * |
| 186 | * Debug function for logging configuration |
| 187 | * |
| 188 | * @param[in] Wrapper Pointer to internal configuration data area |
| 189 | * @param[in] ConfigurationValue Configuration value |
| 190 | * @retval Configuration string |
| 191 | */ |
| 192 | |
| 193 | CONST CHAR8* |
| 194 | PcieFmDebugGetCoreConfigurationString ( |
| 195 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 196 | IN UINT8 ConfigurationValue |
| 197 | ) |
| 198 | { |
| 199 | AGESA_STATUS Status; |
| 200 | PCIe_COMPLEX_CONFIG *Complex; |
| 201 | PCIe_PLATFORM_CONFIG *Pcie; |
| 202 | PCIe_FAM_DEBUG_SERVICES *PcieDebugService; |
| 203 | |
| 204 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); |
| 205 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 206 | Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 207 | ASSERT (Status == AGESA_SUCCESS); |
| 208 | if (Status == AGESA_SUCCESS) { |
| 209 | return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); |
| 210 | } |
| 211 | return " !!! Something Wrong !!!"; |
| 212 | } |
| 213 | |
| 214 | /*----------------------------------------------------------------------------------------*/ |
| 215 | /** |
| 216 | * Get wrapper name |
| 217 | * |
| 218 | * Debug function for logging wrapper name |
| 219 | * |
| 220 | * @param[in] Wrapper Pointer to internal configuration data area |
| 221 | * @retval Wrapper Name string |
| 222 | */ |
| 223 | |
| 224 | CONST CHAR8* |
| 225 | PcieFmDebugGetWrapperNameString ( |
| 226 | IN PCIe_WRAPPER_CONFIG *Wrapper |
| 227 | ) |
| 228 | { |
| 229 | AGESA_STATUS Status; |
| 230 | PCIe_COMPLEX_CONFIG *Complex; |
| 231 | PCIe_PLATFORM_CONFIG *Pcie; |
| 232 | PCIe_FAM_DEBUG_SERVICES *PcieDebugService; |
| 233 | |
| 234 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); |
| 235 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 236 | Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 237 | ASSERT (Status == AGESA_SUCCESS); |
| 238 | if (Status == AGESA_SUCCESS) { |
| 239 | return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); |
| 240 | } |
| 241 | return " !!! Something Wrong !!!"; |
| 242 | } |
| 243 | |
| 244 | /*----------------------------------------------------------------------------------------*/ |
| 245 | /** |
| 246 | * Get register address name |
| 247 | * |
| 248 | * Debug function for logging register trace |
| 249 | * |
| 250 | * @param[in] Silicon Silicon config descriptor |
| 251 | * @param[in] AddressFrame Address Frame |
| 252 | * @retval Register address name |
| 253 | */ |
| 254 | CONST CHAR8* |
| 255 | PcieFmDebugGetHostRegAddressSpaceString ( |
| 256 | IN PCIe_SILICON_CONFIG *Silicon, |
| 257 | IN UINT16 AddressFrame |
| 258 | ) |
| 259 | { |
| 260 | AGESA_STATUS Status; |
| 261 | PCIe_COMPLEX_CONFIG *Complex; |
| 262 | PCIe_PLATFORM_CONFIG *Pcie; |
| 263 | PCIe_FAM_DEBUG_SERVICES *PcieDebugService; |
| 264 | |
| 265 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); |
| 266 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 267 | Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 268 | ASSERT (Status == AGESA_SUCCESS); |
| 269 | if (Status == AGESA_SUCCESS) { |
| 270 | return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); |
| 271 | } |
| 272 | return " !!! Something Wrong !!!"; |
| 273 | } |
| 274 | |
| 275 | /*----------------------------------------------------------------------------------------*/ |
| 276 | /** |
| 277 | * Check if the lane can be muxed by link width requested by user |
| 278 | * defined engine descriptor |
| 279 | * |
| 280 | * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). |
| 281 | * Check Engine StartCoreLane could be aligned by user requested link width x2. |
| 282 | * |
| 283 | * @param[in] PortDescriptor Pointer to user defined engine descriptor |
| 284 | * @param[in] Engine Pointer engine configuration |
| 285 | * @retval TRUE Lane can be muxed |
| 286 | * @retval FALSE Lane can NOT be muxed |
| 287 | */ |
| 288 | |
| 289 | BOOLEAN |
| 290 | PcieFmCheckPortPcieLaneCanBeMuxed ( |
| 291 | IN PCIe_PORT_DESCRIPTOR *PortDescriptor, |
| 292 | IN PCIe_ENGINE_CONFIG *Engine |
| 293 | ) |
| 294 | { |
| 295 | AGESA_STATUS Status; |
| 296 | PCIe_COMPLEX_CONFIG *Complex; |
| 297 | PCIe_PLATFORM_CONFIG *Pcie; |
| 298 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
| 299 | |
| 300 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
| 301 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 302 | Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 303 | ASSERT (Status == AGESA_SUCCESS); |
| 304 | if (Status == AGESA_SUCCESS) { |
| 305 | return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); |
| 306 | } |
| 307 | return FALSE; |
| 308 | } |
| 309 | |
| 310 | /*----------------------------------------------------------------------------------------*/ |
| 311 | /** |
| 312 | * Map engine to specific PCI device address |
| 313 | * |
| 314 | * |
| 315 | * |
| 316 | * @param[in] Engine Pointer to engine configuration |
| 317 | * @retval AGESA_ERROR Fail to map PCI device address |
| 318 | * @retval AGESA_SUCCESS Successfully allocate PCI address |
| 319 | */ |
| 320 | |
| 321 | AGESA_STATUS |
| 322 | PcieFmMapPortPciAddress ( |
| 323 | IN PCIe_ENGINE_CONFIG *Engine |
| 324 | ) |
| 325 | { |
| 326 | AGESA_STATUS Status; |
| 327 | PCIe_COMPLEX_CONFIG *Complex; |
| 328 | PCIe_PLATFORM_CONFIG *Pcie; |
| 329 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
| 330 | |
| 331 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
| 332 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 333 | Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 334 | ASSERT (Status == AGESA_SUCCESS); |
| 335 | if (Status == AGESA_SUCCESS) { |
| 336 | return PcieConfigService->PcieFmMapPortPciAddress (Engine); |
| 337 | } |
| 338 | return AGESA_ERROR; |
| 339 | } |
| 340 | |
| 341 | /*----------------------------------------------------------------------------------------*/ |
| 342 | /** |
| 343 | * Get total number of silicons/wrappers/engines for this complex |
| 344 | * |
| 345 | * |
| 346 | * |
| 347 | * @param[in] SocketId Socket ID. |
| 348 | * @param[out] Length Length of configuration info block |
| 349 | * @param[out] StdHeader Standard Configuration Header |
| 350 | * @retval AGESA_SUCCESS Configuration data length is correct |
| 351 | */ |
| 352 | AGESA_STATUS |
| 353 | PcieFmGetComplexDataLength ( |
| 354 | IN UINT8 SocketId, |
| 355 | OUT UINTN *Length, |
| 356 | IN AMD_CONFIG_PARAMS *StdHeader |
| 357 | ) |
| 358 | { |
| 359 | AGESA_STATUS Status; |
| 360 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 361 | Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 362 | ASSERT (Status == AGESA_SUCCESS); |
| 363 | if (Status == AGESA_SUCCESS) { |
| 364 | return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); |
| 365 | } |
| 366 | return Status; |
| 367 | } |
| 368 | |
| 369 | |
| 370 | |
| 371 | |
| 372 | /*----------------------------------------------------------------------------------------*/ |
| 373 | /** |
| 374 | * Build configuration |
| 375 | * |
| 376 | * |
| 377 | * @param[in] SocketId Socket ID. |
| 378 | * @param[out] Buffer Pointer to buffer to build internal complex data structure |
| 379 | * @param[out] StdHeader Standard configuration header. |
| 380 | * @retval AGESA_SUCCESS Configuration data build successfully |
| 381 | */ |
| 382 | AGESA_STATUS |
| 383 | PcieFmBuildComplexConfiguration ( |
| 384 | IN UINT8 SocketId, |
| 385 | OUT VOID *Buffer, |
| 386 | IN AMD_CONFIG_PARAMS *StdHeader |
| 387 | ) |
| 388 | { |
| 389 | AGESA_STATUS Status; |
| 390 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 391 | Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 392 | ASSERT (Status == AGESA_SUCCESS); |
| 393 | if (Status == AGESA_SUCCESS) { |
| 394 | return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); |
| 395 | } |
| 396 | return Status; |
| 397 | } |
| 398 | |
| 399 | /*----------------------------------------------------------------------------------------*/ |
| 400 | /** |
| 401 | * Get max link speed capability supported by this port |
| 402 | * |
| 403 | * |
| 404 | * |
| 405 | * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX |
| 406 | * @param[in] Engine Pointer to engine config descriptor |
| 407 | * @retval PcieGen1/PcieGen2 Max supported link gen capability |
| 408 | */ |
| 409 | PCIE_LINK_SPEED_CAP |
| 410 | PcieFmGetLinkSpeedCap ( |
| 411 | IN UINT32 Flags, |
| 412 | IN PCIe_ENGINE_CONFIG *Engine |
| 413 | ) |
| 414 | { |
| 415 | AGESA_STATUS Status; |
| 416 | PCIe_COMPLEX_CONFIG *Complex; |
| 417 | PCIe_PLATFORM_CONFIG *Pcie; |
| 418 | PCIe_FAM_INIT_SERVICES *PcieInitService; |
| 419 | |
| 420 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
| 421 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 422 | Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 423 | ASSERT (Status == AGESA_SUCCESS); |
| 424 | if (Status == AGESA_SUCCESS) { |
| 425 | return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); |
| 426 | } |
| 427 | return PcieGen1; |
| 428 | } |
| 429 | |
| 430 | /*----------------------------------------------------------------------------------------*/ |
| 431 | /** |
| 432 | * Get native PHY lane bitmap |
| 433 | * |
| 434 | * |
| 435 | * @param[in] PhyLaneBitmap Package PHY lane bitmap |
| 436 | * @param[in] Engine Standard configuration header. |
| 437 | * @retval Native PHY lane bitmap |
| 438 | */ |
| 439 | UINT32 |
| 440 | PcieFmGetNativePhyLaneBitmap ( |
| 441 | IN UINT32 PhyLaneBitmap, |
| 442 | IN PCIe_ENGINE_CONFIG *Engine |
| 443 | ) |
| 444 | { |
| 445 | AGESA_STATUS Status; |
| 446 | PCIe_COMPLEX_CONFIG *Complex; |
| 447 | PCIe_PLATFORM_CONFIG *Pcie; |
| 448 | PCIe_FAM_INIT_SERVICES *PcieInitService; |
| 449 | |
| 450 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
| 451 | Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 452 | Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 453 | ASSERT (Status == AGESA_SUCCESS); |
| 454 | if (Status == AGESA_SUCCESS) { |
| 455 | return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); |
| 456 | } |
| 457 | return 0x0; |
| 458 | } |
| 459 | |
| 460 | /*----------------------------------------------------------------------------------------*/ |
| 461 | /** |
| 462 | * Set current link speed |
| 463 | * |
| 464 | * |
| 465 | * @param[in] LinkSpeedCapability Link Speed Capability |
| 466 | * @param[in] Engine Pointer to engine configuration descriptor |
| 467 | * @param[in] Pcie Pointer to global PCIe configuration |
| 468 | * |
| 469 | */ |
| 470 | VOID |
| 471 | PcieFmSetLinkSpeedCap ( |
| 472 | IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, |
| 473 | IN PCIe_ENGINE_CONFIG *Engine, |
| 474 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 475 | ) |
| 476 | { |
| 477 | AGESA_STATUS Status; |
| 478 | PCIe_COMPLEX_CONFIG *Complex; |
| 479 | PCIe_FAM_INIT_SERVICES *PcieInitService; |
| 480 | |
| 481 | Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 482 | Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 483 | ASSERT (Status == AGESA_SUCCESS); |
| 484 | if (Status == AGESA_SUCCESS) { |
| 485 | PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | /*----------------------------------------------------------------------------------------*/ |
| 490 | /** |
| 491 | * Get SB port info |
| 492 | * |
| 493 | * |
| 494 | * @param[out] SocketId Socket ID |
| 495 | * @param[out] SbPort Pointer to SB configuration descriptor |
| 496 | * @param[in] StdHeader Standard configuration header. |
| 497 | * @retval AGESA_SUCCESS SB configuration determined successfully |
| 498 | */ |
| 499 | AGESA_STATUS |
| 500 | PcieFmGetSbConfigInfo ( |
| 501 | IN UINT8 SocketId, |
| 502 | OUT PCIe_PORT_DESCRIPTOR *SbPort, |
| 503 | IN AMD_CONFIG_PARAMS *StdHeader |
| 504 | ) |
| 505 | { |
| 506 | AGESA_STATUS Status; |
| 507 | PCIe_FAM_CONFIG_SERVICES *PcieConfigService; |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 508 | Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 509 | ASSERT (Status == AGESA_SUCCESS); |
| 510 | if (Status == AGESA_SUCCESS) { |
| 511 | return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); |
| 512 | } |
| 513 | return Status; |
| 514 | } |