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review.coreboot.org / coreboot / 8d3640d22610eeb9a21c803d75c698e681a1dc62 / . / src / vendorcode / amd / agesa / f15tn / Proc / GNB / Common / GnbPcie.h
blob: 357484ddbf2af9d30305ae81f7a12f031efeece9 [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * PCIe component definitions.
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: GNB
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42* ***************************************************************************
43
44*
45*/
46
47#ifndef _GNBPCIE_H_
48#define _GNBPCIE_H_
49
50#pragma pack (push, 1)
51
52#define MAX_NUMBER_OF_COMPLEXES 4
53
54#define DESCRIPTOR_TERMINATE_GNB 0x40000000ull
55#define DESCRIPTOR_TERMINATE_TOPOLOGY 0x20000000ull
56#define DESCRIPTOR_ALLOCATED 0x10000000ull
57#define DESCRIPTOR_VIRTUAL 0x08000000ull
58#define DESCRIPTOR_PLATFORM 0x04000000ull
59#define DESCRIPTOR_COMPLEX 0x02000000ull
60#define DESCRIPTOR_SILICON 0x01000000ull
61#define DESCRIPTOR_PCIE_WRAPPER 0x00800000ull
62#define DESCRIPTOR_DDI_WRAPPER 0x00400000ull
63#define DESCRIPTOR_PCIE_ENGINE 0x00200000ull
64#define DESCRIPTOR_DDI_ENGINE 0x00100000ull
65
66#define DESCRIPTOR_ALL_WRAPPERS (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
67#define DESCRIPTOR_ALL_ENGINES (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
68
69#define DESCRIPTOR_ALL_TYPES (DESCRIPTOR_ALL_WRAPPERS | DESCRIPTOR_ALL_ENGINES | DESCRIPTOR_SILICON | DESCRIPTOR_PLATFORM)
70
71#define UNUSED_LANE_ID 128
72//#define PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
73//#define PCIE_LINK_L0_POOLING (60 * 1000)
74//#define PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
75//#define PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
76
77// Get lowest PHY lane on engine
78#define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0)
79// Get highest PHY lane on engine
80#define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0)
81// Get number of lanes on wrapper
82#define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
83// Check if virtual descriptor
84#define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_VIRTUAL) != 0) : FALSE)
85// Check if it is allocated descriptor
86#define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0) : FALSE)
87// Check if it is last descriptor in list
88#define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) : TRUE)
89// Check if descriptor a PCIe engine
90#define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_ENGINE) != 0) : FALSE)
91// Check if descriptor a DDI engine
92#define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_ENGINE) != 0) : FALSE)
93// Check if descriptor a DDI wrapper
94#define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_DDI_WRAPPER) != 0) : FALSE)
95// Check if descriptor a PCIe wrapper
96#define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Header.DescriptorFlags & DESCRIPTOR_PCIE_WRAPPER) != 0) : FALSE)
97// Check if descriptor a PCIe wrapper
98#define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Header.DescriptorFlags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : (Descriptor+1)) : NULL)
99
100#define LANE_TYPE_PCIE_CORE_CONFIG 0x00000001ul
101#define LANE_TYPE_PCIE_CORE_ALLOC 0x00000002ul
102#define LANE_TYPE_PCIE_CORE_ACTIVE 0x00000004ul
103#define LANE_TYPE_PCIE_SB_CORE_CONFIG 0x00000008ul
104#define LANE_TYPE_PCIE_CORE_HOTPLUG 0x00000010ul
105#define LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE 0x00000020ul
106#define LANE_TYPE_PCIE_PHY 0x00000100ul
107#define LANE_TYPE_PCIE_PHY_NATIVE 0x00000200ul
108#define LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE 0x00000400ul
109#define LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG 0x00000800ul
110#define LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE 0x00001000ul
111#define LANE_TYPE_DDI_PHY 0x00010000ul
112#define LANE_TYPE_DDI_PHY_NATIVE 0x00020000ul
113#define LANE_TYPE_DDI_PHY_NATIVE_ACTIVE 0x00040000ul
114#define LANE_TYPE_PHY_NATIVE_ALL 0x00100000ul
115#define LANE_TYPE_PCIE_PHY_NATIVE_MASTER_PLL 0x00200000ul
116#define LANE_TYPE_CORE_ALL LANE_TYPE_PHY_NATIVE_ALL
117#define LANE_TYPE_ALL LANE_TYPE_PHY_NATIVE_ALL
118
119#define LANE_TYPE_PCIE_LANES (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_SB_CORE_CONFIG | \
120 LANE_TYPE_PCIE_CORE_HOTPLUG | LANE_TYPE_PCIE_CORE_ALLOC | \
121 LANE_TYPE_PCIE_PHY | LANE_TYPE_PCIE_PHY_NATIVE | \
122 LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG | \
123 LANE_TYPE_PCIE_CORE_CONFIG | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE | \
124 LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)
125
126#define LANE_TYPE_DDI_LANES (LANE_TYPE_DDI_PHY | LANE_TYPE_DDI_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE_ACTIVE)
127
128
129#define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY 0x00000001ull
130#define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY 0x00000002ull
131#define INIT_STATUS_PCIE_PORT_TRAINING_FAIL 0x00000004ull
132#define INIT_STATUS_PCIE_TRAINING_SUCCESS 0x00000008ull
133#define INIT_STATUS_PCIE_EP_NOT_PRESENT 0x00000010ull
134#define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE 0x00000020ull
135#define INIT_STATUS_DDI_ACTIVE 0x00000040ull
136#define INIT_STATUS_ALLOCATED 0x00000080ull
137
138#define PCIE_PORT_GEN_CAP_BOOT 0x00000001ul
139#define PCIE_PORT_GEN_CAP_MAX 0x00000002ul
140#define PCIE_GLOBAL_GEN_CAP_ALL_PORTS 0x00000010ul
141#define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS 0x00000011ul
142#define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS 0x00000012ul
143
144#define PCIE_POWERGATING_SKIP_CORE 0x00000001ul
145#define PCIE_POWERGATING_SKIP_PHY 0x00000002ul
146
147/// PCIe Link Training State
148typedef enum {
149 PcieTrainingStandard, ///< Standard training algorithm. Training contained to AmdEarlyInit.
150 ///< PCIe device accessible after AmdEarlyInit complete
151 PcieTrainingDistributed, ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
152 ///< PCIe device accessible after AmdPostInit complete.
153 ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
154} PCIE_TRAINING_ALGORITHM;
155
156/// PCIe Link Training State
157typedef enum {
158 LinkStateResetAssert, ///< Assert port GPIO reset
159 LinkStateResetDuration, ///< Timeout for reset duration
160 LinkStateResetExit, ///< Deassert port GPIO reset
161 LinkTrainingResetTimeout, ///< Port GPIO reset timeout
162 LinkStateReleaseTraining, ///< Release link training
163 LinkStateDetectPresence, ///< Detect device presence
164 LinkStateDetecting, ///< Detect link training.
165 LinkStateBrokenLane, ///< Check and handle broken lane
166 LinkStateGen2Fail, ///< Check and handle device that fail training if GEN2 capability advertised
167 LinkStateL0, ///< Device trained to L0
168 LinkStateVcoNegotiation, ///< Check VCO negotiation complete
169 LinkStateRetrain, ///< Force retrain link.
170 LinkStateTrainingFail, ///< Link training fail
171 LinkStateTrainingSuccess, ///< Link training success
172 LinkStateGfxWorkaround, ///< GFX workaround
173 LinkStateCompliance, ///< Link in compliance mode
174 LinkStateDeviceNotPresent, ///< Link is not connected
175 LinkStateTrainingCompleted ///< Link training completed
176} PCIE_LINK_TRAINING_STATE;
177
178/// PCIe Port Visibility
179typedef enum {
180 UnhidePorts, ///< Command to unhide port
181 HidePorts, ///< Command to hide unused ports
182} PCIE_PORT_VISIBILITY;
183
184
185/// Table Register Entry
186typedef struct {
187 UINT16 Reg; ///< Address
188 UINT32 Mask; ///< Mask
189 UINT32 Data; ///< Data
190} PCIE_PORT_REGISTER_ENTRY;
191
192/// Table Register Entry
193typedef struct {
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame^]194 CONST PCIE_PORT_REGISTER_ENTRY *Table; ///< Table
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]195 UINT32 Length; ///< Length
196} PCIE_PORT_REGISTER_TABLE_HEADER;
197
198/// Table Register Entry
199typedef struct {
200 UINT32 Reg; ///< Address
201 UINT32 Mask; ///< Mask
202 UINT32 Data; ///< Data
203} PCIE_HOST_REGISTER_ENTRY;
204
205/// Table Register Entry
206typedef struct {
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame^]207 CONST PCIE_HOST_REGISTER_ENTRY *Table; ///< Table
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]208 UINT32 Length; ///< Length
209} PCIE_HOST_REGISTER_TABLE_HEADER;
210
211///Link ASPM info
212typedef struct {
213 PCI_ADDR DownstreamPort; ///< PCI address of downstream port
214 PCIE_ASPM_TYPE DownstreamAspm; ///< Downstream Device Aspm
215 PCI_ADDR UpstreamPort; ///< PCI address of upstream port
216 PCIE_ASPM_TYPE UpstreamAspm; ///< Upstream Device Capability
217 PCIE_ASPM_TYPE RequestedAspm; ///< Requested ASPM
218} PCIe_LINK_ASPM;
219
220///PCIe ASPM Latency Information
221typedef struct {
222 UINT8 MaxL0sExitLatency; ///< Max L0s exit latency in us
223 UINT8 MaxL1ExitLatency; ///< Max L1 exit latency in us
224} PCIe_ASPM_LATENCY_INFO;
225
226/// PCI address association
227typedef struct {
228 UINT8 NewDeviceAddress; ///< New PCI address (Device,Fucntion)
229 UINT8 NativeDeviceAddress; ///< Native PCI address (Device,Fucntion)
230} PCI_ADDR_LIST;
231
232/// The return status for GFX Card Workaround.
233typedef enum {
234 GFX_WORKAROUND_DEVICE_NOT_READY, ///< GFX Workaround device is not ready.
235 GFX_WORKAROUND_RESET_DEVICE, ///< GFX Workaround device need reset.
236 GFX_WORKAROUND_SUCCESS ///< The service completed normally.
237} GFX_WORKAROUND_STATUS;
238
239/// GFX workaround control
240typedef enum {
241 GfxWorkaroundDisable, ///< GFX Workaround disabled
242 GfxWorkaroundEnable ///< GFX Workaround enabled
243} GFX_WORKAROUND_CONTROL;
244
245/// PIF lane power state
246typedef enum {
247 PifPowerStateL0, ///<
248 PifPowerStateLS1, ///<
249 PifPowerStateLS2, ///<
250 PifPowerStateOff = 0x7, ///<
251} PCIE_PIF_POWER_STATE;
252
253/// PIF lane power control
254typedef enum {
255 PowerDownPifs, ///<
256 PowerUpPifs ///<
257} PCIE_PIF_POWER_CONTROL;
258
259///PLL rumup time
260typedef enum {
261 NormalRampup, ///<
262 LongRampup, ///<
263} PCIE_PLL_RAMPUP_TIME;
264
265typedef UINT16 PCIe_ENGINE_INIT_STATUS;
266
267/// PCIe port configuration info
268typedef struct {
269 PCIe_PORT_DATA PortData; ///< Port data
270 UINT8 StartCoreLane; ///< Start Core Lane
271 UINT8 EndCoreLane; ///< End Core lane
272 UINT8 NativeDevNumber :5; ///< Native PCI device number of the port
273 UINT8 NativeFunNumber :3; ///< Native PCI function number of the port
274 UINT8 CoreId :4; ///< PCIe core ID
275 UINT8 PortId :4; ///< Port ID on wrapper
276 PCI_ADDR Address; ///< PCI address of the port
277 UINT8 State; ///< Training state
278 UINT8 PcieBridgeId:4; ///< IOC PCIe bridge ID
279 UINT16 UnitId:12; ///< Port start unit ID
280 UINT16 NumberOfUnitId:4; ///< Def number of unitIDs assigned to port
281 UINT8 GfxWrkRetryCount:4; ///< Number of retry for GFX workaround
282 UINT32 TimeStamp; ///< Time stamp used to during training process
283 UINT8 LogicalBridgeId; ///< Logical Bridge ID
284} PCIe_PORT_CONFIG;
285
286///Descriptor header
287typedef struct {
288 UINT32 DescriptorFlags; ///< Descriptor flags
289 UINT16 Parent; ///< Offset of parent descriptor
290 UINT16 Peer; ///< Offset of the peer descriptor
291 UINT16 Child; ///< Offset of the list of child descriptors
292} PCIe_DESCRIPTOR_HEADER;
293
294/// DDI (Digital Display Interface) configuration info
295typedef struct {
296 PCIe_DDI_DATA DdiData; ///< DDI Data
297 UINT8 DisplayPriorityIndex; ///< Display priority index
298 UINT8 ConnectorId; ///< Connector id determined by enumeration
299 UINT8 DisplayDeviceId; ///< Display device id determined by enumeration
300} PCIe_DDI_CONFIG;
301
302
303/// Engine configuration data
304typedef struct {
305 PCIe_DESCRIPTOR_HEADER Header; ///< Descripto header
306 PCIe_ENGINE_DATA EngineData; ///< Engine Data
307 PCIe_ENGINE_INIT_STATUS InitStatus; ///< Initialization Status
308 UINT8 Scratch; ///< Scratch pad
309 union {
310 PCIe_PORT_CONFIG Port; ///< PCIe port configuration data
311 PCIe_DDI_CONFIG Ddi; ///< DDI configuration data
312 } Type;
313} PCIe_ENGINE_CONFIG;
314
315/// Wrapper configuration data
316typedef struct {
317 PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header
318 UINT8 WrapId; ///< Wrapper ID
319 UINT8 NumberOfPIFs; ///< Number of PIFs on wrapper
320 UINT8 StartPhyLane; ///< Start PHY Lane
321 UINT8 EndPhyLane; ///< End PHY Lane
322 UINT8 StartPcieCoreId:4; ///< Start PCIe Core ID
323 UINT8 EndPcieCoreId:4; ///< End PCIe Core ID
324 UINT8 NumberOfLanes; ///< Number of lanes
325 struct {
326 UINT8 PowerOffUnusedLanes:1; ///< Power Off unused lanes
327 UINT8 PowerOffUnusedPlls:1; ///< Power Off unused Plls
328 UINT8 ClkGating:1; ///< TXCLK gating
329 UINT8 LclkGating:1; ///< LCLK gating
330 UINT8 TxclkGatingPllPowerDown:1; ///< TXCLK clock gating PLL power down
331 UINT8 PllOffInL1:1; ///< PLL off in L1
332 UINT8 AccessEncoding:1; ///< Reg access encoding
333 } Features;
334 UINT8 MasterPll; ///< Bitmap of master PLL
335} PCIe_WRAPPER_CONFIG;
336
337
338/// Silicon configuration data
339typedef struct {
340 PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header
341 UINT8 SiliconId; ///< Gnb silicon(module) ID
342 UINT8 NodeId; ///< Node to which GNB connected
343 UINT8 LinkId; ///< Link to which GNB connected if LinkId > 3 GNB connected to sublink = LinkId - 4
344 PCI_ADDR Address; ///< PCI address of GNB host bridge
345} PCIe_SILICON_CONFIG;
346
347typedef PCIe_SILICON_CONFIG GNB_HANDLE;
348
349/// Complex configuration data
350typedef struct {
351 PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header
352 UINT8 SocketId; ///< Processor socket ID
353} PCIe_COMPLEX_CONFIG;
354
355/// PCIe platform configuration info
356typedef struct {
357 PCIe_DESCRIPTOR_HEADER Header; ///< Descrptor Header
Stefan Reinauerd91ddc82015-07-30 11:17:40 -0700[diff] [blame]358 UINTN StdHeader; ///< Standard configuration header TODO:Used to be PVOID
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]359 UINT32 LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
360 UINT32 LinkL0Pooling; ///< Pooling for link to get to L0 in us
361 UINT32 LinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
362 UINT32 LinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us ///
363 UINT8 GfxCardWorkaround; ///< GFX Card Workaround
364 UINT8 PsppPolicy; ///< PSPP policy
365 UINT8 TrainingExitState; ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
366 UINT8 TrainingAlgorithm; ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
367 PCIe_COMPLEX_CONFIG ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///< Complex
368} PCIe_PLATFORM_CONFIG;
369
370/// PCIe Engine Description
371typedef struct {
372 UINT32 Flags; /**< Descriptor flags
373 * @li @b Bit31 - last descriptor on wrapper
374 * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
375 */
376 PCIe_ENGINE_DATA EngineData; ///< Engine Data
377} PCIe_ENGINE_DESCRIPTOR;
378
379/// PCIe Lane allocation descriptor
380typedef struct {
381 UINT32 Flags; ///< Flags
382 UINT8 WrapId; ///< Wrapper ID
383 UINT8 EngineType; ///< Engine Type
384 UINT8 NumberOfEngines; ///< Number of engines to configure
385 UINT8 NumberOfConfigurations; ///< Number of possible configurations
386 UINT8 *ConfigTable; ///< Pointer to config table
387} PCIe_LANE_ALLOC_DESCRIPTOR;
388
389#pragma pack (pop)
390
391#endif