zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * FCH IO access common routine |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /*;******************************************************************************** |
| 16 | ; |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | ;*********************************************************************************/ |
| 42 | |
| 43 | #include "FchPlatform.h" |
| 44 | #define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE |
| 45 | |
| 46 | /*----------------------------------------------------------------------------------------*/ |
| 47 | /** |
| 48 | * ProgramPciByteTable - Program PCI register by table (8 bits data) |
| 49 | * |
| 50 | * |
| 51 | * |
| 52 | * @param[in] pPciByteTable - Table data pointer |
| 53 | * @param[in] dwTableSize - Table length |
| 54 | * @param[in] StdHeader |
| 55 | * |
| 56 | */ |
| 57 | VOID |
| 58 | ProgramPciByteTable ( |
| 59 | IN REG8_MASK *pPciByteTable, |
| 60 | IN UINT16 dwTableSize, |
| 61 | IN AMD_CONFIG_PARAMS *StdHeader |
| 62 | ) |
| 63 | { |
| 64 | UINT8 i; |
| 65 | UINT8 dbBusNo; |
| 66 | UINT8 dbDevFnNo; |
| 67 | UINT8 Or8; |
| 68 | UINT8 Mask8; |
| 69 | PCI_ADDR PciAddress; |
| 70 | |
| 71 | dbBusNo = pPciByteTable->RegIndex; |
| 72 | dbDevFnNo = pPciByteTable->AndMask; |
| 73 | pPciByteTable++; |
| 74 | |
| 75 | for ( i = 1; i < dwTableSize; i++ ) { |
| 76 | if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) { |
| 77 | pPciByteTable++; |
| 78 | dbBusNo = pPciByteTable->RegIndex; |
| 79 | dbDevFnNo = pPciByteTable->AndMask; |
| 80 | pPciByteTable++; |
| 81 | i++; |
| 82 | } else { |
| 83 | PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex; |
| 84 | Or8 = pPciByteTable->OrMask; |
| 85 | Mask8 = ~pPciByteTable->AndMask; |
| 86 | LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader); |
| 87 | pPciByteTable++; |
| 88 | } |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | /*----------------------------------------------------------------------------------------*/ |
| 93 | /** |
| 94 | * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data) |
| 95 | * |
| 96 | * |
| 97 | * |
| 98 | * @param[in] pAcpiTbl - Table data pointer |
| 99 | * @param[in] StdHeader |
| 100 | * |
| 101 | */ |
| 102 | VOID |
| 103 | ProgramFchAcpiMmioTbl ( |
| 104 | IN ACPI_REG_WRITE *pAcpiTbl, |
| 105 | IN AMD_CONFIG_PARAMS *StdHeader |
| 106 | ) |
| 107 | { |
| 108 | UINT8 i; |
| 109 | UINT8 Or8; |
| 110 | UINT8 Mask8; |
| 111 | UINT32 ddtempVar; |
| 112 | |
| 113 | if (pAcpiTbl != NULL) { |
| 114 | if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) { |
| 115 | // Signature Checking |
| 116 | pAcpiTbl++; |
| 117 | for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) { |
| 118 | ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; |
| 119 | Or8 = pAcpiTbl->DataOrMask; |
| 120 | Mask8 = ~pAcpiTbl->DataAndMask; |
| 121 | LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader); |
| 122 | pAcpiTbl++; |
| 123 | } |
| 124 | } |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | /*----------------------------------------------------------------------------------------*/ |
| 129 | /** |
| 130 | * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) |
| 131 | * |
| 132 | * |
| 133 | * |
| 134 | * @param[in] pSciMapTbl - Table data pointer |
| 135 | * @param[in] FchResetDataBlock |
| 136 | * |
| 137 | */ |
| 138 | VOID |
| 139 | ProgramFchSciMapTbl ( |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 140 | CONST IN SCI_MAP_CONTROL *pSciMapTbl, |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 141 | IN FCH_RESET_DATA_BLOCK *FchResetDataBlock |
| 142 | ) |
| 143 | { |
| 144 | AMD_CONFIG_PARAMS *StdHeader; |
| 145 | |
| 146 | UINT32 ddtempVar; |
| 147 | StdHeader = FchResetDataBlock->StdHeader; |
| 148 | |
| 149 | if (pSciMapTbl != NULL) { |
| 150 | while (pSciMapTbl->InputPin != 0xFF) { |
| 151 | if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) { |
| 152 | ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin; |
| 153 | if (((pSciMapTbl->InputPin == 0x78 ) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \ |
| 154 | ((pSciMapTbl->InputPin == 0x79 ) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) { |
| 155 | } else { |
| 156 | LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader); |
| 157 | } |
| 158 | } else { |
| 159 | //Assert Warning "SCI map is invalid" |
| 160 | } |
| 161 | pSciMapTbl++; |
| 162 | } |
| 163 | } |
| 164 | } |
| 165 | |
| 166 | /*----------------------------------------------------------------------------------------*/ |
| 167 | /** |
| 168 | * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data) |
| 169 | * |
| 170 | * |
| 171 | * |
| 172 | * @param[in] pGpioTbl - Table data pointer |
| 173 | * @param[in] FchResetDataBlock |
| 174 | * |
| 175 | */ |
| 176 | VOID |
| 177 | ProgramFchGpioTbl ( |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 178 | CONST IN GPIO_CONTROL *pGpioTbl, |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 179 | IN FCH_RESET_DATA_BLOCK *FchResetDataBlock |
| 180 | ) |
| 181 | { |
| 182 | AMD_CONFIG_PARAMS *StdHeader; |
| 183 | |
| 184 | UINT32 ddtempVar; |
| 185 | StdHeader = FchResetDataBlock->StdHeader; |
| 186 | |
| 187 | if (pGpioTbl != NULL) { |
| 188 | while (pGpioTbl->GpioPin != 0xFF) { |
| 189 | ddtempVar = ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin; |
| 190 | LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->PinFunction, StdHeader); |
| 191 | ddtempVar = ACPI_MMIO_BASE | GPIO_BASE | pGpioTbl->GpioPin; |
| 192 | LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pGpioTbl->CfgByte, StdHeader); |
| 193 | pGpioTbl++; |
| 194 | } |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | /*----------------------------------------------------------------------------------------*/ |
| 199 | /** |
| 200 | * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data) |
| 201 | * |
| 202 | * |
| 203 | * |
| 204 | * @param[in] pSataPhyTbl - Table data pointer |
| 205 | * @param[in] FchResetDataBlock |
| 206 | * |
| 207 | */ |
| 208 | VOID |
| 209 | ProgramFchSataPhyTbl ( |
| 210 | IN SATA_PHY_CONTROL *pSataPhyTbl, |
| 211 | IN FCH_RESET_DATA_BLOCK *FchResetDataBlock |
| 212 | ) |
| 213 | { |
| 214 | AMD_CONFIG_PARAMS *StdHeader; |
| 215 | |
| 216 | //UINT32 ddtempVar; |
| 217 | StdHeader = FchResetDataBlock->StdHeader; |
| 218 | |
| 219 | if (pSataPhyTbl != NULL) { |
| 220 | while (pSataPhyTbl->PhyData != 0xFFFFFFFF) { |
| 221 | //to be implemented |
| 222 | pSataPhyTbl++; |
| 223 | } |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | /** |
| 228 | * GetChipSysMode - Get Chip status |
| 229 | * |
| 230 | * |
| 231 | * @param[in] Value - Return Chip strap status |
| 232 | * StrapStatus [15.0] - Hudson-2 chip Strap Status |
| 233 | * @li <b>0001</b> - Not USED FWH |
| 234 | * @li <b>0002</b> - Not USED LPC ROM |
| 235 | * @li <b>0004</b> - EC enabled |
| 236 | * @li <b>0008</b> - Reserved |
| 237 | * @li <b>0010</b> - Internal Clock mode |
| 238 | * @param[in] StdHeader |
| 239 | * |
| 240 | */ |
| 241 | VOID |
| 242 | GetChipSysMode ( |
| 243 | IN VOID *Value, |
| 244 | IN AMD_CONFIG_PARAMS *StdHeader |
| 245 | ) |
| 246 | { |
| 247 | LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader); |
| 248 | } |
| 249 | |
| 250 | /** |
| 251 | * IsImcEnabled - Is IMC Enabled |
| 252 | * @retval TRUE for IMC Enabled; FALSE for IMC Disabled |
| 253 | */ |
| 254 | BOOLEAN |
| 255 | IsImcEnabled ( |
| 256 | IN AMD_CONFIG_PARAMS *StdHeader |
| 257 | ) |
| 258 | { |
| 259 | UINT8 dbSysConfig; |
| 260 | GetChipSysMode (&dbSysConfig, StdHeader); |
| 261 | if (dbSysConfig & ChipSysEcEnable) { |
| 262 | return TRUE; |
| 263 | } else { |
| 264 | return FALSE; |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | |
| 269 | /** |
| 270 | * GetEfuseStatue - Get Efuse status |
| 271 | * |
| 272 | * |
| 273 | * @param[in] Value - Return Chip strap status |
| 274 | * @param[in] StdHeader |
| 275 | * |
| 276 | */ |
| 277 | VOID |
| 278 | GetEfuseStatus ( |
| 279 | IN VOID *Value, |
| 280 | IN AMD_CONFIG_PARAMS *StdHeader |
| 281 | ) |
| 282 | { |
| 283 | UINT8 Or8; |
| 284 | UINT8 Mask8; |
| 285 | |
| 286 | Or8 = BIT5; |
| 287 | Mask8 = BIT5; |
| 288 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); |
| 289 | LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 ), Value, StdHeader); |
| 290 | LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 + 1), Value, StdHeader); |
| 291 | Or8 = 0; |
| 292 | Mask8 = BIT5; |
| 293 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); |
| 294 | } |
| 295 | |
| 296 | /*----------------------------------------------------------------------------------------*/ |
| 297 | /** |
| 298 | * SbSleepTrapControl - SB Sleep Trap Control |
| 299 | * |
| 300 | * |
| 301 | * |
| 302 | * @param[in] SleepTrap - Whether sleep trap is enabled |
| 303 | * |
| 304 | */ |
| 305 | VOID |
| 306 | SbSleepTrapControl ( |
| 307 | IN BOOLEAN SleepTrap |
| 308 | ) |
| 309 | { |
| 310 | if (SleepTrap) { |
| 311 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); |
| 312 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2; |
| 313 | |
| 314 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) &= ~ (BIT5); |
| 315 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); |
| 316 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1; |
| 317 | } else { |
| 318 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xBE ) |= BIT5; |
| 319 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); |
| 320 | ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0; |
| 321 | |
| 322 | ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); |
| 323 | } |
| 324 | } |