| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Install of build option: Memory |
| 6 | * |
| 7 | * Contains AMD AGESA install macros and test conditions. Output is the |
| 8 | * defaults tables reflecting the User's build options selection. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: Options |
| 13 | * @e \$Revision: 64574 $ @e \$Date: 2012-01-25 01:01:51 -0600 (Wed, 25 Jan 2012) $ |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
| Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 19 | * |
| Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 30 | * |
| Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * |
| 42 | ***************************************************************************/ |
| 43 | |
| 44 | #ifndef _OPTION_MEMORY_INSTALL_H_ |
| 45 | #define _OPTION_MEMORY_INSTALL_H_ |
| 46 | |
| 47 | /* Memory Includes */ |
| 48 | #include "OptionMemory.h" |
| 49 | |
| 50 | /*------------------------------------------------------------------------------- |
| 51 | * This option file is designed to be included into the platform solution install |
| 52 | * file. The platform solution install file will define the options status. |
| 53 | * Check to validate the definition |
| 54 | */ |
| 55 | |
| 56 | /*---------------------------------------------------------------------------------- |
| 57 | * FEATURE BLOCK FUNCTIONS |
| 58 | * |
| 59 | * This section defines function names that depend upon options that are selected |
| 60 | * in the platform solution install file. |
| 61 | */ |
| 62 | BOOLEAN MemFDefRet ( |
| 63 | IN OUT MEM_NB_BLOCK *NBPtr |
| 64 | ) |
| 65 | { |
| 66 | return FALSE; |
| 67 | } |
| 68 | |
| 69 | BOOLEAN MemMDefRet ( |
| 70 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 71 | ) |
| 72 | { |
| 73 | return TRUE; |
| 74 | } |
| 75 | |
| 76 | BOOLEAN MemMDefRetFalse ( |
| 77 | IN MEM_MAIN_DATA_BLOCK *MMPtr |
| 78 | ) |
| 79 | { |
| 80 | return FALSE; |
| 81 | } |
| 82 | |
| 83 | /* -----------------------------------------------------------------------------*/ |
| 84 | /** |
| 85 | * |
| 86 | * |
| 87 | * This function initializes the northbridge block for dimm identification translator |
| 88 | * |
| 89 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 90 | * @param[in,out] *MemPtr - Pointer to the MEM_DATA_STRUCT |
| 91 | * @param[in,out] NodeID - ID of current node to construct |
| 92 | * @return TRUE - This is the correct constructor for the targeted node. |
| 93 | * @return FALSE - This isn't the correct constructor for the targeted node. |
| 94 | */ |
| 95 | BOOLEAN MemNIdentifyDimmConstructorRetDef ( |
| 96 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 97 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 98 | IN UINT8 NodeID |
| 99 | ) |
| 100 | { |
| 101 | return FALSE; |
| 102 | } |
| 103 | /*---------------------------------------------------------------------------------- |
| 104 | * TABLE FEATURE BLOCK FUNCTIONS |
| 105 | * |
| 106 | * This section defines function names that depend upon options that are selected |
| 107 | * in the platform solution install file. |
| 108 | */ |
| 109 | UINT8 MemFTableDefRet ( |
| 110 | IN OUT MEM_TABLE_ALIAS **MTPtr |
| 111 | ) |
| 112 | { |
| 113 | return 0; |
| 114 | } |
| 115 | /*---------------------------------------------------------------------------------- |
| 116 | * FEATURE S3 BLOCK FUNCTIONS |
| 117 | * |
| 118 | * This section defines function names that depend upon options that are selected |
| 119 | * in the platform solution install file. |
| 120 | */ |
| 121 | BOOLEAN MemFS3DefConstructorRet ( |
| 122 | IN OUT VOID *S3NBPtr, |
| 123 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 124 | IN UINT8 NodeID |
| 125 | ) |
| 126 | { |
| Kyösti Mälkki | 6aa45c0 | 2016-06-24 16:37:05 +0300 | [diff] [blame] | 127 | return FALSE; |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | #if (OPTION_MEMCTLR_DR == TRUE) |
| 131 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 132 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 133 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr; |
| 134 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr |
| 135 | #else |
| 136 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet |
| 137 | #endif |
| 138 | #else |
| 139 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet |
| 140 | #endif |
| 141 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 142 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr; |
| 143 | #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr |
| 144 | #else |
| 145 | #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef |
| 146 | #endif |
| 147 | #endif |
| 148 | |
| 149 | #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) |
| 150 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 151 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 152 | #if (OPTION_MEMCTLR_Ni == TRUE) |
| 153 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi; |
| 154 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi |
| 155 | #else |
| 156 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet |
| 157 | #endif |
| 158 | #if (OPTION_MEMCTLR_DA == TRUE) |
| 159 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA; |
| 160 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA |
| 161 | #else |
| 162 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet |
| 163 | #endif |
| 164 | #if (OPTION_MEMCTLR_PH == TRUE) |
| 165 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh; |
| 166 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh |
| 167 | #else |
| 168 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet |
| 169 | #endif |
| 170 | #if (OPTION_MEMCTLR_RB == TRUE) |
| 171 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb; |
| 172 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb |
| 173 | #else |
| 174 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet |
| 175 | #endif |
| 176 | #endif |
| 177 | #else |
| 178 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet |
| 179 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet |
| 180 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet |
| 181 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet |
| 182 | #endif |
| 183 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 184 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA; |
| 185 | #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA |
| 186 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb; |
| 187 | #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb |
| 188 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh; |
| 189 | #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh |
| 190 | #else |
| 191 | #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef |
| 192 | #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef |
| 193 | #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef |
| 194 | #endif |
| 195 | #endif |
| 196 | |
| 197 | #if (OPTION_MEMCTLR_OR == TRUE) |
| 198 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 199 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 200 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr; |
| 201 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr |
| 202 | #else |
| 203 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet |
| 204 | #endif |
| 205 | #else |
| 206 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet |
| 207 | #endif |
| 208 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 209 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr; |
| 210 | #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr |
| 211 | #else |
| 212 | #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef |
| 213 | #endif |
| 214 | #endif |
| 215 | |
| 216 | #if (OPTION_MEMCTLR_HY == TRUE) |
| 217 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 218 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 219 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy; |
| 220 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy |
| 221 | #else |
| 222 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet |
| 223 | #endif |
| 224 | #else |
| 225 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet |
| 226 | #endif |
| 227 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 228 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy; |
| 229 | #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy |
| 230 | #else |
| 231 | #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef |
| 232 | #endif |
| 233 | #endif |
| 234 | |
| 235 | #if (OPTION_MEMCTLR_C32 == TRUE) |
| 236 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 237 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 238 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32; |
| 239 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32 |
| 240 | #else |
| 241 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet |
| 242 | #endif |
| 243 | #else |
| 244 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet |
| 245 | #endif |
| 246 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 247 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32; |
| 248 | #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32 |
| 249 | #else |
| 250 | #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef |
| 251 | #endif |
| 252 | #endif |
| 253 | |
| 254 | #if (OPTION_MEMCTLR_LN == TRUE) |
| 255 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 256 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 257 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockLN; |
| 258 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemS3ResumeConstructNBBlockLN |
| 259 | #else |
| 260 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet |
| 261 | #endif |
| 262 | #else |
| 263 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN MemFS3DefConstructorRet |
| 264 | #endif |
| 265 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 266 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorLN; |
| 267 | #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorLN |
| 268 | #else |
| 269 | #define MEM_IDENDIMM_LN MemNIdentifyDimmConstructorRetDef |
| 270 | #endif |
| 271 | #endif |
| 272 | |
| 273 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 274 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 275 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 276 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockON; |
| 277 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemS3ResumeConstructNBBlockON |
| 278 | #else |
| 279 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet |
| 280 | #endif |
| 281 | #else |
| 282 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON MemFS3DefConstructorRet |
| 283 | #endif |
| 284 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 285 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorON; |
| 286 | #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorON |
| 287 | #else |
| 288 | #define MEM_IDENDIMM_ON MemNIdentifyDimmConstructorRetDef |
| 289 | #endif |
| 290 | #endif |
| 291 | |
| 292 | #if (OPTION_MEMCTLR_TN == TRUE) |
| 293 | #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)) |
| 294 | #if (OPTION_S3_MEM_SUPPORT == TRUE) |
| 295 | extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockTN; |
| 296 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemS3ResumeConstructNBBlockTN |
| 297 | #else |
| 298 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet |
| 299 | #endif |
| 300 | #else |
| 301 | #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN MemFS3DefConstructorRet |
| 302 | #endif |
| 303 | #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE) |
| 304 | extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorTN; |
| 305 | #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorTN |
| 306 | #else |
| 307 | #define MEM_IDENDIMM_TN MemNIdentifyDimmConstructorRetDef |
| 308 | #endif |
| 309 | #endif |
| 310 | |
| 311 | |
| 312 | |
| 313 | |
| 314 | /*---------------------------------------------------------------------------------- |
| 315 | * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS |
| 316 | * |
| 317 | *---------------------------------------------------------------------------------- |
| 318 | */ |
| 319 | #define MEM_NB_SUPPORT_DR |
| 320 | #define MEM_NB_SUPPORT_RB |
| 321 | #define MEM_NB_SUPPORT_DA |
| 322 | #define MEM_NB_SUPPORT_Ni |
| 323 | #define MEM_NB_SUPPORT_PH |
| 324 | #define MEM_NB_SUPPORT_HY |
| 325 | #define MEM_NB_SUPPORT_LN |
| 326 | #define MEM_NB_SUPPORT_OR |
| 327 | #define MEM_NB_SUPPORT_C32 |
| 328 | #define MEM_NB_SUPPORT_ON |
| 329 | #define MEM_NB_SUPPORT_TN |
| 330 | #define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 } |
| 331 | |
| 332 | #if (AGESA_ENTRY_INIT_POST == TRUE) |
| 333 | /*---------------------------------------------------------------------------------- |
| 334 | * FLOW CONTROL FUNCTION |
| 335 | * |
| 336 | * This section selects the function that controls the memory initialization sequence |
| 337 | * based upon the number of processor families that the BIOS will support. |
| 338 | */ |
| 339 | extern MEM_FLOW_CFG MemMFlowDef; |
| 340 | |
| 341 | #if (OPTION_MEMCTLR_DR == TRUE) |
| 342 | extern MEM_FLOW_CFG MemMFlowDr; |
| 343 | #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr, |
| 344 | #else |
| 345 | #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef, |
| 346 | #endif |
| 347 | #if (OPTION_MEMCTLR_DA == TRUE) |
| 348 | extern MEM_FLOW_CFG MemMFlowDA; |
| 349 | #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA, |
| 350 | #else |
| 351 | #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef, |
| 352 | #endif |
| 353 | #if (OPTION_MEMCTLR_HY == TRUE) |
| 354 | extern MEM_FLOW_CFG MemMFlowHy; |
| 355 | #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy, |
| 356 | #else |
| 357 | #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef, |
| 358 | #endif |
| 359 | #if (OPTION_MEMCTLR_OR == TRUE) |
| 360 | extern MEM_FLOW_CFG MemMFlowOr; |
| 361 | #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr, |
| 362 | #else |
| 363 | #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef, |
| 364 | #endif |
| 365 | #if (OPTION_MEMCTLR_LN == TRUE) |
| 366 | extern MEM_FLOW_CFG MemMFlowLN; |
| 367 | #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN, |
| 368 | #else |
| 369 | #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef, |
| 370 | #endif |
| 371 | #if (OPTION_MEMCTLR_C32 == TRUE) |
| 372 | extern MEM_FLOW_CFG MemMFlowC32; |
| 373 | #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32, |
| 374 | #else |
| 375 | #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef, |
| 376 | #endif |
| 377 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 378 | extern MEM_FLOW_CFG MemMFlowON; |
| 379 | #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON, |
| 380 | #else |
| 381 | #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef, |
| 382 | #endif |
| 383 | #if (OPTION_MEMCTLR_Ni == TRUE) |
| 384 | extern MEM_FLOW_CFG MemMFlowDA; |
| 385 | #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA, |
| 386 | #else |
| 387 | #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef, |
| 388 | #endif |
| 389 | #if (OPTION_MEMCTLR_RB == TRUE) |
| 390 | extern MEM_FLOW_CFG MemMFlowRb; |
| 391 | #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb, |
| 392 | #else |
| 393 | #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef, |
| 394 | #endif |
| 395 | #if (OPTION_MEMCTLR_PH == TRUE) |
| 396 | extern MEM_FLOW_CFG MemMFlowPh; |
| 397 | #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh, |
| 398 | #else |
| 399 | #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef, |
| 400 | #endif |
| 401 | #if (OPTION_MEMCTLR_TN == TRUE) |
| 402 | extern MEM_FLOW_CFG MemMFlowTN; |
| 403 | #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowTN, |
| 404 | #else |
| 405 | #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowDef, |
| 406 | #endif |
| 407 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 408 | MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 409 | MEM_MAIN_FLOW_CONTROL_PTR_Dr |
| 410 | MEM_MAIN_FLOW_CONTROL_PTR_DA |
| 411 | MEM_MAIN_FLOW_CONTROL_PTR_RB |
| 412 | MEM_MAIN_FLOW_CONTROL_PTR_PH |
| 413 | MEM_MAIN_FLOW_CONTROL_PTR_Hy |
| 414 | MEM_MAIN_FLOW_CONTROL_PTR_OR |
| 415 | MEM_MAIN_FLOW_CONTROL_PTR_LN |
| 416 | MEM_MAIN_FLOW_CONTROL_PTR_C32 |
| 417 | MEM_MAIN_FLOW_CONTROL_PTR_ON |
| 418 | MemMFlowDef, |
| 419 | MEM_MAIN_FLOW_CONTROL_PTR_Ni |
| 420 | MEM_MAIN_FLOW_CONTROL_PTR_TN |
| 421 | MemMFlowDef, |
| 422 | MemMFlowDef, |
| 423 | NULL |
| 424 | }; |
| 425 | |
| 426 | #if (OPTION_ONLINE_SPARE == TRUE) |
| 427 | extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare; |
| 428 | #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMOnlineSpare |
| 429 | extern OPTION_MEM_FEATURE_NB MemFOnlineSpare; |
| 430 | #define MEM_FEATURE_ONLINE_SPARE MemFOnlineSpare |
| 431 | #else |
| 432 | #define MEM_MAIN_FEATURE_ONLINE_SPARE MemMDefRet |
| 433 | #define MEM_FEATURE_ONLINE_SPARE MemFDefRet |
| 434 | #endif |
| 435 | |
| 436 | #if (OPTION_MEM_RESTORE == TRUE) |
| 437 | extern OPTION_MEM_FEATURE_MAIN MemMContextSave; |
| 438 | extern OPTION_MEM_FEATURE_MAIN MemMContextRestore; |
| 439 | #define MEM_MAIN_FEATURE_MEM_SAVE MemMContextSave |
| 440 | #define MEM_MAIN_FEATURE_MEM_RESTORE MemMContextRestore |
| 441 | #else |
| 442 | #define MEM_MAIN_FEATURE_MEM_SAVE MemMDefRet |
| 443 | #define MEM_MAIN_FEATURE_MEM_RESTORE MemMDefRetFalse |
| 444 | #endif |
| 445 | |
| 446 | #if (OPTION_BANK_INTERLEAVE == TRUE) |
| 447 | extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks; |
| 448 | #define MEM_FEATURE_BANK_INTERLEAVE MemFInterleaveBanks |
| 449 | extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks; |
| 450 | #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks |
| 451 | #else |
| 452 | #define MEM_FEATURE_BANK_INTERLEAVE MemFDefRet |
| 453 | #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet |
| 454 | #endif |
| 455 | |
| 456 | #if (OPTION_NODE_INTERLEAVE == TRUE) |
| 457 | extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes; |
| 458 | #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMInterleaveNodes |
| 459 | extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes; |
| 460 | extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes; |
| 461 | #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFCheckInterleaveNodes |
| 462 | #define MEM_FEATURE_NODE_INTERLEAVE MemFInterleaveNodes |
| 463 | #else |
| 464 | #define MEM_FEATURE_NODE_INTERLEAVE_CHECK MemFDefRet |
| 465 | #define MEM_FEATURE_NODE_INTERLEAVE MemFDefRet |
| 466 | #define MEM_MAIN_FEATURE_NODE_INTERLEAVE MemMDefRet |
| 467 | #endif |
| 468 | |
| 469 | #if (OPTION_DCT_INTERLEAVE == TRUE) |
| 470 | extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels; |
| 471 | #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFInterleaveChannels |
| 472 | #else |
| 473 | #define MEM_FEATURE_CHANNEL_INTERLEAVE MemFDefRet |
| 474 | #endif |
| 475 | |
| 476 | #if (OPTION_ECC == TRUE) |
| 477 | extern OPTION_MEM_FEATURE_MAIN MemMEcc; |
| 478 | #define MEM_MAIN_FEATURE_ECC MemMEcc |
| 479 | extern OPTION_MEM_FEATURE_NB MemFCheckECC; |
| 480 | extern OPTION_MEM_FEATURE_NB MemFInitECC; |
| 481 | #define MEM_FEATURE_CK_ECC MemFCheckECC |
| 482 | #define MEM_FEATURE_ECC MemFInitECC |
| 483 | #define MEM_FEATURE_ECCX8 MemMDefRet |
| 484 | #else |
| 485 | #define MEM_MAIN_FEATURE_ECC MemMDefRet |
| 486 | #define MEM_FEATURE_CK_ECC MemFDefRet |
| 487 | #define MEM_FEATURE_ECC MemFDefRet |
| 488 | #define MEM_FEATURE_ECCX8 MemMDefRet |
| 489 | #endif |
| 490 | |
| 491 | |
| 492 | extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr; |
| 493 | #define MEM_MAIN_FEATURE_MEM_CLEAR MemMMctMemClr |
| 494 | |
| 495 | #if (OPTION_DMI == TRUE) |
| 496 | #if (OPTION_DDR3 == TRUE) |
| 497 | extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3; |
| 498 | #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3 |
| 499 | #else |
| 500 | extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2; |
| 501 | #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2 |
| 502 | #endif |
| 503 | #else |
| 504 | #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet |
| 505 | #endif |
| 506 | |
| 507 | |
| 508 | #if (OPTION_DDR3 == TRUE) |
| 509 | extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal; |
| 510 | extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3; |
| 511 | extern OPTION_MEM_FEATURE_NB MemFLvDdr3; |
| 512 | #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal |
| 513 | #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3 |
| 514 | #define MEM_FEATURE_LVDDR3 MemFLvDdr3 |
| 515 | #else |
| 516 | #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet |
| 517 | #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet |
| 518 | #define MEM_FEATURE_LVDDR3 MemFDefRet |
| 519 | #endif |
| 520 | |
| 521 | extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion; |
| 522 | #define MEM_FEATURE_REGION_INTERLEAVE MemFInterleaveRegion |
| 523 | |
| 524 | extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc; |
| 525 | #define MEM_MAIN_FEATURE_UMAALLOC MemMUmaAlloc |
| 526 | |
| 527 | #if (OPTION_PARALLEL_TRAINING == TRUE) |
| 528 | extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining; |
| 529 | #define MEM_MAIN_FEATURE_TRAINING MemMParallelTraining |
| 530 | #else |
| 531 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 532 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 533 | #endif |
| 534 | |
| 535 | #if (OPTION_DIMM_EXCLUDE == TRUE) |
| 536 | extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM; |
| 537 | #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMRASExcludeDIMM |
| 538 | extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM; |
| 539 | #define MEM_FEATURE_DIMM_EXCLUDE MemFRASExcludeDIMM |
| 540 | #else |
| 541 | #define MEM_FEATURE_DIMM_EXCLUDE MemFDefRet |
| 542 | #define MEM_MAIN_FEATURE_DIMM_EXCLUDE MemMDefRet |
| 543 | #endif |
| 544 | |
| 545 | /*---------------------------------------------------------------------------------- |
| 546 | * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS |
| 547 | * |
| 548 | *---------------------------------------------------------------------------------- |
| 549 | */ |
| 550 | #if OPTION_DDR2 == TRUE |
| 551 | extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2; |
| 552 | #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2, |
| 553 | #if (OPTION_HW_DRAM_INIT == TRUE) |
| 554 | extern MEM_TECH_FEAT MemTDramInitHw; |
| 555 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw |
| 556 | #else |
| 557 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef |
| 558 | #endif |
| 559 | #if (OPTION_SW_DRAM_INIT == TRUE) |
| 560 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef |
| 561 | #else |
| 562 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef |
| 563 | #endif |
| 564 | #else |
| 565 | #define MEM_TECH_CONSTRUCTOR_DDR2 |
| 566 | #endif |
| 567 | #if OPTION_DDR3 == TRUE |
| 568 | extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3; |
| 569 | #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3, |
| 570 | #if (OPTION_HW_DRAM_INIT == TRUE) |
| 571 | extern MEM_TECH_FEAT MemTDramInitHw; |
| 572 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw |
| 573 | #else |
| 574 | #define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef |
| 575 | #endif |
| 576 | #if (OPTION_SW_DRAM_INIT == TRUE) |
| 577 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTDramInitSw3 |
| 578 | #else |
| 579 | #define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef |
| 580 | #endif |
| 581 | #else |
| 582 | #define MEM_TECH_CONSTRUCTOR_DDR3 |
| 583 | #endif |
| 584 | |
| 585 | /*--------------------------------------------------------------------------------------------------- |
| 586 | * FEATURE BLOCKS |
| 587 | * |
| 588 | * This section instantiates a feature block structure for each memory controller installed |
| 589 | * by the platform solution install file. |
| 590 | *--------------------------------------------------------------------------------------------------- |
| 591 | */ |
| 592 | |
| 593 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 594 | extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb; |
| 595 | #endif |
| 596 | extern OPTION_MEM_FEATURE_NB MemFStandardTraining; |
| 597 | |
| 598 | /*--------------------------------------------------------------------------------------------------- |
| 599 | * DEERHOUND FEATURE BLOCK |
| 600 | *--------------------------------------------------------------------------------------------------- |
| 601 | */ |
| 602 | #if (OPTION_MEMCTLR_DR == TRUE) |
| 603 | #if OPTION_DDR2 |
| 604 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 605 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 606 | #endif |
| 607 | #if OPTION_DDR3 |
| 608 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 609 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 610 | #endif |
| 611 | |
| 612 | #undef MEM_TECH_FEATURE_CPG |
| 613 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 614 | |
| 615 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 616 | #undef MEM_TECH_FEATURE_HWRXEN |
| 617 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 618 | #else |
| 619 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 620 | #undef MEM_TECH_FEATURE_HWRXEN |
| 621 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 622 | #endif |
| 623 | |
| 624 | #undef MEM_MAIN_FEATURE_TRAINING |
| 625 | #undef MEM_FEATURE_TRAINING |
| 626 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 627 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 628 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 629 | |
| 630 | MEM_FEAT_BLOCK_NB MemFeatBlockDr = { |
| 631 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 632 | MEM_FEATURE_ONLINE_SPARE, |
| 633 | MEM_FEATURE_BANK_INTERLEAVE, |
| 634 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 635 | MEM_FEATURE_NODE_INTERLEAVE_CHECK, |
| 636 | MEM_FEATURE_NODE_INTERLEAVE, |
| 637 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 638 | MemFDefRet, |
| 639 | MEM_FEATURE_CK_ECC, |
| 640 | MEM_FEATURE_ECC, |
| 641 | MEM_FEATURE_TRAINING, |
| 642 | MEM_FEATURE_LVDDR3, |
| 643 | MemFDefRet, |
| 644 | MEM_TECH_FEATURE_DRAMINIT, |
| 645 | MEM_FEATURE_DIMM_EXCLUDE, |
| 646 | MemFDefRet, |
| 647 | MEM_TECH_FEATURE_CPG, |
| 648 | MEM_TECH_FEATURE_HWRXEN |
| 649 | }; |
| 650 | |
| 651 | #undef MEM_NB_SUPPORT_DR |
| 652 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR; |
| 653 | extern MEM_INITIALIZER MemNInitDefaultsDR; |
| 654 | |
| 655 | |
| 656 | #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, |
| 657 | #endif // OPTION_MEMCTRL_DR |
| 658 | |
| 659 | /*--------------------------------------------------------------------------------------------------- |
| 660 | * DASHOUND FEATURE BLOCK |
| 661 | *--------------------------------------------------------------------------------------------------- |
| 662 | */ |
| 663 | #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) |
| 664 | #if OPTION_DDR2 |
| 665 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 666 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 667 | #endif |
| 668 | #if OPTION_DDR3 |
| 669 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 670 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 671 | #endif |
| 672 | |
| 673 | #undef MEM_TECH_FEATURE_CPG |
| 674 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 675 | |
| 676 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 677 | #undef MEM_TECH_FEATURE_HWRXEN |
| 678 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 679 | #else |
| 680 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 681 | #undef MEM_TECH_FEATURE_HWRXEN |
| 682 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 683 | #endif |
| 684 | |
| 685 | #undef MEM_MAIN_FEATURE_TRAINING |
| 686 | #undef MEM_FEATURE_TRAINING |
| 687 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 688 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 689 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 690 | |
| 691 | #if (OPTION_MEMCTLR_Ni == TRUE) |
| 692 | MEM_FEAT_BLOCK_NB MemFeatBlockNi = { |
| 693 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 694 | MemFDefRet, |
| 695 | MEM_FEATURE_BANK_INTERLEAVE, |
| 696 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 697 | MemFDefRet, |
| 698 | MemFDefRet, |
| 699 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 700 | MEM_FEATURE_REGION_INTERLEAVE, |
| 701 | MEM_FEATURE_CK_ECC, |
| 702 | MEM_FEATURE_ECC, |
| 703 | MEM_FEATURE_TRAINING, |
| 704 | MEM_FEATURE_LVDDR3, |
| 705 | MemFDefRet, |
| 706 | MEM_TECH_FEATURE_DRAMINIT, |
| 707 | MEM_FEATURE_DIMM_EXCLUDE, |
| 708 | MemFDefRet, |
| 709 | MEM_TECH_FEATURE_CPG, |
| 710 | MEM_TECH_FEATURE_HWRXEN |
| 711 | }; |
| 712 | |
| 713 | #undef MEM_NB_SUPPORT_Ni |
| 714 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi; |
| 715 | extern MEM_INITIALIZER MemNInitDefaultsNi; |
| 716 | |
| 717 | #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA }, |
| 718 | #endif |
| 719 | |
| 720 | #if (OPTION_MEMCTLR_PH == TRUE) |
| 721 | MEM_FEAT_BLOCK_NB MemFeatBlockPh = { |
| 722 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 723 | MemFDefRet, |
| 724 | MEM_FEATURE_BANK_INTERLEAVE, |
| 725 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 726 | MemFDefRet, |
| 727 | MemFDefRet, |
| 728 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 729 | MEM_FEATURE_REGION_INTERLEAVE, |
| 730 | MEM_FEATURE_CK_ECC, |
| 731 | MEM_FEATURE_ECC, |
| 732 | MEM_FEATURE_TRAINING, |
| 733 | MEM_FEATURE_LVDDR3, |
| 734 | MemFDefRet, |
| 735 | MEM_TECH_FEATURE_DRAMINIT, |
| 736 | MEM_FEATURE_DIMM_EXCLUDE, |
| 737 | MemFDefRet, |
| 738 | MEM_TECH_FEATURE_CPG, |
| 739 | MEM_TECH_FEATURE_HWRXEN |
| 740 | }; |
| 741 | |
| 742 | #undef MEM_NB_SUPPORT_PH |
| 743 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh; |
| 744 | extern MEM_INITIALIZER MemNInitDefaultsPh; |
| 745 | |
| 746 | #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, |
| 747 | #endif |
| 748 | |
| 749 | #if (OPTION_MEMCTLR_RB == TRUE) |
| 750 | MEM_FEAT_BLOCK_NB MemFeatBlockRb = { |
| 751 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 752 | MemFDefRet, |
| 753 | MEM_FEATURE_BANK_INTERLEAVE, |
| 754 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 755 | MemFDefRet, |
| 756 | MemFDefRet, |
| 757 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 758 | MEM_FEATURE_REGION_INTERLEAVE, |
| 759 | MEM_FEATURE_CK_ECC, |
| 760 | MEM_FEATURE_ECC, |
| 761 | MEM_FEATURE_TRAINING, |
| 762 | MEM_FEATURE_LVDDR3, |
| 763 | MemFDefRet, |
| 764 | MEM_TECH_FEATURE_DRAMINIT, |
| 765 | MEM_FEATURE_DIMM_EXCLUDE, |
| 766 | MemFDefRet, |
| 767 | MEM_TECH_FEATURE_CPG, |
| 768 | MEM_TECH_FEATURE_HWRXEN |
| 769 | }; |
| 770 | |
| 771 | #undef MEM_NB_SUPPORT_RB |
| 772 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb; |
| 773 | extern MEM_INITIALIZER MemNInitDefaultsRb; |
| 774 | |
| 775 | #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, |
| 776 | #endif |
| 777 | |
| 778 | #if (OPTION_MEMCTLR_DA == TRUE) |
| 779 | MEM_FEAT_BLOCK_NB MemFeatBlockDA = { |
| 780 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 781 | MemFDefRet, |
| 782 | MEM_FEATURE_BANK_INTERLEAVE, |
| 783 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 784 | MemFDefRet, |
| 785 | MemFDefRet, |
| 786 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 787 | MEM_FEATURE_REGION_INTERLEAVE, |
| 788 | MEM_FEATURE_CK_ECC, |
| 789 | MEM_FEATURE_ECC, |
| 790 | MEM_FEATURE_TRAINING, |
| 791 | MEM_FEATURE_LVDDR3, |
| 792 | MemFDefRet, |
| 793 | MEM_TECH_FEATURE_DRAMINIT, |
| 794 | MEM_FEATURE_DIMM_EXCLUDE, |
| 795 | MemFDefRet, |
| 796 | MEM_TECH_FEATURE_CPG, |
| 797 | MEM_TECH_FEATURE_HWRXEN |
| 798 | }; |
| 799 | |
| 800 | #undef MEM_NB_SUPPORT_DA |
| 801 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA; |
| 802 | extern MEM_INITIALIZER MemNInitDefaultsDA; |
| 803 | |
| 804 | #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, |
| 805 | #endif |
| 806 | #endif // OPTION_MEMCTRL_DA |
| 807 | |
| 808 | /*--------------------------------------------------------------------------------------------------- |
| 809 | * HYDRA FEATURE BLOCK |
| 810 | *--------------------------------------------------------------------------------------------------- |
| 811 | */ |
| 812 | #if (OPTION_MEMCTLR_HY == TRUE) |
| 813 | #if OPTION_DDR2 |
| 814 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 815 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 816 | #endif |
| 817 | #if OPTION_DDR3 |
| 818 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 819 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 820 | #endif |
| 821 | |
| 822 | #undef MEM_TECH_FEATURE_CPG |
| 823 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 824 | |
| 825 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 826 | #undef MEM_TECH_FEATURE_HWRXEN |
| 827 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 828 | #else |
| 829 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 830 | #undef MEM_TECH_FEATURE_HWRXEN |
| 831 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 832 | #endif |
| 833 | |
| 834 | |
| 835 | #undef MEM_MAIN_FEATURE_TRAINING |
| 836 | #undef MEM_FEATURE_TRAINING |
| 837 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 838 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 839 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 840 | |
| 841 | MEM_FEAT_BLOCK_NB MemFeatBlockHy = { |
| 842 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 843 | MEM_FEATURE_ONLINE_SPARE, |
| 844 | MEM_FEATURE_BANK_INTERLEAVE, |
| 845 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 846 | MEM_FEATURE_NODE_INTERLEAVE_CHECK, |
| 847 | MEM_FEATURE_NODE_INTERLEAVE, |
| 848 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 849 | MemFDefRet, |
| 850 | MEM_FEATURE_CK_ECC, |
| 851 | MEM_FEATURE_ECC, |
| 852 | MEM_FEATURE_TRAINING, |
| 853 | MEM_FEATURE_LVDDR3, |
| 854 | MEM_FEATURE_ONDIMMTHERMAL, |
| 855 | MEM_TECH_FEATURE_DRAMINIT, |
| 856 | MEM_FEATURE_DIMM_EXCLUDE, |
| 857 | MemFDefRet, |
| 858 | MEM_TECH_FEATURE_CPG, |
| 859 | MEM_TECH_FEATURE_HWRXEN |
| 860 | }; |
| 861 | |
| 862 | #undef MEM_NB_SUPPORT_HY |
| 863 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY; |
| 864 | extern MEM_INITIALIZER MemNInitDefaultsHY; |
| 865 | #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, |
| 866 | #endif // OPTION_MEMCTRL_HY |
| 867 | /*--------------------------------------------------------------------------------------------------- |
| 868 | * LLANO FEATURE BLOCK |
| 869 | *--------------------------------------------------------------------------------------------------- |
| 870 | */ |
| 871 | #if (OPTION_MEMCTLR_LN == TRUE) |
| 872 | #if OPTION_DDR2 |
| 873 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 874 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 875 | #endif |
| 876 | #if OPTION_DDR3 |
| 877 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 878 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 879 | #endif |
| 880 | |
| 881 | #if (OPTION_EARLY_SAMPLES == TRUE) |
| 882 | extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportLN; |
| 883 | #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportLN |
| 884 | #else |
| 885 | #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet |
| 886 | #endif |
| 887 | |
| 888 | #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) |
| 889 | extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; |
| 890 | #undef MEM_TECH_FEATURE_CPG |
| 891 | #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb |
| 892 | #else |
| 893 | #undef MEM_TECH_FEATURE_CPG |
| 894 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 895 | #endif |
| 896 | |
| 897 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 898 | #undef MEM_TECH_FEATURE_HWRXEN |
| 899 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 900 | #else |
| 901 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 902 | #undef MEM_TECH_FEATURE_HWRXEN |
| 903 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 904 | #endif |
| 905 | |
| 906 | #undef MEM_MAIN_FEATURE_TRAINING |
| 907 | #undef MEM_FEATURE_TRAINING |
| 908 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 909 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 910 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 911 | |
| 912 | MEM_FEAT_BLOCK_NB MemFeatBlockLn = { |
| 913 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 914 | MemFDefRet, |
| 915 | MEM_FEATURE_BANK_INTERLEAVE, |
| 916 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 917 | MemFDefRet, |
| 918 | MemFDefRet, |
| 919 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 920 | MEM_FEATURE_REGION_INTERLEAVE, |
| 921 | MEM_FEATURE_CK_ECC, |
| 922 | MemFDefRet, |
| 923 | MEM_FEATURE_TRAINING, |
| 924 | MEM_FEATURE_LVDDR3, |
| 925 | MEM_FEATURE_ONDIMMTHERMAL, |
| 926 | MEM_TECH_FEATURE_DRAMINIT, |
| 927 | MEM_FEATURE_DIMM_EXCLUDE, |
| 928 | MEM_EARLY_SAMPLE_SUPPORT, |
| 929 | MEM_TECH_FEATURE_CPG, |
| 930 | MEM_TECH_FEATURE_HWRXEN |
| 931 | }; |
| 932 | #undef MEM_NB_SUPPORT_LN |
| 933 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockLN; |
| 934 | extern MEM_INITIALIZER MemNInitDefaultsLN; |
| 935 | #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockLN, MemNInitDefaultsLN, &MemFeatBlockLn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, |
| 936 | |
| 937 | #endif // OPTION_MEMCTRL_LN |
| 938 | |
| 939 | /*--------------------------------------------------------------------------------------------------- |
| 940 | * ONTARIO FEATURE BLOCK |
| 941 | *--------------------------------------------------------------------------------------------------- |
| 942 | */ |
| 943 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 944 | #if OPTION_DDR2 |
| 945 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 946 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 947 | #endif |
| 948 | #if OPTION_DDR3 |
| 949 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 950 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 951 | #endif |
| 952 | |
| 953 | #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) |
| 954 | extern OPTION_MEM_FEATURE_NB MemNInitCPGClientNb; |
| 955 | #undef MEM_TECH_FEATURE_CPG |
| 956 | #define MEM_TECH_FEATURE_CPG MemNInitCPGClientNb |
| 957 | #else |
| 958 | #undef MEM_TECH_FEATURE_CPG |
| 959 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 960 | #endif |
| 961 | |
| 962 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 963 | #undef MEM_TECH_FEATURE_HWRXEN |
| 964 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 965 | #else |
| 966 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 967 | #undef MEM_TECH_FEATURE_HWRXEN |
| 968 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 969 | #endif |
| 970 | |
| 971 | #undef MEM_MAIN_FEATURE_TRAINING |
| 972 | #undef MEM_FEATURE_TRAINING |
| 973 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 974 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 975 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 976 | |
| 977 | #if (OPTION_EARLY_SAMPLES == TRUE) |
| 978 | extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportON; |
| 979 | #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportON |
| 980 | #else |
| 981 | #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet |
| 982 | #endif |
| 983 | |
| 984 | MEM_FEAT_BLOCK_NB MemFeatBlockOn = { |
| 985 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 986 | MemFDefRet, |
| 987 | MEM_FEATURE_BANK_INTERLEAVE, |
| 988 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 989 | MemFDefRet, |
| 990 | MemFDefRet, |
| 991 | MemFDefRet, |
| 992 | MemFDefRet, |
| 993 | MemFDefRet, |
| 994 | MemFDefRet, |
| 995 | MEM_FEATURE_TRAINING, |
| 996 | MEM_FEATURE_LVDDR3, |
| 997 | MEM_FEATURE_ONDIMMTHERMAL, |
| 998 | MEM_TECH_FEATURE_DRAMINIT, |
| 999 | MEM_FEATURE_DIMM_EXCLUDE, |
| 1000 | MEM_EARLY_SAMPLE_SUPPORT, |
| 1001 | MEM_TECH_FEATURE_CPG, |
| 1002 | MEM_TECH_FEATURE_HWRXEN |
| 1003 | }; |
| 1004 | |
| 1005 | #undef MEM_NB_SUPPORT_ON |
| 1006 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockON; |
| 1007 | extern MEM_INITIALIZER MemNInitDefaultsON; |
| 1008 | #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockON, MemNInitDefaultsON, &MemFeatBlockOn, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, |
| 1009 | |
| 1010 | #endif // OPTION_MEMCTRL_ON |
| 1011 | |
| 1012 | |
| 1013 | |
| 1014 | /*--------------------------------------------------------------------------------------------------- |
| 1015 | * OROCHI FEATURE BLOCK |
| 1016 | *--------------------------------------------------------------------------------------------------- |
| 1017 | */ |
| 1018 | #if (OPTION_MEMCTLR_OR == TRUE) |
| 1019 | #if OPTION_DDR2 |
| 1020 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1021 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 1022 | #endif |
| 1023 | #if OPTION_DDR3 |
| 1024 | #undef MEM_MAIN_FEATURE_LVDDR3 |
| 1025 | extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; |
| 1026 | #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre |
| 1027 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1028 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 1029 | #endif |
| 1030 | |
| 1031 | #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT) |
| 1032 | #undef MEM_FEATURE_REGION_INTERLEAVE |
| 1033 | #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet |
| 1034 | #endif |
| 1035 | |
| 1036 | #if (OPTION_EARLY_SAMPLES == TRUE) |
| 1037 | extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr; |
| 1038 | #define MEM_EARLY_SAMPLE_SUPPORT MemNInitEarlySampleSupportOr |
| 1039 | #else |
| 1040 | #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet |
| 1041 | #endif |
| 1042 | |
| 1043 | #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) |
| 1044 | extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; |
| 1045 | #undef MEM_TECH_FEATURE_CPG |
| 1046 | #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb |
| 1047 | #else |
| 1048 | #undef MEM_TECH_FEATURE_CPG |
| 1049 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 1050 | #endif |
| 1051 | |
| 1052 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1053 | #undef MEM_TECH_FEATURE_HWRXEN |
| 1054 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 1055 | #else |
| 1056 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 1057 | #undef MEM_TECH_FEATURE_HWRXEN |
| 1058 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 1059 | #endif |
| 1060 | |
| 1061 | |
| 1062 | #undef MEM_MAIN_FEATURE_TRAINING |
| 1063 | #undef MEM_FEATURE_TRAINING |
| 1064 | #if (OPTION_RDDQS_2D_TRAINING == TRUE) |
| 1065 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies; |
| 1066 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTrainingUsingAdjacentDies |
| 1067 | #else |
| 1068 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 1069 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 1070 | #endif |
| 1071 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 1072 | |
| 1073 | MEM_FEAT_BLOCK_NB MemFeatBlockOr = { |
| 1074 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 1075 | MEM_FEATURE_ONLINE_SPARE, |
| 1076 | MEM_FEATURE_BANK_INTERLEAVE, |
| 1077 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 1078 | MEM_FEATURE_NODE_INTERLEAVE_CHECK, |
| 1079 | MEM_FEATURE_NODE_INTERLEAVE, |
| 1080 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 1081 | MEM_FEATURE_REGION_INTERLEAVE, |
| 1082 | MEM_FEATURE_CK_ECC, |
| 1083 | MEM_FEATURE_ECC, |
| 1084 | MEM_FEATURE_TRAINING, |
| 1085 | MEM_FEATURE_LVDDR3, |
| 1086 | MEM_FEATURE_ONDIMMTHERMAL, |
| 1087 | MEM_TECH_FEATURE_DRAMINIT, |
| 1088 | MEM_FEATURE_DIMM_EXCLUDE, |
| 1089 | MEM_EARLY_SAMPLE_SUPPORT, |
| 1090 | MEM_TECH_FEATURE_CPG, |
| 1091 | MEM_TECH_FEATURE_HWRXEN |
| 1092 | }; |
| 1093 | |
| 1094 | #undef MEM_NB_SUPPORT_OR |
| 1095 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR; |
| 1096 | extern MEM_INITIALIZER MemNInitDefaultsOR; |
| 1097 | #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, |
| 1098 | #endif // OPTION_MEMCTRL_OR |
| 1099 | |
| 1100 | /*--------------------------------------------------------------------------------------------------- |
| 1101 | * C32 FEATURE BLOCK |
| 1102 | *--------------------------------------------------------------------------------------------------- |
| 1103 | */ |
| 1104 | #if (OPTION_MEMCTLR_C32 == TRUE) |
| 1105 | #if OPTION_DDR2 |
| 1106 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1107 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 1108 | #endif |
| 1109 | #if OPTION_DDR3 |
| 1110 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1111 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 1112 | #endif |
| 1113 | |
| 1114 | #undef MEM_TECH_FEATURE_CPG |
| 1115 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 1116 | |
| 1117 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1118 | #undef MEM_TECH_FEATURE_HWRXEN |
| 1119 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 1120 | #else |
| 1121 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 1122 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 1123 | #endif |
| 1124 | |
| 1125 | #undef MEM_MAIN_FEATURE_TRAINING |
| 1126 | #undef MEM_FEATURE_TRAINING |
| 1127 | #if (OPTION_MEMCTLR_OR == TRUE) |
| 1128 | #if (OPTION_RDDQS_2D_TRAINING == TRUE) |
| 1129 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTrainingUsingAdjacentDies; |
| 1130 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTrainingUsingAdjacentDies |
| 1131 | #else |
| 1132 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 1133 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 1134 | #endif |
| 1135 | #else |
| 1136 | extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 1137 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 1138 | #endif |
| 1139 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 1140 | |
| 1141 | MEM_FEAT_BLOCK_NB MemFeatBlockC32 = { |
| 1142 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 1143 | MEM_FEATURE_ONLINE_SPARE, |
| 1144 | MEM_FEATURE_BANK_INTERLEAVE, |
| 1145 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 1146 | MEM_FEATURE_NODE_INTERLEAVE_CHECK, |
| 1147 | MEM_FEATURE_NODE_INTERLEAVE, |
| 1148 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 1149 | MemFDefRet, |
| 1150 | MEM_FEATURE_CK_ECC, |
| 1151 | MEM_FEATURE_ECC, |
| 1152 | MEM_FEATURE_TRAINING, |
| 1153 | MEM_FEATURE_LVDDR3, |
| 1154 | MEM_FEATURE_ONDIMMTHERMAL, |
| 1155 | MEM_TECH_FEATURE_DRAMINIT, |
| 1156 | MEM_FEATURE_DIMM_EXCLUDE, |
| 1157 | MemFDefRet, |
| 1158 | MEM_TECH_FEATURE_CPG, |
| 1159 | MEM_TECH_FEATURE_HWRXEN |
| 1160 | }; |
| 1161 | |
| 1162 | #undef MEM_NB_SUPPORT_C32 |
| 1163 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32; |
| 1164 | extern MEM_INITIALIZER MemNInitDefaultsC32; |
| 1165 | #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, |
| 1166 | #endif // OPTION_MEMCTRL_C32 |
| 1167 | |
| 1168 | /*--------------------------------------------------------------------------------------------------- |
| 1169 | * TRINITY FEATURE BLOCK |
| 1170 | *--------------------------------------------------------------------------------------------------- |
| 1171 | */ |
| 1172 | #if (OPTION_MEMCTLR_TN == TRUE) |
| 1173 | #if OPTION_DDR2 |
| 1174 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1175 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT |
| 1176 | #endif |
| 1177 | #if OPTION_DDR3 |
| 1178 | #undef MEM_MAIN_FEATURE_LVDDR3 |
| 1179 | extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre; |
| 1180 | #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre |
| 1181 | #undef MEM_TECH_FEATURE_DRAMINIT |
| 1182 | #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT |
| 1183 | #endif |
| 1184 | |
| 1185 | #define MEM_EARLY_SAMPLE_SUPPORT MemFDefRet |
| 1186 | |
| 1187 | #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE) |
| 1188 | extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb; |
| 1189 | #undef MEM_TECH_FEATURE_CPG |
| 1190 | #define MEM_TECH_FEATURE_CPG MemNInitCPGUnb |
| 1191 | #else |
| 1192 | #undef MEM_TECH_FEATURE_CPG |
| 1193 | #define MEM_TECH_FEATURE_CPG MemFDefRet |
| 1194 | #endif |
| 1195 | |
| 1196 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1197 | #undef MEM_TECH_FEATURE_HWRXEN |
| 1198 | #define MEM_TECH_FEATURE_HWRXEN MemNInitDqsTrainRcvrEnHwNb |
| 1199 | #else |
| 1200 | extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb; |
| 1201 | #undef MEM_TECH_FEATURE_HWRXEN |
| 1202 | #define MEM_TECH_FEATURE_HWRXEN MemNDisableDqsTrainRcvrEnHwNb |
| 1203 | #endif |
| 1204 | |
| 1205 | |
| 1206 | #undef MEM_MAIN_FEATURE_TRAINING |
| 1207 | #undef MEM_FEATURE_TRAINING |
| 1208 | //extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining; |
| 1209 | #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining |
| 1210 | #define MEM_FEATURE_TRAINING MemFStandardTraining |
| 1211 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 1212 | CONST MEM_FEAT_BLOCK_NB MemFeatBlockTN = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1213 | MEM_FEAT_BLOCK_NB_STRUCT_VERSION, |
| 1214 | MEM_FEATURE_ONLINE_SPARE, |
| 1215 | MEM_FEATURE_BANK_INTERLEAVE, |
| 1216 | MEM_FEATURE_UNDO_BANK_INTERLEAVE, |
| 1217 | MemFDefRet, |
| 1218 | MemFDefRet, |
| 1219 | MEM_FEATURE_CHANNEL_INTERLEAVE, |
| 1220 | MEM_FEATURE_REGION_INTERLEAVE, |
| 1221 | MEM_FEATURE_CK_ECC, |
| 1222 | MEM_FEATURE_ECC, |
| 1223 | MEM_FEATURE_TRAINING, |
| 1224 | MEM_FEATURE_LVDDR3, |
| 1225 | MEM_FEATURE_ONDIMMTHERMAL, |
| 1226 | MEM_TECH_FEATURE_DRAMINIT, |
| 1227 | MEM_FEATURE_DIMM_EXCLUDE, |
| 1228 | MEM_EARLY_SAMPLE_SUPPORT, |
| 1229 | MEM_TECH_FEATURE_CPG, |
| 1230 | MEM_TECH_FEATURE_HWRXEN |
| 1231 | }; |
| 1232 | |
| 1233 | #undef MEM_NB_SUPPORT_TN |
| 1234 | extern MEM_NB_CONSTRUCTOR MemConstructNBBlockTN; |
| 1235 | extern MEM_INITIALIZER MemNInitDefaultsTN; |
| 1236 | #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockTN, MemNInitDefaultsTN, &MemFeatBlockTN, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN }, |
| 1237 | #endif // OPTION_MEMCTRL_TN |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | /*--------------------------------------------------------------------------------------------------- |
| 1242 | * MAIN FEATURE BLOCK |
| 1243 | *--------------------------------------------------------------------------------------------------- |
| 1244 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 1245 | CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1246 | MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, |
| 1247 | MEM_MAIN_FEATURE_TRAINING, |
| 1248 | MEM_MAIN_FEATURE_DIMM_EXCLUDE, |
| 1249 | MEM_MAIN_FEATURE_ONLINE_SPARE, |
| 1250 | MEM_MAIN_FEATURE_NODE_INTERLEAVE, |
| 1251 | MEM_MAIN_FEATURE_ECC, |
| 1252 | MEM_MAIN_FEATURE_MEM_CLEAR, |
| 1253 | MEM_MAIN_FEATURE_MEM_DMI, |
| 1254 | MemMDefRet, |
| 1255 | MEM_MAIN_FEATURE_LVDDR3, |
| 1256 | MEM_MAIN_FEATURE_UMAALLOC, |
| 1257 | MEM_MAIN_FEATURE_MEM_SAVE, |
| 1258 | MEM_MAIN_FEATURE_MEM_RESTORE |
| 1259 | }; |
| 1260 | |
| 1261 | |
| 1262 | /*--------------------------------------------------------------------------------------------------- |
| 1263 | * Technology Training SPECIFIC CONFIGURATION |
| 1264 | * |
| 1265 | * |
| 1266 | *--------------------------------------------------------------------------------------------------- |
| 1267 | */ |
| 1268 | #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0 |
| 1269 | #if OPTION_MEMCTLR_DR |
| 1270 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; |
| 1271 | #if OPTION_DDR2 |
| 1272 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1273 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1274 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1275 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1276 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1277 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1278 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 |
| 1279 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 |
| 1280 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1281 | #else |
| 1282 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1283 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1284 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1285 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1286 | #else |
| 1287 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef |
| 1288 | #endif |
| 1289 | #endif |
| 1290 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1291 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 |
| 1292 | #else |
| 1293 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1294 | #endif |
| 1295 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1296 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1297 | #else |
| 1298 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1299 | #endif |
| 1300 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1301 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw |
| 1302 | #else |
| 1303 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1304 | #endif |
| 1305 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1306 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1307 | #else |
| 1308 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1309 | #endif |
| 1310 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1311 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency |
| 1312 | #else |
| 1313 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1314 | #endif |
| 1315 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Dr = { |
| 1316 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1317 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1318 | TECH_TRAIN_SW_WL_DDR2, |
| 1319 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1320 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1321 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1322 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1323 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1324 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1325 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1326 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1327 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1328 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1329 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1330 | NULL |
| 1331 | }; |
| 1332 | extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; |
| 1333 | #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb |
| 1334 | extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; |
| 1335 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr }, |
| 1336 | #else |
| 1337 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1338 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1339 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1340 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1341 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1342 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1343 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1344 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1345 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1346 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1347 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1348 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1349 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 1350 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1351 | #endif |
| 1352 | #if OPTION_DDR3 |
| 1353 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1354 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 1355 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1356 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 1357 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 1358 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 1359 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 1360 | #else |
| 1361 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1362 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1363 | #endif |
| 1364 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 1365 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1366 | #else |
| 1367 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1368 | #endif |
| 1369 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1370 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 1371 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 1372 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 1373 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 1374 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 |
| 1375 | #else |
| 1376 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1377 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1378 | #else |
| 1379 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1380 | #endif |
| 1381 | #endif |
| 1382 | #else |
| 1383 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1384 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1385 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1386 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1387 | #else |
| 1388 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1389 | #endif |
| 1390 | #endif |
| 1391 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1392 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 1393 | #else |
| 1394 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1395 | #endif |
| 1396 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1397 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 1398 | #else |
| 1399 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1400 | #endif |
| 1401 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1402 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1403 | #else |
| 1404 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1405 | #endif |
| 1406 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1407 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1408 | #else |
| 1409 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1410 | #endif |
| 1411 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1412 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 1413 | #else |
| 1414 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 1415 | #endif |
| 1416 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 1417 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr; |
| 1418 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Dr = { |
| 1419 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1420 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1421 | TECH_TRAIN_SW_WL_DDR3, |
| 1422 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1423 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1424 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1425 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1426 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1427 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1428 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1429 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1430 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1431 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1432 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1433 | MemTFeatDef |
| 1434 | }; |
| 1435 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr }, |
| 1436 | #else |
| 1437 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1438 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 1439 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1440 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 1441 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1442 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1443 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1444 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1445 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1446 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1447 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1448 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1449 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1450 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 1451 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 1452 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1453 | #endif |
| 1454 | #else |
| 1455 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1456 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1457 | #endif |
| 1458 | |
| 1459 | #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB) |
| 1460 | #if OPTION_DDR2 |
| 1461 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1462 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1463 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1464 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1465 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1466 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1467 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 |
| 1468 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 |
| 1469 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1470 | #else |
| 1471 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1472 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1473 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1474 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1475 | #else |
| 1476 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef |
| 1477 | #endif |
| 1478 | #endif |
| 1479 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1480 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 |
| 1481 | #else |
| 1482 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1483 | #endif |
| 1484 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1485 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1486 | #else |
| 1487 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1488 | #endif |
| 1489 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1490 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw |
| 1491 | #else |
| 1492 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1493 | #endif |
| 1494 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1495 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1496 | #else |
| 1497 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1498 | #endif |
| 1499 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1500 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency |
| 1501 | #else |
| 1502 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1503 | #endif |
| 1504 | MEM_TECH_FEAT_BLOCK omi1867 = { |
| 1505 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1506 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1507 | TECH_TRAIN_SW_WL_DDR2, |
| 1508 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1509 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1510 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1511 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1512 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1513 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1514 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1515 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1516 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1517 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1518 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1519 | NULL |
| 1520 | }; |
| 1521 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2PH = { |
| 1522 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1523 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1524 | TECH_TRAIN_SW_WL_DDR2, |
| 1525 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1526 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1527 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1528 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1529 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1530 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1531 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1532 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1533 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1534 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1535 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1536 | NULL |
| 1537 | }; |
| 1538 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Rb = { |
| 1539 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1540 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1541 | TECH_TRAIN_SW_WL_DDR2, |
| 1542 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1543 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1544 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1545 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1546 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1547 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1548 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1549 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1550 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1551 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1552 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1553 | NULL |
| 1554 | }; |
| 1555 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Ni = { |
| 1556 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1557 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1558 | TECH_TRAIN_SW_WL_DDR2, |
| 1559 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1560 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1561 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1562 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1563 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1564 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1565 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1566 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1567 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1568 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1569 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1570 | NULL |
| 1571 | }; |
| 1572 | extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; |
| 1573 | #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb |
| 1574 | extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; |
| 1575 | #if (OPTION_MEMCTLR_DA) |
| 1576 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA |
| 1577 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &omi1867 }, |
| 1578 | #else |
| 1579 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1580 | #endif |
| 1581 | #if (OPTION_MEMCTLR_PH) |
| 1582 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh |
| 1583 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH }, |
| 1584 | #else |
| 1585 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1586 | #endif |
| 1587 | #if (OPTION_MEMCTLR_RB) |
| 1588 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb |
| 1589 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb }, |
| 1590 | #else |
| 1591 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1592 | #endif |
| 1593 | |
| 1594 | #if (OPTION_MEMCTLR_Ni) |
| 1595 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi |
| 1596 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni }, |
| 1597 | #else |
| 1598 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1599 | #endif |
| 1600 | #else |
| 1601 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1602 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1603 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1604 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1605 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1606 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1607 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1608 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1609 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1610 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1611 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1612 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1613 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 1614 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1615 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1616 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1617 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1618 | #endif |
| 1619 | #if OPTION_DDR3 |
| 1620 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1621 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 1622 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1623 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 1624 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 1625 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 1626 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 1627 | #else |
| 1628 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1629 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1630 | #endif |
| 1631 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 1632 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1633 | #else |
| 1634 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1635 | #endif |
| 1636 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1637 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 1638 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 1639 | #endif |
| 1640 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1641 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 1642 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 1643 | #endif |
| 1644 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1645 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 1646 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 1647 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1648 | #else |
| 1649 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1650 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1651 | #else |
| 1652 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1653 | #endif |
| 1654 | #endif |
| 1655 | #else |
| 1656 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1657 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1658 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1659 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 1660 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1661 | #else |
| 1662 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1663 | #endif |
| 1664 | #endif |
| 1665 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1666 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 1667 | #else |
| 1668 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1669 | #endif |
| 1670 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1671 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 1672 | #else |
| 1673 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1674 | #endif |
| 1675 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1676 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1677 | #else |
| 1678 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1679 | #endif |
| 1680 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1681 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1682 | #else |
| 1683 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1684 | #endif |
| 1685 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1686 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 1687 | #else |
| 1688 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 1689 | #endif |
| 1690 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3DA = { |
| 1691 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1692 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1693 | TECH_TRAIN_SW_WL_DDR3, |
| 1694 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1695 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1696 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1697 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1698 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1699 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1700 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1701 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1702 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1703 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1704 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1705 | NULL |
| 1706 | }; |
| 1707 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ph = { |
| 1708 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1709 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1710 | TECH_TRAIN_SW_WL_DDR3, |
| 1711 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1712 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1713 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1714 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1715 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1716 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1717 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1718 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1719 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1720 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1721 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1722 | NULL |
| 1723 | }; |
| 1724 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Rb = { |
| 1725 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1726 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1727 | TECH_TRAIN_SW_WL_DDR3, |
| 1728 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1729 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1730 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1731 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1732 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1733 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1734 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1735 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1736 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1737 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1738 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1739 | NULL |
| 1740 | }; |
| 1741 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Ni = { |
| 1742 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1743 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1744 | TECH_TRAIN_SW_WL_DDR3, |
| 1745 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1746 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1747 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1748 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1749 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1750 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1751 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1752 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1753 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1754 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1755 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1756 | |
| 1757 | }; |
| 1758 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 1759 | #if (OPTION_MEMCTLR_DA) |
| 1760 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA; |
| 1761 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA }, |
| 1762 | #else |
| 1763 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1764 | #endif |
| 1765 | #if (OPTION_MEMCTLR_PH) |
| 1766 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh; |
| 1767 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph }, |
| 1768 | #else |
| 1769 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1770 | #endif |
| 1771 | #if (OPTION_MEMCTLR_RB) |
| 1772 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb; |
| 1773 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb }, |
| 1774 | #else |
| 1775 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1776 | #endif |
| 1777 | #if (OPTION_MEMCTLR_Ni) |
| 1778 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi; |
| 1779 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni }, |
| 1780 | #else |
| 1781 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1782 | #endif |
| 1783 | #else |
| 1784 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1785 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 1786 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 1787 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1788 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1789 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1790 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1791 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1792 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1793 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1794 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1795 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1796 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1797 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 1798 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 1799 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1800 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1801 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1802 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1803 | #endif |
| 1804 | #else |
| 1805 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1806 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1807 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1808 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1809 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1810 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1811 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1812 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1813 | #endif |
| 1814 | |
| 1815 | #if OPTION_MEMCTLR_HY |
| 1816 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy; |
| 1817 | #if OPTION_DDR2 |
| 1818 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1819 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1820 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1821 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1822 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1823 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1824 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 |
| 1825 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 |
| 1826 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1827 | #else |
| 1828 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1829 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1830 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1831 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 1832 | #else |
| 1833 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTFeatDef |
| 1834 | #endif |
| 1835 | #endif |
| 1836 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1837 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 |
| 1838 | #else |
| 1839 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1840 | #endif |
| 1841 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1842 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1843 | #else |
| 1844 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1845 | #endif |
| 1846 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1847 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw |
| 1848 | #else |
| 1849 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1850 | #endif |
| 1851 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1852 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1853 | #else |
| 1854 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1855 | #endif |
| 1856 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1857 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency |
| 1858 | #else |
| 1859 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1860 | #endif |
| 1861 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2Hy = { |
| 1862 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1863 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 1864 | TECH_TRAIN_SW_WL_DDR2, |
| 1865 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 1866 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 1867 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 1868 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 1869 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 1870 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1871 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 1872 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 1873 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 1874 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 1875 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 1876 | NULL |
| 1877 | }; |
| 1878 | extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; |
| 1879 | #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb |
| 1880 | extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; |
| 1881 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy }, |
| 1882 | #else |
| 1883 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 1884 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 1885 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 1886 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 1887 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 1888 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1889 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 1890 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1891 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 1892 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1893 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 1894 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 1895 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 1896 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 1897 | #endif |
| 1898 | #if OPTION_DDR3 |
| 1899 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1900 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 1901 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1902 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 1903 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 1904 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 1905 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 1906 | #else |
| 1907 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1908 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1909 | #endif |
| 1910 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 1911 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1912 | #else |
| 1913 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1914 | #endif |
| 1915 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 1916 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 1917 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 1918 | #endif |
| 1919 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1920 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 1921 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 1922 | #endif |
| 1923 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1924 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 1925 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 1926 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1927 | #else |
| 1928 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1929 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1930 | #else |
| 1931 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1932 | #endif |
| 1933 | #endif |
| 1934 | #else |
| 1935 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1936 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1937 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1938 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 1939 | #else |
| 1940 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 1941 | #endif |
| 1942 | #endif |
| 1943 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1944 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 1945 | #else |
| 1946 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1947 | #endif |
| 1948 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 1949 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 1950 | #else |
| 1951 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1952 | #endif |
| 1953 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1954 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1955 | #else |
| 1956 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1957 | #endif |
| 1958 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 1959 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 1960 | #else |
| 1961 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 1962 | #endif |
| 1963 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 1964 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 1965 | #else |
| 1966 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 1967 | #endif |
| 1968 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3Hy = { |
| 1969 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 1970 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 1971 | TECH_TRAIN_SW_WL_DDR3, |
| 1972 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 1973 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 1974 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 1975 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 1976 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 1977 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1978 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 1979 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 1980 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 1981 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 1982 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 1983 | NULL |
| 1984 | }; |
| 1985 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 1986 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy }, |
| 1987 | #else |
| 1988 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 1989 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 1990 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 1991 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 1992 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 1993 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 1994 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 1995 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1996 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 1997 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1998 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 1999 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2000 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2001 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2002 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2003 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2004 | #endif |
| 2005 | #else |
| 2006 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2007 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2008 | #endif |
| 2009 | |
| 2010 | #if OPTION_MEMCTLR_C32 |
| 2011 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32; |
| 2012 | #if OPTION_DDR2 |
| 2013 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2014 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2015 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2016 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2017 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2018 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2019 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTDqsTrainRcvrEnHwPass1 |
| 2020 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTDqsTrainRcvrEnHwPass2 |
| 2021 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2 MemTTrainDQSEdgeDetect |
| 2022 | #else |
| 2023 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2024 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2025 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2026 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2027 | #else |
| 2028 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2029 | #endif |
| 2030 | #endif |
| 2031 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2032 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTTrainRcvrEnSwPass1 |
| 2033 | #else |
| 2034 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2035 | #endif |
| 2036 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2037 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2038 | #else |
| 2039 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2040 | #endif |
| 2041 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2042 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTTrainDQSEdgeDetectSw |
| 2043 | #else |
| 2044 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2045 | #endif |
| 2046 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2047 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2048 | #else |
| 2049 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2050 | #endif |
| 2051 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2052 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTTrainMaxLatency |
| 2053 | #else |
| 2054 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 2055 | #endif |
| 2056 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR2C32 = { |
| 2057 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2058 | TECH_TRAIN_ENTER_HW_TRN_DDR2, |
| 2059 | TECH_TRAIN_SW_WL_DDR2, |
| 2060 | TECH_TRAIN_HW_WL_P1_DDR2, |
| 2061 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2, |
| 2062 | TECH_TRAIN_HW_WL_P2_DDR2, |
| 2063 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2, |
| 2064 | TECH_TRAIN_EXIT_HW_TRN_DDR2, |
| 2065 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 2066 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2, |
| 2067 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2, |
| 2068 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2, |
| 2069 | TECH_TRAIN_MAX_RD_LAT_DDR2, |
| 2070 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2, |
| 2071 | NULL |
| 2072 | }; |
| 2073 | extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb; |
| 2074 | #define NB_TRAIN_FLOW_DDR2 MemNDQSTiming2Nb |
| 2075 | extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb; |
| 2076 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 }, |
| 2077 | #else |
| 2078 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2079 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2080 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2081 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2082 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2083 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2084 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2085 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2086 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2087 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2088 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2089 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 2090 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2091 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2092 | #endif |
| 2093 | #if OPTION_DDR3 |
| 2094 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2095 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 2096 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2097 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 2098 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 2099 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 2100 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 2101 | #else |
| 2102 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2103 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2104 | #endif |
| 2105 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 2106 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2107 | #else |
| 2108 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2109 | #endif |
| 2110 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2111 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2112 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2113 | #endif |
| 2114 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2115 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2116 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2117 | #endif |
| 2118 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2119 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 2120 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2121 | #else |
| 2122 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2123 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2124 | #else |
| 2125 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2126 | #endif |
| 2127 | #endif |
| 2128 | #else |
| 2129 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2130 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2131 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2132 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2133 | #else |
| 2134 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2135 | #endif |
| 2136 | #endif |
| 2137 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2138 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 2139 | #else |
| 2140 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2141 | #endif |
| 2142 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2143 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 2144 | #else |
| 2145 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2146 | #endif |
| 2147 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2148 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2149 | #else |
| 2150 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2151 | #endif |
| 2152 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2153 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2154 | #else |
| 2155 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2156 | #endif |
| 2157 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2158 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 2159 | #else |
| 2160 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2161 | #endif |
| 2162 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3C32 = { |
| 2163 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2164 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 2165 | TECH_TRAIN_SW_WL_DDR3, |
| 2166 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 2167 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 2168 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 2169 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 2170 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 2171 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2172 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2173 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 2174 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 2175 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 2176 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 2177 | NULL |
| 2178 | }; |
| 2179 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 2180 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 }, |
| 2181 | #else |
| 2182 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2183 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2184 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2185 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 2186 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2187 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2188 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2189 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2190 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2191 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2192 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2193 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2194 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2195 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2196 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2197 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2198 | #endif |
| 2199 | #else |
| 2200 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2201 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2202 | #endif |
| 2203 | |
| 2204 | |
| 2205 | #if OPTION_MEMCTLR_LN |
| 2206 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2207 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2208 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2209 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2210 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2211 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2212 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2213 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2214 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2215 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2216 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2217 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 2218 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2219 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2220 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceLN; |
| 2221 | #if OPTION_DDR3 |
| 2222 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2223 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2224 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2225 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 |
| 2226 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 2227 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 2228 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 2229 | #else |
| 2230 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2231 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2232 | #endif |
| 2233 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2234 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2235 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2236 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2237 | #endif |
| 2238 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 2239 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2240 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2241 | #endif |
| 2242 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 2243 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 2244 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 2245 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 |
| 2246 | #else |
| 2247 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2248 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2249 | #else |
| 2250 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2251 | #endif |
| 2252 | #endif |
| 2253 | #else |
| 2254 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2255 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2256 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2257 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2258 | #else |
| 2259 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2260 | #endif |
| 2261 | #endif |
| 2262 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2263 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 2264 | #else |
| 2265 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2266 | #endif |
| 2267 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2268 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 2269 | #else |
| 2270 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2271 | #endif |
| 2272 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2273 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2274 | #else |
| 2275 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2276 | #endif |
| 2277 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2278 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2279 | #else |
| 2280 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2281 | #endif |
| 2282 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2283 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 2284 | #else |
| 2285 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2286 | #endif |
| 2287 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3LN = { |
| 2288 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2289 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 2290 | TECH_TRAIN_SW_WL_DDR3, |
| 2291 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 2292 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 2293 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 2294 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 2295 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 2296 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2297 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2298 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 2299 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 2300 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 2301 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 2302 | NULL |
| 2303 | }; |
| 2304 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 2305 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceLN, &memTechTrainingFeatSequenceDDR3LN }, |
| 2306 | #else |
| 2307 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2308 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2309 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2310 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 2311 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2312 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2313 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2314 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2315 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2316 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2317 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2318 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2319 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2320 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2321 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2322 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2323 | #endif |
| 2324 | #else |
| 2325 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2326 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2327 | #endif |
| 2328 | |
| 2329 | |
| 2330 | #if OPTION_MEMCTLR_OR |
| 2331 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr; |
| 2332 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2333 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2334 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2335 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2336 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2337 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2338 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2339 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2340 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2341 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2342 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2343 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 2344 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2345 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2346 | #if OPTION_DDR3 |
| 2347 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2348 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 2349 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2350 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 2351 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 2352 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 2353 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 2354 | #else |
| 2355 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2356 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2357 | #endif |
| 2358 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 2359 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2360 | #else |
| 2361 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2362 | #endif |
| 2363 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2364 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2365 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2366 | #endif |
| 2367 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 2368 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2369 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2370 | #endif |
| 2371 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 2372 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 2373 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 2374 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 |
| 2375 | #else |
| 2376 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2377 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2378 | #else |
| 2379 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2380 | #endif |
| 2381 | #endif |
| 2382 | #else |
| 2383 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2384 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2385 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2386 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2387 | #else |
| 2388 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2389 | #endif |
| 2390 | #endif |
| 2391 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2392 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2393 | #else |
| 2394 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2395 | #endif |
| 2396 | #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 |
| 2397 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2398 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2399 | #else |
| 2400 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2401 | #endif |
| 2402 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2403 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2404 | #else |
| 2405 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2406 | #endif |
| 2407 | #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 |
| 2408 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2409 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2410 | #else |
| 2411 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2412 | #endif |
| 2413 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2414 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 2415 | #else |
| 2416 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2417 | #endif |
| 2418 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3OR = { |
| 2419 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2420 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 2421 | TECH_TRAIN_SW_WL_DDR3, |
| 2422 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 2423 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 2424 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 2425 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 2426 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 2427 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2428 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2429 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 2430 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 2431 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 2432 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 2433 | NULL |
| 2434 | }; |
| 2435 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 2436 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR }, |
| 2437 | #else |
| 2438 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2439 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2440 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2441 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 2442 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2443 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2444 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2445 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2446 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2447 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2448 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2449 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2450 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2451 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2452 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2453 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2454 | #endif |
| 2455 | #else |
| 2456 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2457 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2458 | #endif |
| 2459 | |
| 2460 | |
| 2461 | #if OPTION_MEMCTLR_ON |
| 2462 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON; |
| 2463 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2464 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2465 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2466 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2467 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2468 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2469 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2470 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2471 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2472 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2473 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2474 | #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef |
| 2475 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2476 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2477 | #if OPTION_DDR3 |
| 2478 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2479 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2480 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2481 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTrainingClient3 |
| 2482 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 2483 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 2484 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 2485 | #else |
| 2486 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2487 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2488 | #endif |
| 2489 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2490 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2491 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 2492 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 2493 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 2494 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 2495 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTRdPosWithRxEnDlySeeds3 |
| 2496 | #else |
| 2497 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2498 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2499 | #else |
| 2500 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2501 | #endif |
| 2502 | #endif |
| 2503 | #else |
| 2504 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2505 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2506 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2507 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2508 | #else |
| 2509 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2510 | #endif |
| 2511 | #endif |
| 2512 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2513 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainRcvrEnSwPass1 |
| 2514 | #else |
| 2515 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2516 | #endif |
| 2517 | #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 |
| 2518 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2519 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTTrainOptRcvrEnSwPass1 |
| 2520 | #else |
| 2521 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2522 | #endif |
| 2523 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2524 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2525 | #else |
| 2526 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2527 | #endif |
| 2528 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2529 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2530 | #else |
| 2531 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2532 | #endif |
| 2533 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2534 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 2535 | #else |
| 2536 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2537 | #endif |
| 2538 | MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3ON = { |
| 2539 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2540 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 2541 | TECH_TRAIN_SW_WL_DDR3, |
| 2542 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 2543 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 2544 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 2545 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 2546 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 2547 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2548 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2549 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 2550 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 2551 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 2552 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 2553 | NULL |
| 2554 | }; |
| 2555 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 2556 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON }, |
| 2557 | #else |
| 2558 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2559 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2560 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2561 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 2562 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2563 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2564 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2565 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2566 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2567 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2568 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2569 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2570 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2571 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2572 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2573 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2574 | #endif |
| 2575 | #else |
| 2576 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2577 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2578 | #endif |
| 2579 | |
| 2580 | #if OPTION_MEMCTLR_TN |
| 2581 | extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceTN; |
| 2582 | #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef |
| 2583 | #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef |
| 2584 | #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef |
| 2585 | #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef |
| 2586 | #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef |
| 2587 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2588 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef |
| 2589 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2590 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef |
| 2591 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2592 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef |
| 2593 | #define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2594 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2595 | #if OPTION_DDR3 |
| 2596 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2597 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTPreparePhyAssistedTraining |
| 2598 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2599 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTExitPhyAssistedTraining |
| 2600 | #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE) |
| 2601 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTWriteLevelizationHw3Pass1 |
| 2602 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTWriteLevelizationHw3Pass2 |
| 2603 | #else |
| 2604 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2605 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2606 | #endif |
| 2607 | #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE) |
| 2608 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2609 | #else |
| 2610 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2611 | #endif |
| 2612 | #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE) |
| 2613 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2614 | #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 |
| 2615 | #endif |
| 2616 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTDqsTrainRcvrEnHwPass1 |
| 2617 | #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2618 | #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 |
| 2619 | #endif |
| 2620 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTDqsTrainRcvrEnHwPass2 |
| 2621 | #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE) |
| 2622 | #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 |
| 2623 | extern MEM_TECH_FEAT MemNRdPosTrnTN; |
| 2624 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemNRdPosTrnTN |
| 2625 | #else |
| 2626 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2627 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2628 | #else |
| 2629 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2630 | #endif |
| 2631 | #endif |
| 2632 | #else |
| 2633 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2634 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2635 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2636 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTTrainDQSEdgeDetect |
| 2637 | #else |
| 2638 | #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef |
| 2639 | #endif |
| 2640 | #endif |
| 2641 | #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2642 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2643 | #else |
| 2644 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2645 | #endif |
| 2646 | #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 |
| 2647 | #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE) |
| 2648 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2649 | #else |
| 2650 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2651 | #endif |
| 2652 | #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2653 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2654 | #else |
| 2655 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2656 | #endif |
| 2657 | #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 |
| 2658 | #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE) |
| 2659 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTTrainDQSEdgeDetectSw |
| 2660 | #else |
| 2661 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2662 | #endif |
| 2663 | #if (OPTION_MAX_RD_LAT_TRAINING == TRUE) |
| 2664 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTTrainMaxLatency |
| 2665 | #else |
| 2666 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2667 | #endif |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 2668 | CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3TN = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 2669 | MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, |
| 2670 | TECH_TRAIN_ENTER_HW_TRN_DDR3, |
| 2671 | TECH_TRAIN_SW_WL_DDR3, |
| 2672 | TECH_TRAIN_HW_WL_P1_DDR3, |
| 2673 | TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3, |
| 2674 | TECH_TRAIN_HW_WL_P2_DDR3, |
| 2675 | TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3, |
| 2676 | TECH_TRAIN_EXIT_HW_TRN_DDR3, |
| 2677 | TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2678 | TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3, |
| 2679 | TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3, |
| 2680 | TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3, |
| 2681 | TECH_TRAIN_MAX_RD_LAT_DDR3, |
| 2682 | TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3, |
| 2683 | |
| 2684 | }; |
| 2685 | #define NB_TRAIN_FLOW_DDR3 MemNDQSTiming3Nb |
| 2686 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceTN, &memTechTrainingFeatSequenceDDR3TN }, |
| 2687 | #else |
| 2688 | #undef TECH_TRAIN_ENTER_HW_TRN_DDR3 |
| 2689 | #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef |
| 2690 | #undef TECH_TRAIN_EXIT_HW_TRN_DDR3 |
| 2691 | #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef |
| 2692 | #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef |
| 2693 | #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef |
| 2694 | #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef |
| 2695 | #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2696 | #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef |
| 2697 | #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2698 | #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef |
| 2699 | #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2700 | #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef |
| 2701 | #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef |
| 2702 | #define NB_TRAIN_FLOW_DDR3 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue |
| 2703 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2704 | #endif |
| 2705 | #else |
| 2706 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2707 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 }, |
| 2708 | #endif |
| 2709 | |
| 2710 | |
| 2711 | |
| 2712 | #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 } |
| 2713 | MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { |
| 2714 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR |
| 2715 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA |
| 2716 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY |
| 2717 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_LN |
| 2718 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 |
| 2719 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON |
| 2720 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni |
| 2721 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR |
| 2722 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH |
| 2723 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB |
| 2724 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN |
| 2725 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_END |
| 2726 | }; |
| 2727 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 2728 | CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 2729 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR |
| 2730 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA |
| 2731 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY |
| 2732 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_LN |
| 2733 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 |
| 2734 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON |
| 2735 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni |
| 2736 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR |
| 2737 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH |
| 2738 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB |
| 2739 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN |
| 2740 | MEM_TECH_ENABLE_TRAINING_SEQUENCE_END |
| 2741 | }; |
| 2742 | /*--------------------------------------------------------------------------------------------------- |
| 2743 | * NB TRAINING FLOW CONTROL |
| 2744 | * |
| 2745 | * |
| 2746 | *--------------------------------------------------------------------------------------------------- |
| 2747 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 2748 | OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 2749 | NB_TRAIN_FLOW_DDR2, |
| 2750 | NB_TRAIN_FLOW_DDR3, |
| 2751 | }; |
| 2752 | /*--------------------------------------------------------------------------------------------------- |
| 2753 | * TECHNOLOGY BLOCK |
| 2754 | * |
| 2755 | * |
| 2756 | *--------------------------------------------------------------------------------------------------- |
| 2757 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 2758 | MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 2759 | MEM_TECH_CONSTRUCTOR_DDR2 |
| 2760 | MEM_TECH_CONSTRUCTOR_DDR3 |
| 2761 | NULL |
| 2762 | }; |
| 2763 | /*--------------------------------------------------------------------------------------------------- |
| 2764 | * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION |
| 2765 | * |
| 2766 | * |
| 2767 | *--------------------------------------------------------------------------------------------------- |
| 2768 | */ |
| 2769 | #if OPTION_MEMCTLR_HY |
| 2770 | #if OPTION_UDIMMS |
| 2771 | #if OPTION_DDR2 |
| 2772 | #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, |
| 2773 | #else |
| 2774 | #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, |
| 2775 | #endif |
| 2776 | #if OPTION_DDR3 |
| 2777 | #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUHy3, |
| 2778 | #else |
| 2779 | #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, |
| 2780 | #endif |
| 2781 | #else |
| 2782 | #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, |
| 2783 | #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, |
| 2784 | #endif |
| 2785 | #if OPTION_RDIMMS |
| 2786 | #if OPTION_DDR2 |
| 2787 | #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, |
| 2788 | #else |
| 2789 | #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, |
| 2790 | #endif |
| 2791 | #if OPTION_DDR3 |
| 2792 | #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsRHy3, |
| 2793 | #else |
| 2794 | #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, |
| 2795 | #endif |
| 2796 | #else |
| 2797 | #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, |
| 2798 | #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, |
| 2799 | #endif |
| 2800 | #if OPTION_SODIMMS |
| 2801 | #if OPTION_DDR2 |
| 2802 | #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, |
| 2803 | #else |
| 2804 | #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, |
| 2805 | #endif |
| 2806 | #if OPTION_DDR3 |
| 2807 | #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsSHy3, |
| 2808 | #else |
| 2809 | #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, |
| 2810 | #endif |
| 2811 | #else |
| 2812 | #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, |
| 2813 | #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, |
| 2814 | #endif |
| 2815 | #else |
| 2816 | #define PLAT_SP_HY_FF_SDIMM2 MemPConstructPsUDef, |
| 2817 | #define PLAT_SP_HY_FF_RDIMM2 MemPConstructPsUDef, |
| 2818 | #define PLAT_SP_HY_FF_UDIMM2 MemPConstructPsUDef, |
| 2819 | #define PLAT_SP_HY_FF_SDIMM3 MemPConstructPsUDef, |
| 2820 | #define PLAT_SP_HY_FF_RDIMM3 MemPConstructPsUDef, |
| 2821 | #define PLAT_SP_HY_FF_UDIMM3 MemPConstructPsUDef, |
| 2822 | #endif |
| 2823 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { |
| 2824 | PLAT_SP_HY_FF_UDIMM2 |
| 2825 | PLAT_SP_HY_FF_RDIMM2 |
| 2826 | PLAT_SP_HY_FF_SDIMM2 |
| 2827 | PLAT_SP_HY_FF_UDIMM3 |
| 2828 | PLAT_SP_HY_FF_RDIMM3 |
| 2829 | PLAT_SP_HY_FF_SDIMM3 |
| 2830 | }; |
| 2831 | |
| 2832 | #if OPTION_MEMCTLR_DR |
| 2833 | #if OPTION_UDIMMS |
| 2834 | #if OPTION_DDR2 |
| 2835 | extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2; |
| 2836 | #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDr2, |
| 2837 | #else |
| 2838 | #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, |
| 2839 | #endif |
| 2840 | #if OPTION_DDR3 |
| 2841 | #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDr3, |
| 2842 | #else |
| 2843 | #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, |
| 2844 | #endif |
| 2845 | #else |
| 2846 | #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, |
| 2847 | #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, |
| 2848 | #endif |
| 2849 | #if OPTION_RDIMMS |
| 2850 | #if OPTION_DDR2 |
| 2851 | extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2; |
| 2852 | #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsRDr2, |
| 2853 | #else |
| 2854 | #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, |
| 2855 | #endif |
| 2856 | #if OPTION_DDR3 |
| 2857 | #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsRDr3, |
| 2858 | #else |
| 2859 | #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, |
| 2860 | #endif |
| 2861 | #else |
| 2862 | #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, |
| 2863 | #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, |
| 2864 | #endif |
| 2865 | #if OPTION_SODIMMS |
| 2866 | #if OPTION_DDR2 |
| 2867 | #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, |
| 2868 | #else |
| 2869 | #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, |
| 2870 | #endif |
| 2871 | #if OPTION_DDR3 |
| 2872 | #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsSDr3, |
| 2873 | #else |
| 2874 | #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, |
| 2875 | #endif |
| 2876 | #else |
| 2877 | #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, |
| 2878 | #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, |
| 2879 | #endif |
| 2880 | #else |
| 2881 | #define PLAT_SP_DR_FF_SDIMM2 MemPConstructPsUDef, |
| 2882 | #define PLAT_SP_DR_FF_RDIMM2 MemPConstructPsUDef, |
| 2883 | #define PLAT_SP_DR_FF_UDIMM2 MemPConstructPsUDef, |
| 2884 | #define PLAT_SP_DR_FF_SDIMM3 MemPConstructPsUDef, |
| 2885 | #define PLAT_SP_DR_FF_RDIMM3 MemPConstructPsUDef, |
| 2886 | #define PLAT_SP_DR_FF_UDIMM3 MemPConstructPsUDef, |
| 2887 | #endif |
| 2888 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = { |
| 2889 | PLAT_SP_DR_FF_UDIMM2 |
| 2890 | PLAT_SP_DR_FF_RDIMM2 |
| 2891 | PLAT_SP_DR_FF_SDIMM2 |
| 2892 | PLAT_SP_DR_FF_UDIMM3 |
| 2893 | PLAT_SP_DR_FF_RDIMM3 |
| 2894 | PLAT_SP_DR_FF_SDIMM3 |
| 2895 | }; |
| 2896 | |
| 2897 | #if (OPTION_MEMCTLR_DA == TRUE) |
| 2898 | #if OPTION_UDIMMS |
| 2899 | #if OPTION_DDR2 |
| 2900 | #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, |
| 2901 | #else |
| 2902 | #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, |
| 2903 | #endif |
| 2904 | #if OPTION_DDR3 |
| 2905 | #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDA3, |
| 2906 | #else |
| 2907 | #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, |
| 2908 | #endif |
| 2909 | #else |
| 2910 | #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, |
| 2911 | #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, |
| 2912 | #endif |
| 2913 | #if OPTION_RDIMMS |
| 2914 | #if OPTION_DDR2 |
| 2915 | #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, |
| 2916 | #else |
| 2917 | #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, |
| 2918 | #endif |
| 2919 | #if OPTION_DDR3 |
| 2920 | #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, |
| 2921 | #else |
| 2922 | #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, |
| 2923 | #endif |
| 2924 | #else |
| 2925 | #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, |
| 2926 | #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, |
| 2927 | #endif |
| 2928 | #if OPTION_SODIMMS |
| 2929 | #if OPTION_DDR2 |
| 2930 | #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsSDA2, |
| 2931 | #else |
| 2932 | #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, |
| 2933 | #endif |
| 2934 | #if OPTION_DDR3 |
| 2935 | #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsSDA3, |
| 2936 | #else |
| 2937 | #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, |
| 2938 | #endif |
| 2939 | #else |
| 2940 | #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, |
| 2941 | #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, |
| 2942 | #endif |
| 2943 | #else |
| 2944 | #define PLAT_SP_DA_FF_SDIMM2 MemPConstructPsUDef, |
| 2945 | #define PLAT_SP_DA_FF_RDIMM2 MemPConstructPsUDef, |
| 2946 | #define PLAT_SP_DA_FF_UDIMM2 MemPConstructPsUDef, |
| 2947 | #define PLAT_SP_DA_FF_SDIMM3 MemPConstructPsUDef, |
| 2948 | #define PLAT_SP_DA_FF_RDIMM3 MemPConstructPsUDef, |
| 2949 | #define PLAT_SP_DA_FF_UDIMM3 MemPConstructPsUDef, |
| 2950 | #endif |
| 2951 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { |
| 2952 | PLAT_SP_DA_FF_UDIMM2 |
| 2953 | PLAT_SP_DA_FF_RDIMM2 |
| 2954 | PLAT_SP_DA_FF_SDIMM2 |
| 2955 | PLAT_SP_DA_FF_UDIMM3 |
| 2956 | PLAT_SP_DA_FF_RDIMM3 |
| 2957 | PLAT_SP_DA_FF_SDIMM3 |
| 2958 | }; |
| 2959 | |
| 2960 | #if (OPTION_MEMCTLR_Ni == TRUE) |
| 2961 | #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, |
| 2962 | #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, |
| 2963 | #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, |
| 2964 | #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsSNi3, |
| 2965 | #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, |
| 2966 | #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUNi3, |
| 2967 | #else |
| 2968 | #define PLAT_SP_NI_FF_SDIMM2 MemPConstructPsUDef, |
| 2969 | #define PLAT_SP_NI_FF_RDIMM2 MemPConstructPsUDef, |
| 2970 | #define PLAT_SP_NI_FF_UDIMM2 MemPConstructPsUDef, |
| 2971 | #define PLAT_SP_NI_FF_SDIMM3 MemPConstructPsUDef, |
| 2972 | #define PLAT_SP_NI_FF_RDIMM3 MemPConstructPsUDef, |
| 2973 | #define PLAT_SP_NI_FF_UDIMM3 MemPConstructPsUDef, |
| 2974 | #endif |
| 2975 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { |
| 2976 | PLAT_SP_NI_FF_UDIMM2 |
| 2977 | PLAT_SP_NI_FF_RDIMM2 |
| 2978 | PLAT_SP_NI_FF_SDIMM2 |
| 2979 | PLAT_SP_NI_FF_UDIMM3 |
| 2980 | PLAT_SP_NI_FF_RDIMM3 |
| 2981 | PLAT_SP_NI_FF_SDIMM3 |
| 2982 | }; |
| 2983 | |
| 2984 | #if (OPTION_MEMCTLR_PH == TRUE) |
| 2985 | #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, |
| 2986 | #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, |
| 2987 | #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, |
| 2988 | #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsSPh3, |
| 2989 | #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, |
| 2990 | #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUPh3, |
| 2991 | #else |
| 2992 | #define PLAT_SP_PH_FF_SDIMM2 MemPConstructPsUDef, |
| 2993 | #define PLAT_SP_PH_FF_RDIMM2 MemPConstructPsUDef, |
| 2994 | #define PLAT_SP_PH_FF_UDIMM2 MemPConstructPsUDef, |
| 2995 | #define PLAT_SP_PH_FF_SDIMM3 MemPConstructPsUDef, |
| 2996 | #define PLAT_SP_PH_FF_RDIMM3 MemPConstructPsUDef, |
| 2997 | #define PLAT_SP_PH_FF_UDIMM3 MemPConstructPsUDef, |
| 2998 | #endif |
| 2999 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { |
| 3000 | PLAT_SP_PH_FF_UDIMM2 |
| 3001 | PLAT_SP_PH_FF_RDIMM2 |
| 3002 | PLAT_SP_PH_FF_SDIMM2 |
| 3003 | PLAT_SP_PH_FF_UDIMM3 |
| 3004 | PLAT_SP_PH_FF_RDIMM3 |
| 3005 | PLAT_SP_PH_FF_SDIMM3 |
| 3006 | }; |
| 3007 | |
| 3008 | #if (OPTION_MEMCTLR_RB == TRUE) |
| 3009 | #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, |
| 3010 | #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, |
| 3011 | #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, |
| 3012 | #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsSRb3, |
| 3013 | #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, |
| 3014 | #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsURb3, |
| 3015 | #else |
| 3016 | #define PLAT_SP_RB_FF_SDIMM2 MemPConstructPsUDef, |
| 3017 | #define PLAT_SP_RB_FF_RDIMM2 MemPConstructPsUDef, |
| 3018 | #define PLAT_SP_RB_FF_UDIMM2 MemPConstructPsUDef, |
| 3019 | #define PLAT_SP_RB_FF_SDIMM3 MemPConstructPsUDef, |
| 3020 | #define PLAT_SP_RB_FF_RDIMM3 MemPConstructPsUDef, |
| 3021 | #define PLAT_SP_RB_FF_UDIMM3 MemPConstructPsUDef, |
| 3022 | #endif |
| 3023 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { |
| 3024 | PLAT_SP_RB_FF_UDIMM2 |
| 3025 | PLAT_SP_RB_FF_RDIMM2 |
| 3026 | PLAT_SP_RB_FF_SDIMM2 |
| 3027 | PLAT_SP_RB_FF_UDIMM3 |
| 3028 | PLAT_SP_RB_FF_RDIMM3 |
| 3029 | PLAT_SP_RB_FF_SDIMM3 |
| 3030 | }; |
| 3031 | |
| 3032 | #if OPTION_MEMCTLR_LN |
| 3033 | #if OPTION_UDIMMS |
| 3034 | #if OPTION_DDR3 |
| 3035 | #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsULN3, |
| 3036 | #else |
| 3037 | #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, |
| 3038 | #endif |
| 3039 | #else |
| 3040 | #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, |
| 3041 | #endif |
| 3042 | #if OPTION_SODIMMS |
| 3043 | #if OPTION_DDR3 |
| 3044 | #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsSLN3, |
| 3045 | #else |
| 3046 | #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, |
| 3047 | #endif |
| 3048 | #else |
| 3049 | #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, |
| 3050 | #endif |
| 3051 | #else |
| 3052 | #define PLAT_SP_LN_FF_SDIMM3 MemPConstructPsUDef, |
| 3053 | #define PLAT_SP_LN_FF_UDIMM3 MemPConstructPsUDef, |
| 3054 | #endif |
| 3055 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[] = { |
| 3056 | PLAT_SP_LN_FF_SDIMM3 |
| 3057 | PLAT_SP_LN_FF_UDIMM3 |
| 3058 | NULL |
| 3059 | }; |
| 3060 | |
| 3061 | #if OPTION_MEMCTLR_C32 |
| 3062 | #if OPTION_UDIMMS |
| 3063 | #if OPTION_DDR2 |
| 3064 | #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, |
| 3065 | #else |
| 3066 | #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, |
| 3067 | #endif |
| 3068 | #if OPTION_DDR3 |
| 3069 | #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUC32_3, |
| 3070 | #else |
| 3071 | #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, |
| 3072 | #endif |
| 3073 | #else |
| 3074 | #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, |
| 3075 | #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, |
| 3076 | #endif |
| 3077 | #if OPTION_RDIMMS |
| 3078 | #if OPTION_DDR2 |
| 3079 | #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, |
| 3080 | #else |
| 3081 | #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, |
| 3082 | #endif |
| 3083 | #if OPTION_DDR3 |
| 3084 | #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsRC32_3, |
| 3085 | #else |
| 3086 | #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, |
| 3087 | #endif |
| 3088 | #else |
| 3089 | #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, |
| 3090 | #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, |
| 3091 | #endif |
| 3092 | #if OPTION_SODIMMS |
| 3093 | #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, |
| 3094 | #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, |
| 3095 | #endif |
| 3096 | #else |
| 3097 | #define PLAT_SP_C32_FF_SDIMM2 MemPConstructPsUDef, |
| 3098 | #define PLAT_SP_C32_FF_RDIMM2 MemPConstructPsUDef, |
| 3099 | #define PLAT_SP_C32_FF_UDIMM2 MemPConstructPsUDef, |
| 3100 | #define PLAT_SP_C32_FF_SDIMM3 MemPConstructPsUDef, |
| 3101 | #define PLAT_SP_C32_FF_RDIMM3 MemPConstructPsUDef, |
| 3102 | #define PLAT_SP_C32_FF_UDIMM3 MemPConstructPsUDef, |
| 3103 | #endif |
| 3104 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { |
| 3105 | PLAT_SP_C32_FF_UDIMM2 |
| 3106 | PLAT_SP_C32_FF_RDIMM2 |
| 3107 | PLAT_SP_C32_FF_SDIMM2 |
| 3108 | PLAT_SP_C32_FF_UDIMM3 |
| 3109 | PLAT_SP_C32_FF_RDIMM3 |
| 3110 | PLAT_SP_C32_FF_SDIMM3 |
| 3111 | }; |
| 3112 | |
| 3113 | #if OPTION_MEMCTLR_ON |
| 3114 | #if OPTION_UDIMMS |
| 3115 | #if OPTION_DDR3 |
| 3116 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUON3, |
| 3117 | #else |
| 3118 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 3119 | #endif |
| 3120 | #else |
| 3121 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 3122 | #endif |
| 3123 | #if OPTION_SODIMMS |
| 3124 | #if OPTION_DDR3 |
| 3125 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsSON3, |
| 3126 | #else |
| 3127 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 3128 | #endif |
| 3129 | #else |
| 3130 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 3131 | #endif |
| 3132 | #else |
| 3133 | #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, |
| 3134 | #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, |
| 3135 | #endif |
| 3136 | MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { |
| 3137 | PLAT_SP_ON_FF_SDIMM3 |
| 3138 | PLAT_SP_ON_FF_UDIMM3 |
| 3139 | NULL |
| 3140 | }; |
| 3141 | |
| 3142 | /*--------------------------------------------------------------------------------------------------- |
| 3143 | * PLATFORM-SPECIFIC CONFIGURATION |
| 3144 | * |
| 3145 | * |
| 3146 | *--------------------------------------------------------------------------------------------------- |
| 3147 | */ |
| 3148 | |
| 3149 | #if OPTION_MEMCTLR_DR |
| 3150 | #if OPTION_UDIMMS |
| 3151 | #if OPTION_DDR2 |
| 3152 | #define PSC_DR_UDIMM_DDR2 //MemAGetPsCfgUDr2 |
| 3153 | #else |
| 3154 | #define PSC_DR_UDIMM_DDR2 |
| 3155 | #endif |
| 3156 | #if OPTION_DDR3 |
| 3157 | #define PSC_DR_UDIMM_DDR3 MemAGetPsCfgUDr3, |
| 3158 | #else |
| 3159 | #define PSC_DR_UDIMM_DDR3 |
| 3160 | #endif |
| 3161 | #endif |
| 3162 | #if OPTION_RDIMMS |
| 3163 | #if OPTION_DDR2 |
| 3164 | #define PSC_DR_RDIMM_DDR2 MemAGetPsCfgRDr2, |
| 3165 | #else |
| 3166 | #define PSC_DR_RDIMM_DDR2 |
| 3167 | #endif |
| 3168 | #if OPTION_DDR3 |
| 3169 | #define PSC_DR_RDIMM_DDR3 MemAGetPsCfgRDr3, |
| 3170 | #else |
| 3171 | #define PSC_DR_RDIMM_DDR3 |
| 3172 | #endif |
| 3173 | #endif |
| 3174 | #if OPTION_SODIMMS |
| 3175 | #if OPTION_DDR2 |
| 3176 | #define PSC_DR_SODIMM_DDR2 //MemAGetPsCfgSDr2 |
| 3177 | #else |
| 3178 | #define PSC_DR_SODIMM_DDR2 |
| 3179 | #endif |
| 3180 | #if OPTION_DDR3 |
| 3181 | #define PSC_DR_SODIMM_DDR3 //MemAGetPsCfgSDr3 |
| 3182 | #else |
| 3183 | #define PSC_DR_SODIMM_DDR3 |
| 3184 | #endif |
| 3185 | #endif |
| 3186 | #endif |
| 3187 | |
| 3188 | #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE) |
| 3189 | #if OPTION_MEMCTLR_Ni |
| 3190 | #define PSC_NI_UDIMM_DDR2 |
| 3191 | #define PSC_NI_UDIMM_DDR3 MemAGetPsCfgUNi3, |
| 3192 | #define PSC_NI_RDIMM_DDR2 |
| 3193 | #define PSC_NI_RDIMM_DDR3 |
| 3194 | #define PSC_NI_SODIMM_DDR2 |
| 3195 | #define PSC_NI_SODIMM_DDR3 MemAGetPsCfgSNi3, |
| 3196 | #endif |
| 3197 | #if OPTION_MEMCTLR_PH |
| 3198 | #define PSC_PH_UDIMM_DDR2 |
| 3199 | #define PSC_PH_UDIMM_DDR3 MemAGetPsCfgUPh3, |
| 3200 | #define PSC_PH_RDIMM_DDR2 |
| 3201 | #define PSC_PH_RDIMM_DDR3 |
| 3202 | #define PSC_PH_SODIMM_DDR2 |
| 3203 | #define PSC_PH_SODIMM_DDR3 MemAGetPsCfgSPh3, |
| 3204 | #endif |
| 3205 | #if OPTION_MEMCTLR_RB |
| 3206 | #define PSC_RB_UDIMM_DDR2 |
| 3207 | #define PSC_RB_UDIMM_DDR3 MemAGetPsCfgURb3, |
| 3208 | #define PSC_RB_RDIMM_DDR2 |
| 3209 | #define PSC_RB_RDIMM_DDR3 |
| 3210 | #define PSC_RB_SODIMM_DDR2 |
| 3211 | #define PSC_RB_SODIMM_DDR3 MemAGetPsCfgSRb3, |
| 3212 | #endif |
| 3213 | #if OPTION_MEMCTLR_DA |
| 3214 | #if OPTION_UDIMMS |
| 3215 | #if OPTION_DDR2 |
| 3216 | #define PSC_DA_UDIMM_DDR2 //MemAGetPsCfgUDr2 |
| 3217 | #else |
| 3218 | #define PSC_DA_UDIMM_DDR2 |
| 3219 | #endif |
| 3220 | #if OPTION_DDR3 |
| 3221 | #define PSC_DA_UDIMM_DDR3 MemAGetPsCfgUDA3, |
| 3222 | #else |
| 3223 | #define PSC_DA_UDIMM_DDR3 |
| 3224 | #endif |
| 3225 | #endif |
| 3226 | #if OPTION_RDIMMS |
| 3227 | #if OPTION_DDR2 |
| 3228 | #define PSC_DA_RDIMM_DDR2 |
| 3229 | #else |
| 3230 | #define PSC_DA_RDIMM_DDR2 |
| 3231 | #endif |
| 3232 | #if OPTION_DDR3 |
| 3233 | #define PSC_DA_RDIMM_DDR3 |
| 3234 | #else |
| 3235 | #define PSC_DA_RDIMM_DDR3 |
| 3236 | #endif |
| 3237 | #endif |
| 3238 | #if OPTION_SODIMMS |
| 3239 | #if OPTION_DDR2 |
| 3240 | #define PSC_DA_SODIMM_DDR2 MemAGetPsCfgSDA2, |
| 3241 | #else |
| 3242 | #define PSC_DA_SODIMM_DDR2 |
| 3243 | #endif |
| 3244 | #if OPTION_DDR3 |
| 3245 | #define PSC_DA_SODIMM_DDR3 MemAGetPsCfgSDA3, |
| 3246 | #else |
| 3247 | #define PSC_DA_SODIMM_DDR3 |
| 3248 | #endif |
| 3249 | #endif |
| 3250 | #endif |
| 3251 | #endif |
| 3252 | |
| 3253 | #if OPTION_MEMCTLR_HY |
| 3254 | #if OPTION_UDIMMS |
| 3255 | #if OPTION_DDR2 |
| 3256 | #define PSC_HY_UDIMM_DDR2 //MemAGetPsCfgUDr2, |
| 3257 | #else |
| 3258 | #define PSC_HY_UDIMM_DDR2 |
| 3259 | #endif |
| 3260 | #if OPTION_DDR3 |
| 3261 | #define PSC_HY_UDIMM_DDR3 MemAGetPsCfgUHy3, |
| 3262 | #else |
| 3263 | #define PSC_HY_UDIMM_DDR3 |
| 3264 | #endif |
| 3265 | #endif |
| 3266 | #if OPTION_RDIMMS |
| 3267 | #if OPTION_DDR2 |
| 3268 | #define PSC_HY_RDIMM_DDR2 |
| 3269 | #else |
| 3270 | #define PSC_HY_RDIMM_DDR2 |
| 3271 | #endif |
| 3272 | #if OPTION_DDR3 |
| 3273 | #define PSC_HY_RDIMM_DDR3 MemAGetPsCfgRHy3, |
| 3274 | #else |
| 3275 | #define PSC_HY_RDIMM_DDR3 |
| 3276 | #endif |
| 3277 | #endif |
| 3278 | #if OPTION_SODIMMS |
| 3279 | #if OPTION_DDR2 |
| 3280 | #define PSC_HY_SODIMM_DDR2 //MemAGetPsCfgSHy2, |
| 3281 | #else |
| 3282 | #define PSC_HY_SODIMM_DDR2 |
| 3283 | #endif |
| 3284 | #if OPTION_DDR3 |
| 3285 | #define PSC_HY_SODIMM_DDR3 //MemAGetPsCfgSHy3, |
| 3286 | #else |
| 3287 | #define PSC_HY_SODIMM_DDR3 |
| 3288 | #endif |
| 3289 | #endif |
| 3290 | #endif |
| 3291 | |
| 3292 | #if OPTION_MEMCTLR_C32 |
| 3293 | #if OPTION_UDIMMS |
| 3294 | #if OPTION_DDR2 |
| 3295 | #define PSC_C32_UDIMM_DDR2 //MemAGetPsCfgUDr2, |
| 3296 | #else |
| 3297 | #define PSC_C32_UDIMM_DDR2 |
| 3298 | #endif |
| 3299 | #if OPTION_DDR3 |
| 3300 | #define PSC_C32_UDIMM_DDR3 MemAGetPsCfgUC32_3, |
| 3301 | #else |
| 3302 | #define PSC_C32_UDIMM_DDR3 |
| 3303 | #endif |
| 3304 | #endif |
| 3305 | #if OPTION_RDIMMS |
| 3306 | #if OPTION_DDR2 |
| 3307 | #define PSC_C32_RDIMM_DDR2 |
| 3308 | #else |
| 3309 | #define PSC_C32_RDIMM_DDR2 |
| 3310 | #endif |
| 3311 | #if OPTION_DDR3 |
| 3312 | #define PSC_C32_RDIMM_DDR3 MemAGetPsCfgRC32_3, |
| 3313 | #else |
| 3314 | #define PSC_C32_RDIMM_DDR3 |
| 3315 | #endif |
| 3316 | #endif |
| 3317 | #if OPTION_SODIMMS |
| 3318 | #if OPTION_DDR2 |
| 3319 | #define PSC_C32_SODIMM_DDR2 //MemAGetPsCfgSC32_2, |
| 3320 | #else |
| 3321 | #define PSC_C32_SODIMM_DDR2 |
| 3322 | #endif |
| 3323 | #if OPTION_DDR3 |
| 3324 | #define PSC_C32_SODIMM_DDR3 //MemAGetPsCfgSC32_3, |
| 3325 | #else |
| 3326 | #define PSC_C32_SODIMM_DDR3 |
| 3327 | #endif |
| 3328 | #endif |
| 3329 | #endif |
| 3330 | |
| 3331 | #if OPTION_MEMCTLR_LN |
| 3332 | #if OPTION_UDIMMS |
| 3333 | #if OPTION_DDR2 |
| 3334 | #define PSC_LN_UDIMM_DDR2 //MemAGetPsCfgULN2, |
| 3335 | #else |
| 3336 | #define PSC_LN_UDIMM_DDR2 |
| 3337 | #endif |
| 3338 | #if OPTION_DDR3 |
| 3339 | #define PSC_LN_UDIMM_DDR3 MemAGetPsCfgULN3, |
| 3340 | #else |
| 3341 | #define PSC_LN_UDIMM_DDR3 |
| 3342 | #endif |
| 3343 | #endif |
| 3344 | #if OPTION_RDIMMS |
| 3345 | #if OPTION_DDR2 |
| 3346 | #define PSC_LN_RDIMM_DDR2 |
| 3347 | #else |
| 3348 | #define PSC_LN_RDIMM_DDR2 |
| 3349 | #endif |
| 3350 | #if OPTION_DDR3 |
| 3351 | #define PSC_LN_RDIMM_DDR3 //MemAGetPsCfgRLN3, |
| 3352 | #else |
| 3353 | #define PSC_LN_RDIMM_DDR3 |
| 3354 | #endif |
| 3355 | #endif |
| 3356 | #if OPTION_SODIMMS |
| 3357 | #if OPTION_DDR2 |
| 3358 | #define PSC_LN_SODIMM_DDR2 //MemAGetPsCfgSLN2, |
| 3359 | #else |
| 3360 | #define PSC_LN_SODIMM_DDR2 |
| 3361 | #endif |
| 3362 | #if OPTION_DDR3 |
| 3363 | #define PSC_LN_SODIMM_DDR3 MemAGetPsCfgSLN3, |
| 3364 | #else |
| 3365 | #define PSC_LN_SODIMM_DDR3 |
| 3366 | #endif |
| 3367 | #endif |
| 3368 | #endif |
| 3369 | |
| 3370 | #if OPTION_MEMCTLR_OR |
| 3371 | #if OPTION_UDIMMS |
| 3372 | #if OPTION_DDR2 |
| 3373 | #define PSC_OR_UDIMM_DDR2 //MemAGetPsCfgUOr2, |
| 3374 | #else |
| 3375 | #define PSC_OR_UDIMM_DDR2 |
| 3376 | #endif |
| 3377 | #if OPTION_DDR3 |
| 3378 | #define PSC_OR_UDIMM_DDR3 //MemAGetPsCfgUOr3, |
| 3379 | #else |
| 3380 | #define PSC_OR_UDIMM_DDR3 |
| 3381 | #endif |
| 3382 | #endif |
| 3383 | #if OPTION_RDIMMS |
| 3384 | #if OPTION_DDR2 |
| 3385 | #define PSC_OR_RDIMM_DDR2 |
| 3386 | #else |
| 3387 | #define PSC_OR_RDIMM_DDR2 |
| 3388 | #endif |
| 3389 | #if OPTION_DDR3 |
| 3390 | #define PSC_OR_RDIMM_DDR3 //MemAGetPsCfgROr3, |
| 3391 | #else |
| 3392 | #define PSC_OR_RDIMM_DDR3 |
| 3393 | #endif |
| 3394 | #endif |
| 3395 | #if OPTION_SODIMMS |
| 3396 | #if OPTION_DDR2 |
| 3397 | #define PSC_OR_SODIMM_DDR2 //MemAGetPsCfgSOr2, |
| 3398 | #else |
| 3399 | #define PSC_OR_SODIMM_DDR2 |
| 3400 | #endif |
| 3401 | #if OPTION_DDR3 |
| 3402 | #define PSC_OR_SODIMM_DDR3 //MemAGetPsCfgSOr3, |
| 3403 | #else |
| 3404 | #define PSC_OR_SODIMM_DDR3 |
| 3405 | #endif |
| 3406 | #endif |
| 3407 | #endif |
| 3408 | |
| 3409 | #if OPTION_MEMCTLR_ON |
| 3410 | #if OPTION_UDIMMS |
| 3411 | #if OPTION_DDR2 |
| 3412 | #define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2, |
| 3413 | #else |
| 3414 | #define PSC_ON_UDIMM_DDR2 |
| 3415 | #endif |
| 3416 | #if OPTION_DDR3 |
| 3417 | #define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3, |
| 3418 | #else |
| 3419 | #define PSC_ON_UDIMM_DDR3 |
| 3420 | #endif |
| 3421 | #endif |
| 3422 | #if OPTION_RDIMMS |
| 3423 | #if OPTION_DDR2 |
| 3424 | #define PSC_ON_RDIMM_DDR2 |
| 3425 | #else |
| 3426 | #define PSC_ON_RDIMM_DDR2 |
| 3427 | #endif |
| 3428 | #if OPTION_DDR3 |
| 3429 | #define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3, |
| 3430 | #else |
| 3431 | #define PSC_ON_RDIMM_DDR3 |
| 3432 | #endif |
| 3433 | #endif |
| 3434 | #if OPTION_SODIMMS |
| 3435 | #if OPTION_DDR2 |
| 3436 | #define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2, |
| 3437 | #else |
| 3438 | #define PSC_ON_SODIMM_DDR2 |
| 3439 | #endif |
| 3440 | #if OPTION_DDR3 |
| 3441 | #define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3, |
| 3442 | #else |
| 3443 | #define PSC_ON_SODIMM_DDR3 |
| 3444 | #endif |
| 3445 | #endif |
| 3446 | #endif |
| 3447 | |
| 3448 | /*---------------------------------------------------------------------- |
| 3449 | * DEFAULT PSCFG DEFINITIONS |
| 3450 | * |
| 3451 | *---------------------------------------------------------------------- |
| 3452 | */ |
| 3453 | |
| 3454 | #ifndef PSC_DR_UDIMM_DDR2 |
| 3455 | #define PSC_DR_UDIMM_DDR2 |
| 3456 | #endif |
| 3457 | #ifndef PSC_DR_RDIMM_DDR2 |
| 3458 | #define PSC_DR_RDIMM_DDR2 |
| 3459 | #endif |
| 3460 | #ifndef PSC_DR_SODIMM_DDR2 |
| 3461 | #define PSC_DR_SODIMM_DDR2 |
| 3462 | #endif |
| 3463 | #ifndef PSC_DR_UDIMM_DDR3 |
| 3464 | #define PSC_DR_UDIMM_DDR3 |
| 3465 | #endif |
| 3466 | #ifndef PSC_DR_RDIMM_DDR3 |
| 3467 | #define PSC_DR_RDIMM_DDR3 |
| 3468 | #endif |
| 3469 | #ifndef PSC_DR_SODIMM_DDR3 |
| 3470 | #define PSC_DR_SODIMM_DDR3 |
| 3471 | #endif |
| 3472 | #ifndef PSC_RB_UDIMM_DDR2 |
| 3473 | #define PSC_RB_UDIMM_DDR2 |
| 3474 | #endif |
| 3475 | #ifndef PSC_RB_RDIMM_DDR2 |
| 3476 | #define PSC_RB_RDIMM_DDR2 |
| 3477 | #endif |
| 3478 | #ifndef PSC_RB_SODIMM_DDR2 |
| 3479 | #define PSC_RB_SODIMM_DDR2 |
| 3480 | #endif |
| 3481 | #ifndef PSC_RB_UDIMM_DDR3 |
| 3482 | #define PSC_RB_UDIMM_DDR3 |
| 3483 | #endif |
| 3484 | #ifndef PSC_RB_RDIMM_DDR3 |
| 3485 | #define PSC_RB_RDIMM_DDR3 |
| 3486 | #endif |
| 3487 | #ifndef PSC_RB_SODIMM_DDR3 |
| 3488 | #define PSC_RB_SODIMM_DDR3 |
| 3489 | #endif |
| 3490 | #ifndef PSC_DA_UDIMM_DDR2 |
| 3491 | #define PSC_DA_UDIMM_DDR2 |
| 3492 | #endif |
| 3493 | #ifndef PSC_DA_RDIMM_DDR2 |
| 3494 | #define PSC_DA_RDIMM_DDR2 |
| 3495 | #endif |
| 3496 | #ifndef PSC_DA_SODIMM_DDR2 |
| 3497 | #define PSC_DA_SODIMM_DDR2 |
| 3498 | #endif |
| 3499 | #ifndef PSC_DA_UDIMM_DDR3 |
| 3500 | #define PSC_DA_UDIMM_DDR3 |
| 3501 | #endif |
| 3502 | #ifndef PSC_DA_RDIMM_DDR3 |
| 3503 | #define PSC_DA_RDIMM_DDR3 |
| 3504 | #endif |
| 3505 | #ifndef PSC_DA_SODIMM_DDR3 |
| 3506 | #define PSC_DA_SODIMM_DDR3 |
| 3507 | #endif |
| 3508 | #ifndef PSC_NI_UDIMM_DDR2 |
| 3509 | #define PSC_NI_UDIMM_DDR2 |
| 3510 | #endif |
| 3511 | #ifndef PSC_NI_RDIMM_DDR2 |
| 3512 | #define PSC_NI_RDIMM_DDR2 |
| 3513 | #endif |
| 3514 | #ifndef PSC_NI_SODIMM_DDR2 |
| 3515 | #define PSC_NI_SODIMM_DDR2 |
| 3516 | #endif |
| 3517 | #ifndef PSC_NI_UDIMM_DDR3 |
| 3518 | #define PSC_NI_UDIMM_DDR3 |
| 3519 | #endif |
| 3520 | #ifndef PSC_NI_RDIMM_DDR3 |
| 3521 | #define PSC_NI_RDIMM_DDR3 |
| 3522 | #endif |
| 3523 | #ifndef PSC_NI_SODIMM_DDR3 |
| 3524 | #define PSC_NI_SODIMM_DDR3 |
| 3525 | #endif |
| 3526 | #ifndef PSC_PH_UDIMM_DDR2 |
| 3527 | #define PSC_PH_UDIMM_DDR2 |
| 3528 | #endif |
| 3529 | #ifndef PSC_PH_RDIMM_DDR2 |
| 3530 | #define PSC_PH_RDIMM_DDR2 |
| 3531 | #endif |
| 3532 | #ifndef PSC_PH_SODIMM_DDR2 |
| 3533 | #define PSC_PH_SODIMM_DDR2 |
| 3534 | #endif |
| 3535 | #ifndef PSC_PH_UDIMM_DDR3 |
| 3536 | #define PSC_PH_UDIMM_DDR3 |
| 3537 | #endif |
| 3538 | #ifndef PSC_PH_RDIMM_DDR3 |
| 3539 | #define PSC_PH_RDIMM_DDR3 |
| 3540 | #endif |
| 3541 | #ifndef PSC_PH_SODIMM_DDR3 |
| 3542 | #define PSC_PH_SODIMM_DDR3 |
| 3543 | #endif |
| 3544 | #ifndef PSC_HY_UDIMM_DDR2 |
| 3545 | #define PSC_HY_UDIMM_DDR2 |
| 3546 | #endif |
| 3547 | #ifndef PSC_HY_RDIMM_DDR2 |
| 3548 | #define PSC_HY_RDIMM_DDR2 |
| 3549 | #endif |
| 3550 | #ifndef PSC_HY_SODIMM_DDR2 |
| 3551 | #define PSC_HY_SODIMM_DDR2 |
| 3552 | #endif |
| 3553 | #ifndef PSC_HY_UDIMM_DDR3 |
| 3554 | #define PSC_HY_UDIMM_DDR3 |
| 3555 | #endif |
| 3556 | #ifndef PSC_HY_RDIMM_DDR3 |
| 3557 | #define PSC_HY_RDIMM_DDR3 |
| 3558 | #endif |
| 3559 | #ifndef PSC_HY_SODIMM_DDR3 |
| 3560 | #define PSC_HY_SODIMM_DDR3 |
| 3561 | #endif |
| 3562 | #ifndef PSC_LN_UDIMM_DDR2 |
| 3563 | #define PSC_LN_UDIMM_DDR2 |
| 3564 | #endif |
| 3565 | #ifndef PSC_LN_RDIMM_DDR2 |
| 3566 | #define PSC_LN_RDIMM_DDR2 |
| 3567 | #endif |
| 3568 | #ifndef PSC_LN_SODIMM_DDR2 |
| 3569 | #define PSC_LN_SODIMM_DDR2 |
| 3570 | #endif |
| 3571 | #ifndef PSC_LN_UDIMM_DDR3 |
| 3572 | #define PSC_LN_UDIMM_DDR3 |
| 3573 | #endif |
| 3574 | #ifndef PSC_LN_RDIMM_DDR3 |
| 3575 | #define PSC_LN_RDIMM_DDR3 |
| 3576 | #endif |
| 3577 | #ifndef PSC_LN_SODIMM_DDR3 |
| 3578 | #define PSC_LN_SODIMM_DDR3 |
| 3579 | #endif |
| 3580 | #ifndef PSC_OR_UDIMM_DDR2 |
| 3581 | #define PSC_OR_UDIMM_DDR2 |
| 3582 | #endif |
| 3583 | #ifndef PSC_OR_RDIMM_DDR2 |
| 3584 | #define PSC_OR_RDIMM_DDR2 |
| 3585 | #endif |
| 3586 | #ifndef PSC_OR_SODIMM_DDR2 |
| 3587 | #define PSC_OR_SODIMM_DDR2 |
| 3588 | #endif |
| 3589 | #ifndef PSC_OR_UDIMM_DDR3 |
| 3590 | #define PSC_OR_UDIMM_DDR3 |
| 3591 | #endif |
| 3592 | #ifndef PSC_OR_RDIMM_DDR3 |
| 3593 | #define PSC_OR_RDIMM_DDR3 |
| 3594 | #endif |
| 3595 | #ifndef PSC_OR_SODIMM_DDR3 |
| 3596 | #define PSC_OR_SODIMM_DDR3 |
| 3597 | #endif |
| 3598 | #ifndef PSC_C32_UDIMM_DDR3 |
| 3599 | #define PSC_C32_UDIMM_DDR3 |
| 3600 | #endif |
| 3601 | #ifndef PSC_C32_RDIMM_DDR3 |
| 3602 | #define PSC_C32_RDIMM_DDR3 |
| 3603 | #endif |
| 3604 | #ifndef PSC_ON_UDIMM_DDR2 |
| 3605 | #define PSC_ON_UDIMM_DDR2 |
| 3606 | #endif |
| 3607 | #ifndef PSC_ON_RDIMM_DDR2 |
| 3608 | #define PSC_ON_RDIMM_DDR2 |
| 3609 | #endif |
| 3610 | #ifndef PSC_ON_SODIMM_DDR2 |
| 3611 | #define PSC_ON_SODIMM_DDR2 |
| 3612 | #endif |
| 3613 | #ifndef PSC_ON_UDIMM_DDR3 |
| 3614 | #define PSC_ON_UDIMM_DDR3 |
| 3615 | #endif |
| 3616 | #ifndef PSC_ON_RDIMM_DDR3 |
| 3617 | #define PSC_ON_RDIMM_DDR3 |
| 3618 | #endif |
| 3619 | #ifndef PSC_ON_SODIMM_DDR3 |
| 3620 | #define PSC_ON_SODIMM_DDR3 |
| 3621 | #endif |
| 3622 | |
| 3623 | MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { |
| 3624 | PSC_DR_UDIMM_DDR2 |
| 3625 | PSC_DR_RDIMM_DDR2 |
| 3626 | PSC_DR_SODIMM_DDR2 |
| 3627 | PSC_DR_UDIMM_DDR3 |
| 3628 | PSC_DR_RDIMM_DDR3 |
| 3629 | PSC_DR_SODIMM_DDR3 |
| 3630 | PSC_RB_UDIMM_DDR3 |
| 3631 | PSC_RB_SODIMM_DDR3 |
| 3632 | PSC_DA_SODIMM_DDR2 |
| 3633 | PSC_DA_UDIMM_DDR3 |
| 3634 | PSC_DA_SODIMM_DDR3 |
| 3635 | PSC_NI_UDIMM_DDR3 |
| 3636 | PSC_NI_SODIMM_DDR3 |
| 3637 | PSC_PH_UDIMM_DDR3 |
| 3638 | PSC_PH_SODIMM_DDR3 |
| 3639 | PSC_HY_UDIMM_DDR3 |
| 3640 | PSC_HY_RDIMM_DDR3 |
| 3641 | PSC_HY_SODIMM_DDR3 |
| 3642 | PSC_LN_UDIMM_DDR3 |
| 3643 | PSC_LN_RDIMM_DDR3 |
| 3644 | PSC_LN_SODIMM_DDR3 |
| 3645 | PSC_OR_UDIMM_DDR3 |
| 3646 | PSC_OR_RDIMM_DDR3 |
| 3647 | PSC_OR_SODIMM_DDR3 |
| 3648 | PSC_C32_UDIMM_DDR3 |
| 3649 | PSC_C32_RDIMM_DDR3 |
| 3650 | PSC_ON_UDIMM_DDR3 |
| 3651 | PSC_ON_RDIMM_DDR3 |
| 3652 | PSC_ON_SODIMM_DDR3 |
| 3653 | NULL |
| 3654 | }; |
| 3655 | CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); |
| 3656 | //remove warning#if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES |
| 3657 | // #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES |
| 3658 | //#endif |
| 3659 | |
| 3660 | /*--------------------------------------------------------------------------------------------------- |
| 3661 | * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION |
| 3662 | * |
| 3663 | * |
| 3664 | *--------------------------------------------------------------------------------------------------- |
| 3665 | */ |
| 3666 | #define MEM_PSC_FLOW_BLOCK_END NULL |
| 3667 | #define PSC_TBL_END NULL |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 3668 | #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, CONST MEM_PSC_TABLE_BLOCK *)) memDefTrue |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 3669 | |
| 3670 | #if OPTION_MEMCTLR_OR |
| 3671 | #if OPTION_UDIMMS |
| 3672 | #if OPTION_AM3_SOCKET_SUPPORT |
| 3673 | extern PSC_TBL_ENTRY MaxFreqTblEntUAM3; |
| 3674 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 &MaxFreqTblEntUAM3, |
| 3675 | extern PSC_TBL_ENTRY DramTermTblEntUAM3; |
| 3676 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &DramTermTblEntUAM3, |
| 3677 | extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3; |
| 3678 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &OdtPat1DTblEntUAM3, |
| 3679 | extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3; |
| 3680 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &OdtPat2DTblEntUAM3, |
| 3681 | extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3; |
| 3682 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &OdtPat3DTblEntUAM3, |
| 3683 | extern PSC_TBL_ENTRY SAOTblEntUAM3; |
| 3684 | #define PSC_TBL_OR_UDIMM3_SAO_AM3 &SAOTblEntUAM3, |
| 3685 | extern PSC_TBL_ENTRY ClkDisMapEntUAM3; |
| 3686 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3, |
| 3687 | extern PSC_TBL_ENTRY S2DTblEntUAM3; |
| 3688 | #define PSC_TBL_OR_UDIMM3_S2D_AM3 &S2DTblEntUAM3, |
| 3689 | extern PSC_TBL_ENTRY WLPass1SeedEntUAM3; |
| 3690 | #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 &WLPass1SeedEntUAM3, |
| 3691 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3; |
| 3692 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 &HWRxEnPass1SeedEntUAM3, |
| 3693 | #endif |
| 3694 | #if OPTION_C32_SOCKET_SUPPORT |
| 3695 | extern PSC_TBL_ENTRY MaxFreqTblEntUC32; |
| 3696 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 &MaxFreqTblEntUC32, |
| 3697 | extern PSC_TBL_ENTRY DramTermTblEntUC32; |
| 3698 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 &DramTermTblEntUC32, |
| 3699 | extern PSC_TBL_ENTRY OdtPat1DTblEntUC32; |
| 3700 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntUC32, |
| 3701 | extern PSC_TBL_ENTRY OdtPat2DTblEntUC32; |
| 3702 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntUC32, |
| 3703 | extern PSC_TBL_ENTRY OdtPat3DTblEntUC32; |
| 3704 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntUC32, |
| 3705 | extern PSC_TBL_ENTRY SAOTblEntUC32; |
| 3706 | #define PSC_TBL_OR_UDIMM3_SAO_C32 &SAOTblEntUC32, |
| 3707 | extern PSC_TBL_ENTRY ClkDisMapEntUC32; |
| 3708 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32, |
| 3709 | extern PSC_TBL_ENTRY ClkDisMap3DEntUC32; |
| 3710 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32, |
| 3711 | extern PSC_TBL_ENTRY S2DTblEntUC32; |
| 3712 | #define PSC_TBL_OR_UDIMM3_S2D_C32 &S2DTblEntUC32, |
| 3713 | extern PSC_TBL_ENTRY WLPass1SeedEntUC32; |
| 3714 | #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 &WLPass1SeedEntUC32, |
| 3715 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32; |
| 3716 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntUC32, |
| 3717 | #endif |
| 3718 | #if OPTION_G34_SOCKET_SUPPORT |
| 3719 | extern PSC_TBL_ENTRY MaxFreqTblEntUG34; |
| 3720 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 &MaxFreqTblEntUG34, |
| 3721 | extern PSC_TBL_ENTRY DramTermTblEntUG34; |
| 3722 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 &DramTermTblEntUG34, |
| 3723 | extern PSC_TBL_ENTRY OdtPat1DTblEntUG34; |
| 3724 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntUG34, |
| 3725 | extern PSC_TBL_ENTRY OdtPat2DTblEntUG34; |
| 3726 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntUG34, |
| 3727 | extern PSC_TBL_ENTRY OdtPat3DTblEntUG34; |
| 3728 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntUG34, |
| 3729 | extern PSC_TBL_ENTRY SAOTblEntUG34; |
| 3730 | #define PSC_TBL_OR_UDIMM3_SAO_G34 &SAOTblEntUG34, |
| 3731 | extern PSC_TBL_ENTRY ClkDisMapEntUG34; |
| 3732 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34, |
| 3733 | extern PSC_TBL_ENTRY S2DTblEntUG34; |
| 3734 | #define PSC_TBL_OR_UDIMM3_S2D_G34 &S2DTblEntUG34, |
| 3735 | extern PSC_TBL_ENTRY WLPass1SeedEntUG34; |
| 3736 | #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 &WLPass1SeedEntUG34, |
| 3737 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34; |
| 3738 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntUG34, |
| 3739 | #endif |
| 3740 | #endif |
| 3741 | #if OPTION_RDIMMS |
| 3742 | #if OPTION_C32_SOCKET_SUPPORT |
| 3743 | extern PSC_TBL_ENTRY MaxFreqTblEntRC32; |
| 3744 | #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 &MaxFreqTblEntRC32, |
| 3745 | extern PSC_TBL_ENTRY DramTermTblEntRC32; |
| 3746 | #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 &DramTermTblEntRC32, |
| 3747 | extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; |
| 3748 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntRC32, |
| 3749 | extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; |
| 3750 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntRC32, |
| 3751 | extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; |
| 3752 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntRC32, |
| 3753 | extern PSC_TBL_ENTRY SAOTblEntRC32; |
| 3754 | #define PSC_TBL_OR_RDIMM3_SAO_C32 &SAOTblEntRC32, |
| 3755 | extern PSC_TBL_ENTRY RC2IBTTblEntRC32; |
| 3756 | #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 &RC2IBTTblEntRC32, |
| 3757 | extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32; |
| 3758 | #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 &RC10OpSpdTblEntRC32, |
| 3759 | extern PSC_TBL_ENTRY ClkDisMapEntRC32; |
| 3760 | #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32, |
| 3761 | extern PSC_TBL_ENTRY S2DTblEntRC32; |
| 3762 | #define PSC_TBL_OR_RDIMM3_S2D_C32 &S2DTblEntRC32, |
| 3763 | extern PSC_TBL_ENTRY WLPass1SeedEntRC32; |
| 3764 | #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 &WLPass1SeedEntRC32, |
| 3765 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32; |
| 3766 | #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntRC32, |
| 3767 | #endif |
| 3768 | #if OPTION_G34_SOCKET_SUPPORT |
| 3769 | extern PSC_TBL_ENTRY MaxFreqTblEntRG34; |
| 3770 | #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 &MaxFreqTblEntRG34, |
| 3771 | extern PSC_TBL_ENTRY DramTermTblEntRG34; |
| 3772 | #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 &DramTermTblEntRG34, |
| 3773 | extern PSC_TBL_ENTRY OdtPat1DTblEntRG34; |
| 3774 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntRG34, |
| 3775 | extern PSC_TBL_ENTRY OdtPat2DTblEntRG34; |
| 3776 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntRG34, |
| 3777 | extern PSC_TBL_ENTRY OdtPat3DTblEntRG34; |
| 3778 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntRG34, |
| 3779 | extern PSC_TBL_ENTRY SAOTblEntRG34; |
| 3780 | #define PSC_TBL_OR_RDIMM3_SAO_G34 &SAOTblEntRG34, |
| 3781 | extern PSC_TBL_ENTRY RC2IBTTblEntRG34; |
| 3782 | #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 &RC2IBTTblEntRG34, |
| 3783 | extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34; |
| 3784 | #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 &RC10OpSpdTblEntRG34, |
| 3785 | extern PSC_TBL_ENTRY ClkDisMapEntRG34; |
| 3786 | #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34, |
| 3787 | extern PSC_TBL_ENTRY S2DTblEntRG34; |
| 3788 | #define PSC_TBL_OR_RDIMM3_S2D_G34 &S2DTblEntRG34, |
| 3789 | extern PSC_TBL_ENTRY WLPass1SeedEntRG34; |
| 3790 | #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 &WLPass1SeedEntRG34, |
| 3791 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34; |
| 3792 | #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntRG34, |
| 3793 | #endif |
| 3794 | #endif |
| 3795 | //#if OPTION_SODIMMS |
| 3796 | //#endif |
| 3797 | #if OPTION_LRDIMMS |
| 3798 | // #if OPTION_C32_SOCKET_SUPPORT |
| 3799 | // extern PSC_TBL_ENTRY MaxFreqTblEntLRC32; |
| 3800 | // #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 &MaxFreqTblEntLRC32, |
| 3801 | // extern PSC_TBL_ENTRY DramTermTblEntLRC32; |
| 3802 | // #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 &DramTermTblEntLRC32, |
| 3803 | // extern PSC_TBL_ENTRY OdtPat1DTblEntRC32; |
| 3804 | // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 &OdtPat1DTblEntLRC32, |
| 3805 | // extern PSC_TBL_ENTRY OdtPat2DTblEntRC32; |
| 3806 | // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 &OdtPat2DTblEntLRC32, |
| 3807 | // extern PSC_TBL_ENTRY OdtPat3DTblEntRC32; |
| 3808 | // #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 &OdtPat3DTblEntLRC32, |
| 3809 | // extern PSC_TBL_ENTRY SAOTblEntRC32; |
| 3810 | // #define PSC_TBL_OR_LRDIMM3_SAO_C32 &SAOTblEntLRC32, |
| 3811 | // extern PSC_TBL_ENTRY IBTTblEntLRC32; |
| 3812 | // #define PSC_TBL_OR_LRDIMM3_IBT_C32 &IBTTblEntLRC32, |
| 3813 | // extern PSC_TBL_ENTRY ClkDisMapEntLRC32; |
| 3814 | // #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32, |
| 3815 | // extern PSC_TBL_ENTRY S2DTblEntLRC32; |
| 3816 | // #define PSC_TBL_OR_LRDIMM3_S2D_C32 &S2DTblEntLRC32, |
| 3817 | // #endif |
| 3818 | #if OPTION_G34_SOCKET_SUPPORT |
| 3819 | extern PSC_TBL_ENTRY MaxFreqTblEntLRG34; |
| 3820 | #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 &MaxFreqTblEntLRG34, |
| 3821 | extern PSC_TBL_ENTRY DramTermTblEntLRG34; |
| 3822 | #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 &DramTermTblEntLRG34, |
| 3823 | extern PSC_TBL_ENTRY OdtPat1DTblEntLRG34; |
| 3824 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 &OdtPat1DTblEntLRG34, |
| 3825 | extern PSC_TBL_ENTRY OdtPat2DTblEntLRG34; |
| 3826 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 &OdtPat2DTblEntLRG34, |
| 3827 | extern PSC_TBL_ENTRY OdtPat3DTblEntLRG34; |
| 3828 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 &OdtPat3DTblEntLRG34, |
| 3829 | extern PSC_TBL_ENTRY SAOTblEntLRG34; |
| 3830 | #define PSC_TBL_OR_LRDIMM3_SAO_G34 &SAOTblEntLRG34, |
| 3831 | extern PSC_TBL_ENTRY IBTTblEntLRG34; |
| 3832 | #define PSC_TBL_OR_LRDIMM3_IBT_G34 &IBTTblEntLRG34, |
| 3833 | extern PSC_TBL_ENTRY ClkDisMapEntLRG34; |
| 3834 | #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34, |
| 3835 | extern PSC_TBL_ENTRY S2DTblEntLRG34; |
| 3836 | #define PSC_TBL_OR_LRDIMM3_S2D_G34 &S2DTblEntLRG34, |
| 3837 | extern PSC_TBL_ENTRY WLPass1SeedEntLRG34; |
| 3838 | #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 &WLPass1SeedEntLRG34, |
| 3839 | extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34; |
| 3840 | #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34, |
| 3841 | #endif |
| 3842 | #endif |
| 3843 | extern PSC_TBL_ENTRY MR0WrTblEntry; |
| 3844 | #define PSC_TBL_OR_MR0_WR &MR0WrTblEntry, |
| 3845 | extern PSC_TBL_ENTRY MR0CLTblEntry; |
| 3846 | #define PSC_TBL_OR_MR0_CL &MR0CLTblEntry, |
| 3847 | extern PSC_TBL_ENTRY OrDdr3CKETriEnt; |
| 3848 | #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt, |
| 3849 | extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt; |
| 3850 | #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt, |
| 3851 | extern PSC_TBL_ENTRY OrDdr3ODTTriEnt; |
| 3852 | #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt, |
| 3853 | extern PSC_TBL_ENTRY OrUDdr3CSTriEnt; |
| 3854 | #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt, |
| 3855 | extern PSC_TBL_ENTRY OrDdr3CSTriEnt; |
| 3856 | #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt, |
| 3857 | extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt; |
| 3858 | #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt, |
| 3859 | extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt; |
| 3860 | #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt, |
| 3861 | |
| 3862 | #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 |
| 3863 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 |
| 3864 | #endif |
| 3865 | #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 |
| 3866 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 |
| 3867 | #endif |
| 3868 | #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 |
| 3869 | #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 |
| 3870 | #endif |
| 3871 | #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 |
| 3872 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 |
| 3873 | #endif |
| 3874 | #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 |
| 3875 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 |
| 3876 | #endif |
| 3877 | #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 |
| 3878 | #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 |
| 3879 | #endif |
| 3880 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 |
| 3881 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 |
| 3882 | #endif |
| 3883 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 |
| 3884 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 |
| 3885 | #endif |
| 3886 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 |
| 3887 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 |
| 3888 | #endif |
| 3889 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 |
| 3890 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 |
| 3891 | #endif |
| 3892 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 |
| 3893 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 |
| 3894 | #endif |
| 3895 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 |
| 3896 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 |
| 3897 | #endif |
| 3898 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 |
| 3899 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 |
| 3900 | #endif |
| 3901 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 |
| 3902 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 |
| 3903 | #endif |
| 3904 | #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 |
| 3905 | #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 |
| 3906 | #endif |
| 3907 | #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3 |
| 3908 | #define PSC_TBL_OR_UDIMM3_SAO_AM3 |
| 3909 | #endif |
| 3910 | #ifndef PSC_TBL_OR_UDIMM3_SAO_C32 |
| 3911 | #define PSC_TBL_OR_UDIMM3_SAO_C32 |
| 3912 | #endif |
| 3913 | #ifndef PSC_TBL_OR_UDIMM3_SAO_G34 |
| 3914 | #define PSC_TBL_OR_UDIMM3_SAO_G34 |
| 3915 | #endif |
| 3916 | #ifndef PSC_TBL_OR_UDIMM3_S2D_AM3 |
| 3917 | #define PSC_TBL_OR_UDIMM3_S2D_AM3 |
| 3918 | #endif |
| 3919 | #ifndef PSC_TBL_OR_UDIMM3_S2D_C32 |
| 3920 | #define PSC_TBL_OR_UDIMM3_S2D_C32 |
| 3921 | #endif |
| 3922 | #ifndef PSC_TBL_OR_UDIMM3_S2D_G34 |
| 3923 | #define PSC_TBL_OR_UDIMM3_S2D_G34 |
| 3924 | #endif |
| 3925 | #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_AM3 |
| 3926 | #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3 |
| 3927 | #endif |
| 3928 | #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_C32 |
| 3929 | #define PSC_TBL_OR_UDIMM3_WL_SEED_C32 |
| 3930 | #endif |
| 3931 | #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_G34 |
| 3932 | #define PSC_TBL_OR_UDIMM3_WL_SEED_G34 |
| 3933 | #endif |
| 3934 | #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 |
| 3935 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 |
| 3936 | #endif |
| 3937 | #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 |
| 3938 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 |
| 3939 | #endif |
| 3940 | #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 |
| 3941 | #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 |
| 3942 | #endif |
| 3943 | #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 |
| 3944 | #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 |
| 3945 | #endif |
| 3946 | #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 |
| 3947 | #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 |
| 3948 | #endif |
| 3949 | #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 |
| 3950 | #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 |
| 3951 | #endif |
| 3952 | #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 |
| 3953 | #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 |
| 3954 | #endif |
| 3955 | #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 |
| 3956 | #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 |
| 3957 | #endif |
| 3958 | #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 |
| 3959 | #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 |
| 3960 | #endif |
| 3961 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 |
| 3962 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 |
| 3963 | #endif |
| 3964 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 |
| 3965 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 |
| 3966 | #endif |
| 3967 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 |
| 3968 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 |
| 3969 | #endif |
| 3970 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 |
| 3971 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 |
| 3972 | #endif |
| 3973 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 |
| 3974 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 |
| 3975 | #endif |
| 3976 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 |
| 3977 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 |
| 3978 | #endif |
| 3979 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 |
| 3980 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 |
| 3981 | #endif |
| 3982 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 |
| 3983 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 |
| 3984 | #endif |
| 3985 | #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 |
| 3986 | #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 |
| 3987 | #endif |
| 3988 | #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3 |
| 3989 | #define PSC_TBL_OR_RDIMM3_SAO_AM3 |
| 3990 | #endif |
| 3991 | #ifndef PSC_TBL_OR_RDIMM3_SAO_C32 |
| 3992 | #define PSC_TBL_OR_RDIMM3_SAO_C32 |
| 3993 | #endif |
| 3994 | #ifndef PSC_TBL_OR_RDIMM3_SAO_G34 |
| 3995 | #define PSC_TBL_OR_RDIMM3_SAO_G34 |
| 3996 | #endif |
| 3997 | #ifndef PSC_TBL_OR_RDIMM3_S2D_AM3 |
| 3998 | #define PSC_TBL_OR_RDIMM3_S2D_AM3 |
| 3999 | #endif |
| 4000 | #ifndef PSC_TBL_OR_RDIMM3_S2D_C32 |
| 4001 | #define PSC_TBL_OR_RDIMM3_S2D_C32 |
| 4002 | #endif |
| 4003 | #ifndef PSC_TBL_OR_RDIMM3_S2D_G34 |
| 4004 | #define PSC_TBL_OR_RDIMM3_S2D_G34 |
| 4005 | #endif |
| 4006 | #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3 |
| 4007 | #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3 |
| 4008 | #endif |
| 4009 | #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32 |
| 4010 | #define PSC_TBL_OR_RDIMM3_RC2IBT_C32 |
| 4011 | #endif |
| 4012 | #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34 |
| 4013 | #define PSC_TBL_OR_RDIMM3_RC2IBT_G34 |
| 4014 | #endif |
| 4015 | #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 |
| 4016 | #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 |
| 4017 | #endif |
| 4018 | #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 |
| 4019 | #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 |
| 4020 | #endif |
| 4021 | #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 |
| 4022 | #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 |
| 4023 | #endif |
| 4024 | #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_AM3 |
| 4025 | #define PSC_TBL_OR_RDIMM3_WL_SEED_AM3 |
| 4026 | #endif |
| 4027 | #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_C32 |
| 4028 | #define PSC_TBL_OR_RDIMM3_WL_SEED_C32 |
| 4029 | #endif |
| 4030 | #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_G34 |
| 4031 | #define PSC_TBL_OR_RDIMM3_WL_SEED_G34 |
| 4032 | #endif |
| 4033 | #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 |
| 4034 | #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 |
| 4035 | #endif |
| 4036 | #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 |
| 4037 | #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 |
| 4038 | #endif |
| 4039 | #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 |
| 4040 | #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 |
| 4041 | #endif |
| 4042 | #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 |
| 4043 | #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 |
| 4044 | #endif |
| 4045 | #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 |
| 4046 | #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 |
| 4047 | #endif |
| 4048 | #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 |
| 4049 | #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 |
| 4050 | #endif |
| 4051 | #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 |
| 4052 | #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 |
| 4053 | #endif |
| 4054 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 |
| 4055 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 |
| 4056 | #endif |
| 4057 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 |
| 4058 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 |
| 4059 | #endif |
| 4060 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 |
| 4061 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 |
| 4062 | #endif |
| 4063 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 |
| 4064 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 |
| 4065 | #endif |
| 4066 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 |
| 4067 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 |
| 4068 | #endif |
| 4069 | #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 |
| 4070 | #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 |
| 4071 | #endif |
| 4072 | #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32 |
| 4073 | #define PSC_TBL_OR_LRDIMM3_SAO_C32 |
| 4074 | #endif |
| 4075 | #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34 |
| 4076 | #define PSC_TBL_OR_LRDIMM3_SAO_G34 |
| 4077 | #endif |
| 4078 | #ifndef PSC_TBL_OR_LRDIMM3_S2D_C32 |
| 4079 | #define PSC_TBL_OR_LRDIMM3_S2D_C32 |
| 4080 | #endif |
| 4081 | #ifndef PSC_TBL_OR_LRDIMM3_S2D_G34 |
| 4082 | #define PSC_TBL_OR_LRDIMM3_S2D_G34 |
| 4083 | #endif |
| 4084 | #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32 |
| 4085 | #define PSC_TBL_OR_LRDIMM3_IBT_C32 |
| 4086 | #endif |
| 4087 | #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34 |
| 4088 | #define PSC_TBL_OR_LRDIMM3_IBT_G34 |
| 4089 | #endif |
| 4090 | #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 |
| 4091 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 |
| 4092 | #endif |
| 4093 | #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32 |
| 4094 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 |
| 4095 | #endif |
| 4096 | #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 |
| 4097 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 |
| 4098 | #endif |
| 4099 | #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34 |
| 4100 | #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 |
| 4101 | #endif |
| 4102 | #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32 |
| 4103 | #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 |
| 4104 | #endif |
| 4105 | #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34 |
| 4106 | #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 |
| 4107 | #endif |
| 4108 | #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 |
| 4109 | #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 |
| 4110 | #endif |
| 4111 | #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 |
| 4112 | #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 |
| 4113 | #endif |
| 4114 | #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 |
| 4115 | #define PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 |
| 4116 | #endif |
| 4117 | #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_C32 |
| 4118 | #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32 |
| 4119 | #endif |
| 4120 | #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_G34 |
| 4121 | #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34 |
| 4122 | #endif |
| 4123 | #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 |
| 4124 | #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 |
| 4125 | #endif |
| 4126 | #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 |
| 4127 | #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 |
| 4128 | #endif |
| 4129 | #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 |
| 4130 | #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 |
| 4131 | #endif |
| 4132 | |
| 4133 | |
| 4134 | PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = { |
| 4135 | PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3 |
| 4136 | PSC_TBL_OR_UDIMM3_MAX_FREQ_C32 |
| 4137 | PSC_TBL_OR_UDIMM3_MAX_FREQ_G34 |
| 4138 | PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3 |
| 4139 | PSC_TBL_OR_RDIMM3_MAX_FREQ_C32 |
| 4140 | PSC_TBL_OR_RDIMM3_MAX_FREQ_G34 |
| 4141 | PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32 |
| 4142 | PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34 |
| 4143 | PSC_TBL_END |
| 4144 | }; |
| 4145 | |
| 4146 | PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = { |
| 4147 | PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3 |
| 4148 | PSC_TBL_OR_UDIMM3_DRAM_TERM_C32 |
| 4149 | PSC_TBL_OR_UDIMM3_DRAM_TERM_G34 |
| 4150 | PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3 |
| 4151 | PSC_TBL_OR_RDIMM3_DRAM_TERM_C32 |
| 4152 | PSC_TBL_OR_RDIMM3_DRAM_TERM_G34 |
| 4153 | PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32 |
| 4154 | PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34 |
| 4155 | PSC_TBL_END |
| 4156 | }; |
| 4157 | |
| 4158 | PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = { |
| 4159 | PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 |
| 4160 | PSC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 |
| 4161 | PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 |
| 4162 | PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3 |
| 4163 | PSC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3 |
| 4164 | PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3 |
| 4165 | PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 |
| 4166 | PSC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 |
| 4167 | PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 |
| 4168 | PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 |
| 4169 | PSC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 |
| 4170 | PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 |
| 4171 | PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32 |
| 4172 | PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_C32 |
| 4173 | PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32 |
| 4174 | PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 |
| 4175 | PSC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 |
| 4176 | PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 |
| 4177 | PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 |
| 4178 | PSC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 |
| 4179 | PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 |
| 4180 | PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34 |
| 4181 | PSC_TBL_OR_LRDIMM3_ODT_PAT_2D_G34 |
| 4182 | PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34 |
| 4183 | PSC_TBL_END |
| 4184 | }; |
| 4185 | |
| 4186 | PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = { |
| 4187 | PSC_TBL_OR_UDIMM3_SAO_AM3 |
| 4188 | PSC_TBL_OR_UDIMM3_SAO_C32 |
| 4189 | PSC_TBL_OR_UDIMM3_SAO_G34 |
| 4190 | PSC_TBL_OR_RDIMM3_SAO_AM3 |
| 4191 | PSC_TBL_OR_RDIMM3_SAO_C32 |
| 4192 | PSC_TBL_OR_RDIMM3_SAO_G34 |
| 4193 | PSC_TBL_OR_LRDIMM3_SAO_C32 |
| 4194 | PSC_TBL_OR_LRDIMM3_SAO_G34 |
| 4195 | PSC_TBL_END |
| 4196 | }; |
| 4197 | |
| 4198 | PSC_TBL_ENTRY* memPSCTblS2DArrayOR[] = { |
| 4199 | PSC_TBL_OR_UDIMM3_S2D_AM3 |
| 4200 | PSC_TBL_OR_UDIMM3_S2D_C32 |
| 4201 | PSC_TBL_OR_UDIMM3_S2D_G34 |
| 4202 | PSC_TBL_OR_RDIMM3_S2D_AM3 |
| 4203 | PSC_TBL_OR_RDIMM3_S2D_C32 |
| 4204 | PSC_TBL_OR_RDIMM3_S2D_G34 |
| 4205 | PSC_TBL_OR_LRDIMM3_S2D_C32 |
| 4206 | PSC_TBL_OR_LRDIMM3_S2D_G34 |
| 4207 | PSC_TBL_END |
| 4208 | }; |
| 4209 | |
| 4210 | PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = { |
| 4211 | PSC_TBL_OR_MR0_WR |
| 4212 | PSC_TBL_END |
| 4213 | }; |
| 4214 | |
| 4215 | PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = { |
| 4216 | PSC_TBL_OR_MR0_CL |
| 4217 | PSC_TBL_END |
| 4218 | }; |
| 4219 | |
| 4220 | PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = { |
| 4221 | PSC_TBL_OR_RDIMM3_RC2IBT_AM3 |
| 4222 | PSC_TBL_OR_RDIMM3_RC2IBT_C32 |
| 4223 | PSC_TBL_OR_RDIMM3_RC2IBT_G34 |
| 4224 | PSC_TBL_END |
| 4225 | }; |
| 4226 | |
| 4227 | PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = { |
| 4228 | PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3 |
| 4229 | PSC_TBL_OR_RDIMM3_RC10OPSPD_C32 |
| 4230 | PSC_TBL_OR_RDIMM3_RC10OPSPD_G34 |
| 4231 | PSC_TBL_END |
| 4232 | }; |
| 4233 | |
| 4234 | PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = { |
| 4235 | PSC_TBL_OR_LRDIMM3_IBT_C32 |
| 4236 | PSC_TBL_OR_LRDIMM3_IBT_G34 |
| 4237 | PSC_TBL_END |
| 4238 | }; |
| 4239 | |
| 4240 | PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = { |
| 4241 | PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 |
| 4242 | PSC_TBL_OR_UDIMM3_CLK_DIS_C32 |
| 4243 | PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 |
| 4244 | PSC_TBL_OR_UDIMM3_CLK_DIS_G34 |
| 4245 | PSC_TBL_OR_RDIMM3_CLK_DIS_C32 |
| 4246 | PSC_TBL_OR_RDIMM3_CLK_DIS_G34 |
| 4247 | PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 |
| 4248 | PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 |
| 4249 | PSC_TBL_OR_CKE_TRI |
| 4250 | PSC_TBL_OR_ODT_TRI_3D |
| 4251 | PSC_TBL_OR_ODT_TRI |
| 4252 | PSC_TBL_OR_LRDIMM3_ODT_TRI_3D |
| 4253 | PSC_TBL_OR_LRDIMM3_ODT_TRI |
| 4254 | PSC_TBL_OR_UDIMM3_CS_TRI |
| 4255 | PSC_TBL_OR_CS_TRI |
| 4256 | PSC_TBL_END |
| 4257 | }; |
| 4258 | |
| 4259 | PSC_TBL_ENTRY* memPSCTblWLSeedArrayOR[] = { |
| 4260 | PSC_TBL_OR_UDIMM3_WL_SEED_AM3 |
| 4261 | PSC_TBL_OR_UDIMM3_WL_SEED_C32 |
| 4262 | PSC_TBL_OR_UDIMM3_WL_SEED_G34 |
| 4263 | PSC_TBL_OR_RDIMM3_WL_SEED_AM3 |
| 4264 | PSC_TBL_OR_RDIMM3_WL_SEED_C32 |
| 4265 | PSC_TBL_OR_RDIMM3_WL_SEED_G34 |
| 4266 | PSC_TBL_OR_LRDIMM3_WL_SEED_AM3 |
| 4267 | PSC_TBL_OR_LRDIMM3_WL_SEED_C32 |
| 4268 | PSC_TBL_OR_LRDIMM3_WL_SEED_G34 |
| 4269 | PSC_TBL_END |
| 4270 | }; |
| 4271 | |
| 4272 | PSC_TBL_ENTRY* memPSCTblHWRxEnSeedArrayOR[] = { |
| 4273 | PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3 |
| 4274 | PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32 |
| 4275 | PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34 |
| 4276 | PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3 |
| 4277 | PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32 |
| 4278 | PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34 |
| 4279 | PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3 |
| 4280 | PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 |
| 4281 | PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 |
| 4282 | PSC_TBL_END |
| 4283 | }; |
| 4284 | |
| 4285 | MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = { |
| 4286 | (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR, |
| 4287 | (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR, |
| 4288 | (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR, |
| 4289 | (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR, |
| 4290 | (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR, |
| 4291 | (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR, |
| 4292 | (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR, |
| 4293 | (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR, |
| 4294 | (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR, |
| 4295 | NULL, |
| 4296 | NULL, |
| 4297 | (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR, |
| 4298 | (PSC_TBL_ENTRY **)&memPSCTblS2DArrayOR, |
| 4299 | (PSC_TBL_ENTRY **)&memPSCTblWLSeedArrayOR, |
| 4300 | (PSC_TBL_ENTRY **)&memPSCTblHWRxEnSeedArrayOR |
| 4301 | }; |
| 4302 | |
| 4303 | extern MEM_PSC_FLOW MemPGetMaxFreqSupported; |
| 4304 | #define PSC_FLOW_OR_MAX_FREQ MemPGetMaxFreqSupported |
| 4305 | extern MEM_PSC_FLOW MemPGetRttNomWr; |
| 4306 | #define PSC_FLOW_OR_DRAM_TERM MemPGetRttNomWr |
| 4307 | extern MEM_PSC_FLOW MemPGetODTPattern; |
| 4308 | #define PSC_FLOW_OR_ODT_PATTERN MemPGetODTPattern |
| 4309 | extern MEM_PSC_FLOW MemPGetSAO; |
| 4310 | #define PSC_FLOW_OR_SAO MemPGetSAO |
| 4311 | extern MEM_PSC_FLOW MemPGetMR0WrCL; |
| 4312 | #define PSC_FLOW_OR_MR0_WRCL MemPGetMR0WrCL |
| 4313 | extern MEM_PSC_FLOW MemPGetTrainingSeeds; |
| 4314 | #define PSC_FLOW_OR_SEED MemPGetTrainingSeeds |
| 4315 | #if OPTION_RDIMMS |
| 4316 | extern MEM_PSC_FLOW MemPGetRC2IBT; |
| 4317 | #define PSC_FLOW_OR_RC2_IBT MemPGetRC2IBT |
| 4318 | extern MEM_PSC_FLOW MemPGetRC10OpSpd; |
| 4319 | #define PSC_FLOW_OR_RC10_OPSPD MemPGetRC10OpSpd |
| 4320 | #endif |
| 4321 | #if OPTION_LRDIMMS |
| 4322 | extern MEM_PSC_FLOW MemPGetLRIBT; |
| 4323 | #define PSC_FLOW_OR_LR_IBT MemPGetLRIBT |
| 4324 | extern MEM_PSC_FLOW MemPGetLRNPR; |
| 4325 | #define PSC_FLOW_OR_LR_NPR MemPGetLRNPR |
| 4326 | extern MEM_PSC_FLOW MemPGetLRNLR; |
| 4327 | #define PSC_FLOW_OR_LR_NLR MemPGetLRNLR |
| 4328 | #endif |
| 4329 | #ifndef PSC_FLOW_OR_MAX_FREQ |
| 4330 | #define PSC_FLOW_OR_MAX_FREQ MEM_PSC_FLOW_DEFTRUE |
| 4331 | #endif |
| 4332 | #ifndef PSC_FLOW_OR_DRAM_TERM |
| 4333 | #define PSC_FLOW_OR_DRAM_TERM MEM_PSC_FLOW_DEFTRUE |
| 4334 | #endif |
| 4335 | #ifndef PSC_FLOW_OR_ODT_PATTERN |
| 4336 | #define PSC_FLOW_OR_ODT_PATTERN MEM_PSC_FLOW_DEFTRUE |
| 4337 | #endif |
| 4338 | #ifndef PSC_FLOW_OR_SAO |
| 4339 | #define PSC_FLOW_OR_SAO MEM_PSC_FLOW_DEFTRUE |
| 4340 | #endif |
| 4341 | #ifndef PSC_FLOW_OR_MR0_WRCL |
| 4342 | #define PSC_FLOW_OR_MR0_WRCL MEM_PSC_FLOW_DEFTRUE |
| 4343 | #endif |
| 4344 | #ifndef PSC_FLOW_OR_RC2_IBT |
| 4345 | #define PSC_FLOW_OR_RC2_IBT MEM_PSC_FLOW_DEFTRUE |
| 4346 | #endif |
| 4347 | #ifndef PSC_FLOW_OR_RC10_OPSPD |
| 4348 | #define PSC_FLOW_OR_RC10_OPSPD MEM_PSC_FLOW_DEFTRUE |
| 4349 | #endif |
| 4350 | #ifndef PSC_FLOW_OR_LR_IBT |
| 4351 | #define PSC_FLOW_OR_LR_IBT MEM_PSC_FLOW_DEFTRUE |
| 4352 | #endif |
| 4353 | #ifndef PSC_FLOW_OR_LR_NPR |
| 4354 | #define PSC_FLOW_OR_LR_NPR MEM_PSC_FLOW_DEFTRUE |
| 4355 | #endif |
| 4356 | #ifndef PSC_FLOW_OR_LR_NLR |
| 4357 | #define PSC_FLOW_OR_LR_NLR MEM_PSC_FLOW_DEFTRUE |
| 4358 | #endif |
| 4359 | #ifndef PSC_FLOW_OR_S2D |
| 4360 | #define PSC_FLOW_OR_S2D MEM_PSC_FLOW_DEFTRUE |
| 4361 | #endif |
| 4362 | #ifndef PSC_FLOW_OR_SEED |
| 4363 | #define PSC_FLOW_OR_SEED MEM_PSC_FLOW_DEFTRUE |
| 4364 | #endif |
| 4365 | |
| 4366 | MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = { |
| 4367 | &memPSCTblBlockOr, |
| 4368 | PSC_FLOW_OR_MAX_FREQ, |
| 4369 | PSC_FLOW_OR_DRAM_TERM, |
| 4370 | PSC_FLOW_OR_ODT_PATTERN, |
| 4371 | PSC_FLOW_OR_SAO, |
| 4372 | PSC_FLOW_OR_MR0_WRCL, |
| 4373 | PSC_FLOW_OR_RC2_IBT, |
| 4374 | PSC_FLOW_OR_RC10_OPSPD, |
| 4375 | PSC_FLOW_OR_LR_IBT, |
| 4376 | PSC_FLOW_OR_LR_NPR, |
| 4377 | PSC_FLOW_OR_LR_NLR, |
| 4378 | PSC_FLOW_OR_S2D, |
| 4379 | PSC_FLOW_OR_SEED |
| 4380 | }; |
| 4381 | #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR, |
| 4382 | #else |
| 4383 | #define MEM_PSC_FLOW_BLOCK_OR |
| 4384 | #endif |
| 4385 | |
| 4386 | #define PSC_TBL_TN_UDIMM3_S2D_FM2 |
| 4387 | #define PSC_TBL_TN_SODIMM3_S2D_FS1 |
| 4388 | #define PSC_TBL_TN_SODIMM3_S2D_FP2 |
| 4389 | #define PSC_TBL_TN_SODIMM3_S2D_FM2 |
| 4390 | #if OPTION_MEMCTLR_TN |
| 4391 | #if OPTION_FS1_SOCKET_SUPPORT |
| 4392 | extern PSC_TBL_ENTRY TNClkDisMapEntSOFS1; |
| 4393 | #define PSC_TBL_TN_CLK_DIS_FS1 &TNClkDisMapEntSOFS1, |
| 4394 | extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFS1; |
| 4395 | #define PSC_TBL_TN_ODT_TRI_FS1 &TNSODdr3ODTTriEntFS1, |
| 4396 | extern PSC_TBL_ENTRY TNSODdr3CSTriEntFS1; |
| 4397 | #define PSC_TBL_TN_CS_TRI_FS1 &TNSODdr3CSTriEntFS1, |
| 4398 | #endif |
| 4399 | #if OPTION_FM2_SOCKET_SUPPORT |
| 4400 | extern PSC_TBL_ENTRY TNClkDisMapEntUFM2; |
| 4401 | #define PSC_TBL_TN_CLK_DIS_FM2 &TNClkDisMapEntUFM2, |
| 4402 | extern PSC_TBL_ENTRY TNUDdr3ODTTriEntFM2; |
| 4403 | #define PSC_TBL_TN_ODT_TRI_FM2 &TNUDdr3ODTTriEntFM2, |
| 4404 | extern PSC_TBL_ENTRY TNUDdr3CSTriEntFM2; |
| 4405 | #define PSC_TBL_TN_CS_TRI_FM2 &TNUDdr3CSTriEntFM2, |
| 4406 | #endif |
| 4407 | #if OPTION_FP2_SOCKET_SUPPORT |
| 4408 | extern PSC_TBL_ENTRY TNClkDisMapEntSOFP2; |
| 4409 | #define PSC_TBL_TN_CLK_DIS_FP2 &TNClkDisMapEntSOFP2, |
| 4410 | extern PSC_TBL_ENTRY TNSODdr3ODTTriEntFP2; |
| 4411 | #define PSC_TBL_TN_ODT_TRI_FP2 &TNSODdr3ODTTriEntFP2, |
| 4412 | extern PSC_TBL_ENTRY TNSODdr3CSTriEntFP2; |
| 4413 | #define PSC_TBL_TN_CS_TRI_FP2 &TNSODdr3CSTriEntFP2, |
| 4414 | #endif |
| 4415 | #if OPTION_UDIMMS |
| 4416 | extern PSC_TBL_ENTRY TNMaxFreqTblEntU; |
| 4417 | #define PSC_TBL_TN_UDIMM3_MAX_FREQ &TNMaxFreqTblEntU, |
| 4418 | extern PSC_TBL_ENTRY TNDramTermTblEntU; |
| 4419 | #define PSC_TBL_TN_UDIMM3_DRAM_TERM &TNDramTermTblEntU, |
| 4420 | extern PSC_TBL_ENTRY TNSAOTblEntU3; |
| 4421 | #define PSC_TBL_TN_UDIMM3_SAO &TNSAOTblEntU3, |
| 4422 | #undef PSC_TBL_TN_UDIMM3_S2D_FM2 |
| 4423 | extern PSC_TBL_ENTRY ex891_1 ; |
| 4424 | #define PSC_TBL_TN_UDIMM3_S2D_FM2 &ex891_1 , |
| 4425 | #endif |
| 4426 | #if OPTION_SODIMMS |
| 4427 | #if OPTION_FS1_SOCKET_SUPPORT |
| 4428 | extern PSC_TBL_ENTRY TNSAOTblEntSO3; |
| 4429 | #define PSC_TBL_TN_SODIMM3_SAO &TNSAOTblEntSO3, |
| 4430 | extern PSC_TBL_ENTRY TNDramTermTblEntSO; |
| 4431 | #define PSC_TBL_TN_SODIMM3_DRAM_TERM &TNDramTermTblEntSO, |
| 4432 | extern PSC_TBL_ENTRY TNMaxFreqTblEntSO; |
| 4433 | #define PSC_TBL_TN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSO, |
| 4434 | #undef PSC_TBL_TN_SODIMM3_S2D_FS1 |
| 4435 | #define PSC_TBL_TN_SODIMM3_S2D_FS1 |
| 4436 | #endif |
| 4437 | #if OPTION_FM2_SOCKET_SUPPORT |
| 4438 | extern PSC_TBL_ENTRY TNSAOTblEntSO3; |
| 4439 | #define PSC_TBL_TN_SODIMM3_SAO &TNSAOTblEntSO3, |
| 4440 | extern PSC_TBL_ENTRY TNDramTermTblEntSO; |
| 4441 | #define PSC_TBL_TN_SODIMM3_DRAM_TERM &TNDramTermTblEntSO, |
| 4442 | extern PSC_TBL_ENTRY TNMaxFreqTblEntSO; |
| 4443 | #define PSC_TBL_TN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSO, |
| 4444 | #undef PSC_TBL_TN_SODIMM3_S2D_FM2 |
| 4445 | extern PSC_TBL_ENTRY ex891_1 ; |
| 4446 | #define PSC_TBL_TN_SODIMM3_S2D_FM2 &ex891_1 , |
| 4447 | #endif |
| 4448 | #if OPTION_FP2_SOCKET_SUPPORT |
| 4449 | extern PSC_TBL_ENTRY TNSAOTblEntSODWNSO3; |
| 4450 | #define PSC_TBL_TN_SODWN_SODIMM3_SAO &TNSAOTblEntSODWNSO3, |
| 4451 | extern PSC_TBL_ENTRY TNDramTermTblEntSODWNSO; |
| 4452 | #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM &TNDramTermTblEntSODWNSO, |
| 4453 | extern PSC_TBL_ENTRY TNMaxFreqTblEntSODWNSO; |
| 4454 | #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ &TNMaxFreqTblEntSODWNSO, |
| 4455 | #undef PSC_TBL_TN_SODIMM3_S2D_FP2 |
| 4456 | #define PSC_TBL_TN_SODIMM3_S2D_FP2 |
| 4457 | #endif |
| 4458 | #endif |
| 4459 | extern PSC_TBL_ENTRY TNMR0WrTblEntry; |
| 4460 | extern PSC_TBL_ENTRY TNMR0CLTblEntry; |
| 4461 | extern PSC_TBL_ENTRY TNDdr3CKETriEnt; |
| 4462 | extern PSC_TBL_ENTRY TNOdtPatTblEnt; |
| 4463 | |
| 4464 | |
| 4465 | #ifndef PSC_TBL_TN_SODIMM3_MAX_FREQ |
| 4466 | #define PSC_TBL_TN_SODIMM3_MAX_FREQ |
| 4467 | #endif |
| 4468 | #ifndef PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ |
| 4469 | #define PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ |
| 4470 | #endif |
| 4471 | #ifndef PSC_TBL_TN_UDIMM3_MAX_FREQ |
| 4472 | #define PSC_TBL_TN_UDIMM3_MAX_FREQ |
| 4473 | #endif |
| 4474 | #ifndef PSC_TBL_TN_UDIMM3_DRAM_TERM |
| 4475 | #define PSC_TBL_TN_UDIMM3_DRAM_TERM |
| 4476 | #endif |
| 4477 | #ifndef PSC_TBL_TN_SODIMM3_DRAM_TERM |
| 4478 | #define PSC_TBL_TN_SODIMM3_DRAM_TERM |
| 4479 | #endif |
| 4480 | #ifndef PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM |
| 4481 | #define PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM |
| 4482 | #endif |
| 4483 | #ifndef PSC_TBL_TN_SODIMM3_SAO |
| 4484 | #define PSC_TBL_TN_SODIMM3_SAO |
| 4485 | #endif |
| 4486 | #ifndef PSC_TBL_TN_SODWN_SODIMM3_SAO |
| 4487 | #define PSC_TBL_TN_SODWN_SODIMM3_SAO |
| 4488 | #endif |
| 4489 | #ifndef PSC_TBL_TN_UDIMM3_SAO |
| 4490 | #define PSC_TBL_TN_UDIMM3_SAO |
| 4491 | #endif |
| 4492 | #ifndef PSC_TBL_TN_CLK_DIS_FM2 |
| 4493 | #define PSC_TBL_TN_CLK_DIS_FM2 |
| 4494 | #endif |
| 4495 | #ifndef PSC_TBL_TN_ODT_TRI_FM2 |
| 4496 | #define PSC_TBL_TN_ODT_TRI_FM2 |
| 4497 | #endif |
| 4498 | #ifndef PSC_TBL_TN_CS_TRI_FM2 |
| 4499 | #define PSC_TBL_TN_CS_TRI_FM2 |
| 4500 | #endif |
| 4501 | #ifndef PSC_TBL_TN_CLK_DIS_FS1 |
| 4502 | #define PSC_TBL_TN_CLK_DIS_FS1 |
| 4503 | #endif |
| 4504 | #ifndef PSC_TBL_TN_ODT_TRI_FS1 |
| 4505 | #define PSC_TBL_TN_ODT_TRI_FS1 |
| 4506 | #endif |
| 4507 | #ifndef PSC_TBL_TN_CS_TRI_FS1 |
| 4508 | #define PSC_TBL_TN_CS_TRI_FS1 |
| 4509 | #endif |
| 4510 | #ifndef PSC_TBL_TN_CLK_DIS_FP2 |
| 4511 | #define PSC_TBL_TN_CLK_DIS_FP2 |
| 4512 | #endif |
| 4513 | #ifndef PSC_TBL_TN_ODT_TRI_FP2 |
| 4514 | #define PSC_TBL_TN_ODT_TRI_FP2 |
| 4515 | #endif |
| 4516 | #ifndef PSC_TBL_TN_CS_TRI_FP2 |
| 4517 | #define PSC_TBL_TN_CS_TRI_FP2 |
| 4518 | #endif |
| 4519 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4520 | PSC_TBL_ENTRY* CONST memPSCTblMaxFreqArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4521 | PSC_TBL_TN_SODIMM3_MAX_FREQ |
| 4522 | PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ |
| 4523 | PSC_TBL_TN_UDIMM3_MAX_FREQ |
| 4524 | PSC_TBL_END |
| 4525 | }; |
| 4526 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4527 | PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4528 | PSC_TBL_TN_UDIMM3_DRAM_TERM |
| 4529 | PSC_TBL_TN_SODIMM3_DRAM_TERM |
| 4530 | PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM |
| 4531 | PSC_TBL_END |
| 4532 | }; |
| 4533 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4534 | PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4535 | &TNOdtPatTblEnt, |
| 4536 | PSC_TBL_END |
| 4537 | }; |
| 4538 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4539 | PSC_TBL_ENTRY* CONST memPSCTblSAOArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4540 | PSC_TBL_TN_SODIMM3_SAO |
| 4541 | PSC_TBL_TN_SODWN_SODIMM3_SAO |
| 4542 | PSC_TBL_TN_UDIMM3_SAO |
| 4543 | PSC_TBL_END |
| 4544 | }; |
| 4545 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4546 | PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4547 | &TNMR0WrTblEntry, |
| 4548 | PSC_TBL_END |
| 4549 | }; |
| 4550 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4551 | PSC_TBL_ENTRY* CONST memPSCTblMR0CLArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4552 | &TNMR0CLTblEntry, |
| 4553 | PSC_TBL_END |
| 4554 | }; |
| 4555 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4556 | PSC_TBL_ENTRY* CONST memPSCTblGenArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4557 | &TNDdr3CKETriEnt, |
| 4558 | PSC_TBL_TN_CLK_DIS_FM2 |
| 4559 | PSC_TBL_TN_ODT_TRI_FM2 |
| 4560 | PSC_TBL_TN_CS_TRI_FM2 |
| 4561 | PSC_TBL_TN_CLK_DIS_FS1 |
| 4562 | PSC_TBL_TN_ODT_TRI_FS1 |
| 4563 | PSC_TBL_TN_CS_TRI_FS1 |
| 4564 | PSC_TBL_TN_CLK_DIS_FP2 |
| 4565 | PSC_TBL_TN_ODT_TRI_FP2 |
| 4566 | PSC_TBL_TN_CS_TRI_FP2 |
| 4567 | PSC_TBL_END |
| 4568 | }; |
| 4569 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4570 | PSC_TBL_ENTRY* CONST memPSCTblS2DArrayTN[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4571 | PSC_TBL_TN_UDIMM3_S2D_FM2 |
| 4572 | PSC_TBL_TN_SODIMM3_S2D_FS1 |
| 4573 | PSC_TBL_TN_SODIMM3_S2D_FP2 |
| 4574 | PSC_TBL_TN_SODIMM3_S2D_FM2 |
| 4575 | PSC_TBL_END |
| 4576 | }; |
| 4577 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4578 | CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4579 | (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN, |
| 4580 | (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN, |
| 4581 | (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN, |
| 4582 | (PSC_TBL_ENTRY **)&memPSCTblSAOArrayTN, |
| 4583 | (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayTN, |
| 4584 | (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayTN, |
| 4585 | NULL, |
| 4586 | NULL, |
| 4587 | NULL, |
| 4588 | NULL, |
| 4589 | NULL, |
| 4590 | (PSC_TBL_ENTRY **)&memPSCTblGenArrayTN, |
| 4591 | (PSC_TBL_ENTRY **)&memPSCTblS2DArrayTN, |
| 4592 | NULL, |
| 4593 | NULL |
| 4594 | }; |
| 4595 | |
| 4596 | extern MEM_PSC_FLOW MemPGetMaxFreqSupported; |
| 4597 | extern MEM_PSC_FLOW MemPGetRttNomWr; |
| 4598 | extern MEM_PSC_FLOW MemPGetODTPattern; |
| 4599 | extern MEM_PSC_FLOW MemPGetSAO; |
| 4600 | extern MEM_PSC_FLOW MemPGetMR0WrCL; |
| 4601 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4602 | CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4603 | &memPSCTblBlockTN, |
| 4604 | MemPGetMaxFreqSupported, |
| 4605 | MemPGetRttNomWr, |
| 4606 | MemPGetODTPattern, |
| 4607 | MemPGetSAO, |
| 4608 | MemPGetMR0WrCL, |
| 4609 | MEM_PSC_FLOW_DEFTRUE, |
| 4610 | MEM_PSC_FLOW_DEFTRUE, |
| 4611 | MEM_PSC_FLOW_DEFTRUE, |
| 4612 | MEM_PSC_FLOW_DEFTRUE, |
| 4613 | MEM_PSC_FLOW_DEFTRUE, |
| 4614 | MEM_PSC_FLOW_DEFTRUE, |
| 4615 | MEM_PSC_FLOW_DEFTRUE |
| 4616 | }; |
| 4617 | #define MEM_PSC_FLOW_BLOCK_TN &memPlatSpecFlowTN, |
| 4618 | #else |
| 4619 | #define MEM_PSC_FLOW_BLOCK_TN |
| 4620 | #endif |
| 4621 | |
| 4622 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4623 | CONST MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4624 | MEM_PSC_FLOW_BLOCK_OR |
| 4625 | MEM_PSC_FLOW_BLOCK_TN |
| 4626 | MEM_PSC_FLOW_BLOCK_END |
| 4627 | }; |
| 4628 | |
| 4629 | /*--------------------------------------------------------------------------------------------------- |
| 4630 | * |
| 4631 | * LRDIMM CONTROL |
| 4632 | * |
| 4633 | *--------------------------------------------------------------------------------------------------- |
| 4634 | */ |
| 4635 | #if (OPTION_LRDIMMS == TRUE) |
| Damien Zammit | 8c318cf | 2014-11-19 00:26:30 +1100 | [diff] [blame] | 4636 | #if (OPTION_MEMCTLR_OR == TRUE) |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4637 | #define MEM_TECH_FEATURE_LRDIMM_INIT &MemTLrdimmConstructor3 |
| Damien Zammit | 8c318cf | 2014-11-19 00:26:30 +1100 | [diff] [blame] | 4638 | #else //#if (OPTION_MEMCTLR_OR == FALSE) |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4639 | #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef |
| 4640 | #endif |
| 4641 | #else //#if (OPTION_LRDIMMS == FALSE) |
| 4642 | #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef |
| 4643 | #endif |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4644 | CONST MEM_TECH_LRDIMM memLrdimmSupported = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4645 | MEM_TECH_LRDIMM_STRUCT_VERSION, |
| 4646 | MEM_TECH_FEATURE_LRDIMM_INIT |
| 4647 | }; |
| 4648 | #else |
| 4649 | /*--------------------------------------------------------------------------------------------------- |
| 4650 | * MAIN FLOW CONTROL |
| 4651 | * |
| 4652 | * |
| 4653 | *--------------------------------------------------------------------------------------------------- |
| 4654 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4655 | MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4656 | NULL |
| 4657 | }; |
| 4658 | /*--------------------------------------------------------------------------------------------------- |
| 4659 | * NB TRAINING FLOW CONTROL |
| 4660 | * |
| 4661 | * |
| 4662 | *--------------------------------------------------------------------------------------------------- |
| 4663 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4664 | OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control |
| Joe Moore | a608dd8 | 2020-01-04 13:33:34 -0700 | [diff] [blame] | 4665 | NULL, |
| 4666 | NULL, |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4667 | }; |
| 4668 | /*--------------------------------------------------------------------------------------------------- |
| 4669 | * DEFAULT TECHNOLOGY BLOCK |
| 4670 | * |
| 4671 | * |
| 4672 | *--------------------------------------------------------------------------------------------------- |
| 4673 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4674 | MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4675 | NULL |
| 4676 | }; |
| 4677 | |
| 4678 | /*--------------------------------------------------------------------------------------------------- |
| 4679 | * DEFAULT TECHNOLOGY MAP |
| 4680 | * |
| 4681 | * |
| 4682 | *--------------------------------------------------------------------------------------------------- |
| 4683 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4684 | CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4685 | |
| 4686 | /*--------------------------------------------------------------------------------------------------- |
| 4687 | * DEFAULT MAIN FEATURE BLOCK |
| 4688 | *--------------------------------------------------------------------------------------------------- |
| 4689 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4690 | CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { |
| Kyösti Mälkki | defbdcf | 2016-04-19 15:17:50 +0300 | [diff] [blame] | 4691 | 0 |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4692 | }; |
| 4693 | |
| 4694 | /*--------------------------------------------------------------------------------------------------- |
| 4695 | * DEFAULT NORTHBRIDGE SUPPORT LIST |
| 4696 | * |
| 4697 | * |
| 4698 | *--------------------------------------------------------------------------------------------------- |
| 4699 | */ |
| 4700 | #if (OPTION_MEMCTLR_DR == TRUE) |
| 4701 | #undef MEM_NB_SUPPORT_DR |
| 4702 | #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR }, |
| 4703 | #endif |
| 4704 | #if (OPTION_MEMCTLR_RB == TRUE) |
| 4705 | #undef MEM_NB_SUPPORT_RB |
| 4706 | #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB }, |
| 4707 | #endif |
| 4708 | #if (OPTION_MEMCTLR_DA == TRUE) |
| 4709 | #undef MEM_NB_SUPPORT_DA |
| 4710 | #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA }, |
| 4711 | #endif |
| 4712 | #if (OPTION_MEMCTLR_PH == TRUE) |
| 4713 | #undef MEM_NB_SUPPORT_PH |
| 4714 | #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH }, |
| 4715 | #endif |
| 4716 | #if (OPTION_MEMCTLR_HY == TRUE) |
| 4717 | #undef MEM_NB_SUPPORT_HY |
| 4718 | #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY }, |
| 4719 | #endif |
| 4720 | #if (OPTION_MEMCTLR_C32 == TRUE) |
| 4721 | #undef MEM_NB_SUPPORT_C32 |
| 4722 | #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 }, |
| 4723 | #endif |
| 4724 | #if (OPTION_MEMCTLR_LN == TRUE) |
| 4725 | #undef MEM_NB_SUPPORT_LN |
| 4726 | #define MEM_NB_SUPPORT_LN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_LN, MEM_IDENDIMM_LN }, |
| 4727 | #endif |
| 4728 | #if (OPTION_MEMCTLR_ON == TRUE) |
| 4729 | #undef MEM_NB_SUPPORT_ON |
| 4730 | #define MEM_NB_SUPPORT_ON { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_ON, MEM_IDENDIMM_ON }, |
| 4731 | #endif |
| 4732 | #if (OPTION_MEMCTLR_OR == TRUE) |
| 4733 | #undef MEM_NB_SUPPORT_OR |
| 4734 | #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR }, |
| 4735 | #endif |
| 4736 | #if (OPTION_MEMCTLR_TN == TRUE) |
| 4737 | #undef MEM_NB_SUPPORT_TN |
| 4738 | #define MEM_NB_SUPPORT_TN { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_TN, MEM_IDENDIMM_TN }, |
| 4739 | #endif |
| 4740 | /*--------------------------------------------------------------------------------------------------- |
| 4741 | * DEFAULT Technology Training |
| 4742 | * |
| 4743 | * |
| 4744 | *--------------------------------------------------------------------------------------------------- |
| 4745 | */ |
| 4746 | #if OPTION_DDR2 |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4747 | CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { |
| Kyösti Mälkki | defbdcf | 2016-04-19 15:17:50 +0300 | [diff] [blame] | 4748 | 0 |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4749 | }; |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4750 | CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { |
| Stefan Reinauer | 8e6bb80 | 2017-06-25 05:46:56 +0200 | [diff] [blame] | 4751 | { 0 } |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4752 | }; |
| 4753 | #endif |
| 4754 | #if OPTION_DDR3 |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4755 | CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { |
| Kyösti Mälkki | defbdcf | 2016-04-19 15:17:50 +0300 | [diff] [blame] | 4756 | 0 |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4757 | }; |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4758 | CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { |
| Stefan Reinauer | 8e6bb80 | 2017-06-25 05:46:56 +0200 | [diff] [blame] | 4759 | { 0 } |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4760 | }; |
| 4761 | #endif |
| 4762 | /*--------------------------------------------------------------------------------------------------- |
| 4763 | * DEFAULT Platform Specific list |
| 4764 | * |
| 4765 | * |
| 4766 | *--------------------------------------------------------------------------------------------------- |
| 4767 | */ |
| 4768 | #if (OPTION_MEMCTLR_DR == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4769 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4770 | NULL |
| 4771 | }; |
| 4772 | #endif |
| 4773 | #if (OPTION_MEMCTLR_RB == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4774 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4775 | NULL |
| 4776 | }; |
| 4777 | #endif |
| 4778 | #if (OPTION_MEMCTLR_DA == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4779 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4780 | NULL |
| 4781 | }; |
| 4782 | #endif |
| 4783 | #if (OPTION_MEMCTLR_Ni == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4784 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4785 | NULL |
| 4786 | }; |
| 4787 | #endif |
| 4788 | #if (OPTION_MEMCTLR_PH == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4789 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4790 | NULL |
| 4791 | }; |
| 4792 | #endif |
| 4793 | #if (OPTION_MEMCTLR_LN == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4794 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4795 | NULL |
| 4796 | }; |
| 4797 | #endif |
| 4798 | #if (OPTION_MEMCTLR_HY == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4799 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4800 | NULL |
| 4801 | }; |
| 4802 | #endif |
| 4803 | #if (OPTION_MEMCTLR_OR == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4804 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4805 | NULL |
| 4806 | }; |
| 4807 | #endif |
| 4808 | #if (OPTION_MEMCTLR_C32 == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4809 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4810 | NULL |
| 4811 | }; |
| 4812 | #endif |
| 4813 | #if (OPTION_MEMCTLR_ON == TRUE) |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4814 | MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4815 | NULL |
| 4816 | }; |
| 4817 | #endif |
| 4818 | /*---------------------------------------------------------------------- |
| 4819 | * DEFAULT PSCFG DEFINITIONS |
| 4820 | * |
| 4821 | *---------------------------------------------------------------------- |
| 4822 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4823 | MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4824 | NULL |
| 4825 | }; |
| 4826 | |
| 4827 | /*---------------------------------------------------------------------- |
| 4828 | * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION |
| 4829 | * |
| 4830 | *---------------------------------------------------------------------- |
| 4831 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4832 | MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4833 | NULL |
| 4834 | }; |
| 4835 | |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4836 | CONST MEM_TECH_LRDIMM memLrdimmSupported = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4837 | MEM_TECH_LRDIMM_STRUCT_VERSION, |
| 4838 | NULL |
| 4839 | }; |
| 4840 | #endif |
| 4841 | |
| 4842 | /*--------------------------------------------------------------------------------------------------- |
| 4843 | * NORTHBRIDGE SUPPORT LIST |
| 4844 | * |
| 4845 | * |
| 4846 | *--------------------------------------------------------------------------------------------------- |
| 4847 | */ |
| Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 4848 | CONST MEM_NB_SUPPORT memNBInstalled[] = { |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 4849 | MEM_NB_SUPPORT_RB |
| 4850 | MEM_NB_SUPPORT_DA |
| 4851 | MEM_NB_SUPPORT_Ni |
| 4852 | MEM_NB_SUPPORT_PH |
| 4853 | MEM_NB_SUPPORT_HY |
| 4854 | MEM_NB_SUPPORT_LN |
| 4855 | MEM_NB_SUPPORT_OR |
| 4856 | MEM_NB_SUPPORT_C32 |
| 4857 | MEM_NB_SUPPORT_ON |
| 4858 | MEM_NB_SUPPORT_TN |
| 4859 | MEM_NB_SUPPORT_END |
| 4860 | }; |
| 4861 | |
| 4862 | #endif // _OPTION_MEMORY_INSTALL_H_ |