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review.coreboot.org / coreboot / 8d3640d22610eeb9a21c803d75c698e681a1dc62 / . / src / vendorcode / amd / agesa / f15tn / Config / OptionFamily15hInstall.h
blob: 977c82c57e964a06837c40c3dbe1dc8dea81070b [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Install of family 15h support
6 *
7 * This file generates the defaults tables for family 15h processors.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Core
12 * @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $
13 */
14/*****************************************************************************
15 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]16 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
17 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]18 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]29 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]40 *
41 ***************************************************************************/
42
43#ifndef _OPTION_FAMILY_15H_INSTALL_H_
44#define _OPTION_FAMILY_15H_INSTALL_H_
45
Alexandru Gagniuc986349d2014-03-29 16:52:46 -0500[diff] [blame]46#include <Proc/CPU/cpuFamilyTranslation.h>
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]47
48/*
49 * Pull in family specific services based on entry point
50 */
51
52/*
53 * Common Family 15h routines
54 */
55extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
56
57/*
58 * Install family 15h model 0 support
59 */
60#ifdef OPTION_FAMILY15H_OR
61 #if OPTION_FAMILY15H_OR == TRUE
62 extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
63 extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
64 extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
65 extern F_CPU_DISABLE_PSTATE F15DisablePstate;
66 extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
67 extern F_CPU_GET_TSC_RATE F15GetTscRate;
68 extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
69 extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
70 extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
71 extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
72 extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
73 extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
74 extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
75 extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
76 extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
77 extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
78 extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
79 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
80 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
81 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
82 extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
83 extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
84 extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
85 extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
86 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
87 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
88 extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
89 extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
90 extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
91 extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
92 extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
93 extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
94 extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
95 extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
96 extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
97 extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
98 extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
99 extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
100 extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
101
102 /**
103 * Core Pair and core pair primary determination table.
104 *
105 * The two fields from the core pair hardware register can be used to determine whether
106 * even number cores are primary or all cores are primary. It can be extended if it is
107 * decided to have other configs as well. The other logically possible value sets are BitMapMapping,
108 * but they are currently not supported by the processor.
109 */
110 CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
111 {
112 {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
113 {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
114 {7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores
115 {0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores
116 {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
117 {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
118 {7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core
119 {0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core
120 {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
121 };
122
123
124 #if USES_REGISTER_TABLES == TRUE
125 CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
126 {
127 #if BASE_FAMILY_PCI == TRUE
128 &F15PciRegisterTable,
129 #endif
130 #if MODEL_SPECIFIC_PCI == TRUE
131 &F15OrMultiLinkPciRegisterTable,
132 &F15OrSingleLinkPciRegisterTable,
133 #endif
134 #if MODEL_SPECIFIC_PCI == TRUE
135 &F15OrPciRegisterTable,
136 #if OPTION_EARLY_SAMPLES == TRUE
137 &F15OrEarlySamplePciRegisterTable,
138 #endif
139 #endif
140 #if BASE_FAMILY_MSR == TRUE
141 &F15MsrRegisterTable,
142 #endif
143 #if MODEL_SPECIFIC_MSR == TRUE
144 &F15OrMsrRegisterTable,
145 #if OPTION_EARLY_SAMPLES == TRUE
146 &F15OrEarlySampleMsrRegisterTable,
147 #endif
148 #endif
149 #if MODEL_SPECIFIC_MSR == TRUE
150 &F15OrSharedMsrRegisterTable,
151 &F15OrSharedMsrCuRegisterTable,
152 &F15OrSharedMsrWorkaroundTable,
153 #if OPTION_EARLY_SAMPLES == TRUE
154 &F15OrEarlySampleSharedMsrRegisterTable,
155 &F15OrEarlySampleSharedMsrWorkaroundTable,
156 #endif
157 #endif
158 #if MODEL_SPECIFIC_HT_PCI == TRUE
159 &F15OrHtPhyRegisterTable,
160 #endif
161 #if BASE_FAMILY_WORKAROUNDS == TRUE
162 &F15OrWorkaroundsTable,
163 #if OPTION_EARLY_SAMPLES == TRUE
164 &F15OrEarlySampleWorkaroundsTable,
165 #endif
166 #endif
167 // the end.
168 NULL
169 };
170 #endif
171
172 #if USES_REGISTER_TABLES == TRUE
173 CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
174 {
175 {MsrRegister, SetRegisterForMsrEntry},
176 {PciRegister, SetRegisterForPciEntry},
177 {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
178 {HtPhyRegister, SetRegisterForHtPhyEntry},
179 {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
180 {DeemphasisRegister, SetRegisterForDeemphasisEntry},
181 {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
182 {ProfileFixup, SetRegisterForPerformanceProfileEntry},
183 {HtHostPciRegister, SetRegisterForHtHostEntry},
184 {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
185 {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
186 {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
187 {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
188 {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
189 {TokenPciRegister, SetRegisterForTokenPciEntry},
190 {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
191 {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
192 {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
193 // End
194 {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
195 };
196 #endif
197
198 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
199 {
200 0,
201 #if DISABLE_PSTATE == TRUE
202 F15DisablePstate,
203 #else
204 (PF_CPU_DISABLE_PSTATE) CommonAssert,
205 #endif
206 #if TRANSITION_PSTATE == TRUE
207 F15TransitionPstate,
208 #else
209 (PF_CPU_TRANSITION_PSTATE) CommonAssert,
210 #endif
211 #if PROC_IDD_MAX == TRUE
212 F15OrGetProcIddMax,
213 #else
214 (PF_CPU_GET_IDD_MAX) CommonAssert,
215 #endif
216 #if GET_TSC_RATE == TRUE
217 F15GetTscRate,
218 #else
219 (PF_CPU_GET_TSC_RATE) CommonAssert,
220 #endif
221 #if GET_NB_FREQ == TRUE
222 F15OrGetCurrentNbFrequency,
223 #else
224 (PF_CPU_GET_NB_FREQ) CommonAssert,
225 #endif
226 #if GET_NB_FREQ == TRUE
227 F15OrGetMinMaxNbFrequency,
228 #else
229 (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
230 #endif
231 #if GET_NB_FREQ == TRUE
232 F15OrGetNbPstateInfo,
233 #else
234 (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
235 #endif
236 #if IS_NBCOF_INIT_NEEDED == TRUE
237 F15CommonGetNbCofVidUpdate,
238 #else
239 (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
240 #endif
241 #if GET_NB_IDD_MAX == TRUE
242 (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
243 #else
244 (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
245 #endif
246 #if AP_INITIAL_LAUNCH == TRUE
247 F15LaunchApCore,
248 #else
249 (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
250 #endif
251 #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
252 F15OrGetNumberOfPhysicalCores,
253 #else
254 (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
255 #endif
256 #if GET_AP_MAILBOX_FROM_HW == TRUE
257 F15OrGetApMailboxFromHardware,
258 #else
259 (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
260 #endif
261 #if SET_AP_CORE_NUMBER == TRUE
262 F15OrSetApCoreNumber,
263 #else
264 (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
265 #endif
266 #if GET_AP_CORE_NUMBER == TRUE
267 F15OrGetApCoreNumber,
268 #else
269 (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
270 #endif
271 #if TRANSFER_AP_CORE_NUMBER == TRUE
272 F15OrTransferApCoreNumber,
273 #else
274 (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
275 #endif
276 #if ID_POSITION_INITIAL_APICID == TRUE
277 F15CpuAmdCoreIdPositionInInitialApicId,
278 #else
279 (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
280 #endif
281 #if SAVE_FEATURES == TRUE
282 // F15OrSaveFeatures,
283 (PF_CPU_SAVE_FEATURES) CommonVoid,
284 #else
285 (PF_CPU_SAVE_FEATURES) CommonAssert,
286 #endif
287 #if WRITE_FEATURES == TRUE
288 // F15OrWriteFeatures,
289 (PF_CPU_WRITE_FEATURES) CommonVoid,
290 #else
291 (PF_CPU_WRITE_FEATURES) CommonAssert,
292 #endif
293 #if SET_WARM_RESET_FLAG == TRUE
294 F15SetAgesaWarmResetFlag,
295 #else
296 (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
297 #endif
298 #if GET_WARM_RESET_FLAG == TRUE
299 F15GetAgesaWarmResetFlag,
300 #else
301 (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
302 #endif
303 #if BRAND_STRING1 == TRUE
304 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
305 #else
306 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
307 #endif
308 #if BRAND_STRING2 == TRUE
309 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
310 #else
311 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
312 #endif
313 #if GET_PATCHES == TRUE
314 GetF15OrMicroCodePatchesStruct,
315 #else
316 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
317 #endif
318 #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
319 GetF15OrMicrocodeEquivalenceTable,
320 #else
321 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
322 #endif
323 #if GET_CACHE_INFO == TRUE
324 GetF15CacheInfo,
325 #else
326 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
327 #endif
328 #if GET_SYSTEM_PM_TABLE == TRUE
329 GetF15OrSysPmTable,
330 #else
331 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
332 #endif
333 #if GET_WHEA_INIT == TRUE
334 GetF15WheaInitData,
335 #else
336 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
337 #endif
338 #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
339 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
340 #else
341 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
342 #endif
343 #if IS_NB_PSTATE_ENABLED == TRUE
344 F15IsNbPstateEnabled,
345 #else
346 (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
347 #endif
348 #if (BASE_FAMILY_HT_PCI == TRUE)
349 F15NextLinkHasHtPhyFeats,
350 #else
351 (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
352 #endif
353 #if (BASE_FAMILY_HT_PCI == TRUE)
354 F15SetHtPhyRegister,
355 #else
356 (PF_SET_HT_PHY_REGISTER) CommonAssert,
357 #endif
358 #if BASE_FAMILY_PCI == TRUE
359 F15GetNextHtLinkFeatures,
360 #else
361 (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
362 #endif
363 #if USES_REGISTER_TABLES == TRUE
364 (REGISTER_TABLE **) F15OrRegisterTables,
365 #else
366 NULL,
367 #endif
368 #if USES_REGISTER_TABLES == TRUE
369 (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
370 #else
371 NULL,
372 #endif
373 #if MODEL_SPECIFIC_HT_PCI == TRUE
374 (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
375 #else
376 NULL,
377 #endif
378 (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
379 InitCacheEnabled,
380 #if AGESA_ENTRY_INIT_EARLY == TRUE
381 GetF15OrEarlyInitOnCoreTable
382 #else
383 (PF_GET_EARLY_INIT_TABLE) CommonVoid
384 #endif
385 };
386
387 #define OR_SOCKETS 8
388 #define OR_MODULES 2
389 #define OR_RECOVERY_SOCKETS 1
390 #define OR_RECOVERY_MODULES 1
391 extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
392 #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
393 #ifndef ADVCFG_PLATFORM_SOCKETS
394 #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
395 #else
396 #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
397 #undef ADVCFG_PLATFORM_SOCKETS
398 #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
399 #endif
400 #endif
401 #ifndef ADVCFG_PLATFORM_MODULES
402 #define ADVCFG_PLATFORM_MODULES OR_MODULES
403 #else
404 #if ADVCFG_PLATFORM_MODULES < OR_MODULES
405 #undef ADVCFG_PLATFORM_MODULES
406 #define ADVCFG_PLATFORM_MODULES OR_MODULES
407 #endif
408 #endif
409
410 #if GET_PATCHES == TRUE
411 #define F15_OR_UCODE_17_UNENC
412 #define F15_OR_UCODE_11F_UNENC
413 #define F15_OR_UCODE_425
414 #define F15_OR_UCODE_509
415 #define F15_OR_UCODE_602
416
417 #if AGESA_ENTRY_INIT_EARLY == TRUE
418 extern CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000602 [];
419 #undef F15_OR_UCODE_602
420 #define F15_OR_UCODE_602 CpuF15OrMicrocodePatch06000602,
421 #endif
422
423 CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] =
424 {
425 F15_OR_UCODE_602
426 F15_OR_UCODE_509
427 F15_OR_UCODE_425
428 F15_OR_UCODE_11F_UNENC
429 F15_OR_UCODE_17_UNENC
430 NULL
431 };
432
433 CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
434 #endif
435
436 #if OPTION_EARLY_SAMPLES == TRUE
437 extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart;
438 extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd;
439 extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch;
440 extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded;
441
442 CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
443 {
444 F15OrEarlySamplesAvoidNbCyclesStart,
445 F15OrEarlySamplesAvoidNbCyclesEnd,
446 F15OrEarlySamplesLoadMicrocodePatch,
447 F15OrEarlySamplesAfterPatchLoaded
448 };
449 #else
450 CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
451 {
452 (PF_F15_OR_ES_AVOID_NB_CYCLES_START) CommonVoid,
453 (PF_F15_OR_ES_AVOID_NB_CYCLES_END) CommonVoid,
454 (PF_F15_OR_ES_LOAD_MCU_PATCH) LoadMicrocodePatch,
455 (PF_F15_OR_ES_AFTER_PATCH_LOADED) CommonVoid
456 };
457 #endif
458
459 #if OPTION_EARLY_SAMPLES == TRUE
460 extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
461
462 CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
463 {
464 #if AGESA_ENTRY_INIT_EARLY == TRUE
465 F15OrHtcInitEarlySampleHook,
466 #else
467 (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
468 #endif
469 };
470 #else
471 CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
472 {
473 #if AGESA_ENTRY_INIT_EARLY == TRUE
474 (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
475 #else
476 (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
477 #endif
478 };
479 #endif
480
481 #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
482
483 #else // OPTION_FAMILY15H_OR == TRUE
484 #define OPT_F15_OR_CPU
485 #define OPT_F15_OR_ID
486 #endif // OPTION_FAMILY15H_OR == TRUE
487#else // defined (OPTION_FAMILY15H_OR)
488 #define OPT_F15_OR_CPU
489 #define OPT_F15_OR_ID
490#endif // defined (OPTION_FAMILY15H_OR)
491
492
493/*
494 * Install family 15h model 10h - 1Fh support
495 */
496#ifdef OPTION_FAMILY15H_TN
497 #if OPTION_FAMILY15H_TN == TRUE
498 extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax;
499 extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo;
500 extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
501 extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax;
502 extern F_CPU_DISABLE_PSTATE F15DisablePstate;
503 extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
504 extern F_CPU_GET_TSC_RATE F15GetTscRate;
505 extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency;
506 extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency;
507 extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
508 extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores;
509 extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware;
510 extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber;
511 extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
512 extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
513 extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
514 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
515 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable;
516 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
517 extern F_IS_NB_PSTATE_ENABLED F15TnIsNbPstateEnabled;
518 extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister;
519 extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
520 extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
521 extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
522 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct;
523 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable;
524 extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable;
525 extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable;
526 extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable;
527 extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable;
528 extern CONST REGISTER_TABLE ROMDATA F15TnMsrWorkaroundTable;
529 extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable;
530 extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable;
531 extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable;
532 extern CONST REGISTER_TABLE ROMDATA F15TnPerNodeMsrWorkaroundTable;
533 extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
534 extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
535
536 /**
537 * Core Pair and core pair primary determination table.
538 *
539 * The two fields from the core pair hardware register can be used to determine whether
540 * even number cores are primary or all cores are primary. It can be extended if it is
541 * decided to have other configs as well. The other logically possible value sets are BitMapMapping,
542 * but they are currently not supported by the processor.
543 */
544 CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] =
545 {
546 {1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
547 {3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
548 {1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
549 {3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
550 {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
551 };
552
553
554 #if USES_REGISTER_TABLES == TRUE
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame^]555 CONST REGISTER_TABLE ROMDATA * CONST F15TnRegisterTables[] =
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]556 {
557 #if BASE_FAMILY_PCI == TRUE
558 &F15PciRegisterTable,
559 #endif
560 #if MODEL_SPECIFIC_PCI == TRUE
561 &F15TnPciRegisterTable,
562 &F15TnPciWorkaroundTable,
563 #endif
564 #if BASE_FAMILY_MSR == TRUE
565 &F15MsrRegisterTable,
566 #endif
567 #if MODEL_SPECIFIC_MSR == TRUE
568 &F15TnMsrRegisterTable,
569 &F15TnMsrWorkaroundTable,
570 &F15TnSharedMsrRegisterTable,
571 &F15TnSharedMsrCuRegisterTable,
572 &F15TnSharedMsrWorkaroundTable,
573 &F15TnPerNodeMsrWorkaroundTable,
574 #endif
575 // the end.
576 NULL
577 };
578 #endif
579
580 #if USES_REGISTER_TABLES == TRUE
581 CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] =
582 {
583 {MsrRegister, SetRegisterForMsrEntry},
584 {PciRegister, SetRegisterForPciEntry},
585 {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
586 {ProfileFixup, SetRegisterForPerformanceProfileEntry},
587 {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
588 {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
589 {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
590 {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
591 // End
592 {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
593 };
594 #endif
595
596 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices =
597 {
598 0,
599 #if DISABLE_PSTATE == TRUE
600 F15DisablePstate,
601 #else
602 (PF_CPU_DISABLE_PSTATE) CommonAssert,
603 #endif
604 #if TRANSITION_PSTATE == TRUE
605 F15TransitionPstate,
606 #else
607 (PF_CPU_TRANSITION_PSTATE) CommonAssert,
608 #endif
609 #if PROC_IDD_MAX == TRUE
610 F15TnGetProcIddMax,
611 #else
612 (PF_CPU_GET_IDD_MAX) CommonAssert,
613 #endif
614 #if GET_TSC_RATE == TRUE
615 F15GetTscRate,
616 #else
617 (PF_CPU_GET_TSC_RATE) CommonAssert,
618 #endif
619 #if GET_NB_FREQ == TRUE
620 F15TnGetCurrentNbFrequency,
621 #else
622 (PF_CPU_GET_NB_FREQ) CommonAssert,
623 #endif
624 #if GET_NB_FREQ == TRUE
625 F15TnGetMinMaxNbFrequency,
626 #else
627 (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
628 #endif
629 #if GET_NB_FREQ == TRUE
630 F15TnGetNbPstateInfo,
631 #else
632 (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
633 #endif
634 #if IS_NBCOF_INIT_NEEDED == TRUE
635 F15CommonGetNbCofVidUpdate,
636 #else
637 (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
638 #endif
639 #if GET_NB_IDD_MAX == TRUE
640 (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax,
641 #else
642 (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
643 #endif
644 #if AP_INITIAL_LAUNCH == TRUE
645 F15LaunchApCore,
646 #else
647 (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
648 #endif
649 #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
650 F15TnGetNumberOfPhysicalCores,
651 #else
652 (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
653 #endif
654 #if GET_AP_MAILBOX_FROM_HW == TRUE
655 F15TnGetApMailboxFromHardware,
656 #else
657 (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
658 #endif
659 #if SET_AP_CORE_NUMBER == TRUE
660 (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
661 #else
662 (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
663 #endif
664 #if GET_AP_CORE_NUMBER == TRUE
665 F15TnGetApCoreNumber,
666 #else
667 (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
668 #endif
669 #if TRANSFER_AP_CORE_NUMBER == TRUE
670 (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
671 #else
672 (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
673 #endif
674 #if ID_POSITION_INITIAL_APICID == TRUE
675 F15CpuAmdCoreIdPositionInInitialApicId,
676 #else
677 (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
678 #endif
679 #if SAVE_FEATURES == TRUE
680 (PF_CPU_SAVE_FEATURES) CommonVoid,
681 #else
682 (PF_CPU_SAVE_FEATURES) CommonAssert,
683 #endif
684 #if WRITE_FEATURES == TRUE
685 (PF_CPU_WRITE_FEATURES) CommonVoid,
686 #else
687 (PF_CPU_WRITE_FEATURES) CommonAssert,
688 #endif
689 #if SET_WARM_RESET_FLAG == TRUE
690 F15SetAgesaWarmResetFlag,
691 #else
692 (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
693 #endif
694 #if GET_WARM_RESET_FLAG == TRUE
695 F15GetAgesaWarmResetFlag,
696 #else
697 (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
698 #endif
699 #if BRAND_STRING1 == TRUE
700 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
701 #else
702 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
703 #endif
704 #if BRAND_STRING2 == TRUE
705 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
706 #else
707 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
708 #endif
709 #if GET_PATCHES == TRUE
710 GetF15TnMicroCodePatchesStruct,
711 #else
712 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
713 #endif
714 #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
715 GetF15TnMicrocodeEquivalenceTable,
716 #else
717 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
718 #endif
719 #if GET_CACHE_INFO == TRUE
720 GetF15CacheInfo,
721 #else
722 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
723 #endif
724 #if GET_SYSTEM_PM_TABLE == TRUE
725 GetF15TnSysPmTable,
726 #else
727 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
728 #endif
729 #if GET_WHEA_INIT == TRUE
730 GetF15WheaInitData,
731 #else
732 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
733 #endif
734 #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
735 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
736 #else
737 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
738 #endif
739 #if IS_NB_PSTATE_ENABLED == TRUE
740 F15TnIsNbPstateEnabled,
741 #else
742 (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
743 #endif
744 #if (BASE_FAMILY_HT_PCI == TRUE)
745 F15NextLinkHasHtPhyFeats,
746 #else
747 (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
748 #endif
749 #if (BASE_FAMILY_HT_PCI == TRUE)
750 F15SetHtPhyRegister,
751 #else
752 (PF_SET_HT_PHY_REGISTER) CommonAssert,
753 #endif
754 #if BASE_FAMILY_PCI == TRUE
755 F15GetNextHtLinkFeatures,
756 #else
757 (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
758 #endif
759 #if USES_REGISTER_TABLES == TRUE
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame^]760 (CONST REGISTER_TABLE **) F15TnRegisterTables,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]761 #else
762 NULL,
763 #endif
764 #if USES_REGISTER_TABLES == TRUE
765 (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors,
766 #else
767 NULL,
768 #endif
769 #if MODEL_SPECIFIC_HT_PCI == TRUE
770 NULL,
771 #else
772 NULL,
773 #endif
774 (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping,
775 InitCacheEnabled,
776 #if AGESA_ENTRY_INIT_EARLY == TRUE
777 GetF15TnEarlyInitOnCoreTable
778 #else
779 (PF_GET_EARLY_INIT_TABLE) CommonVoid
780 #endif
781 };
782
783 #define TN_SOCKETS 1
784 #define TN_MODULES 1
785 #define TN_RECOVERY_SOCKETS 1
786 #define TN_RECOVERY_MODULES 1
787 extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev;
788 #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev,
789 #ifndef ADVCFG_PLATFORM_SOCKETS
790 #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
791 #else
792 #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS
793 #undef ADVCFG_PLATFORM_SOCKETS
794 #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
795 #endif
796 #endif
797 #ifndef ADVCFG_PLATFORM_MODULES
798 #define ADVCFG_PLATFORM_MODULES TN_MODULES
799 #else
800 #if ADVCFG_PLATFORM_MODULES < TN_MODULES
801 #undef ADVCFG_PLATFORM_MODULES
802 #define ADVCFG_PLATFORM_MODULES TN_MODULES
803 #endif
804 #endif
805
806 #if GET_PATCHES == TRUE
807 #define F15_TN_UCODE_10F
808 #define F15_TN_UCODE_0E
809
810 #if AGESA_ENTRY_INIT_EARLY == TRUE
Mike Banon334e8362018-08-23 00:50:08 +0300[diff] [blame]811 extern CONST UINT8 ROMDATA CpuF15TnMicrocodePatch0600111F_Enc [];
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]812 #undef F15_TN_UCODE_10F
Mike Banon334e8362018-08-23 00:50:08 +0300[diff] [blame]813 #define F15_TN_UCODE_10F CpuF15TnMicrocodePatch0600111F_Enc,
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]814
815 #endif
816
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame^]817 CONST UINT8 ROMDATA * CONST CpuF15TnMicroCodePatchArray[] =
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]818 {
819 F15_TN_UCODE_10F
820 F15_TN_UCODE_0E
821 NULL
822 };
823
824 CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1);
825 #endif
826
827
828
829 #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices},
830
831 #else // OPTION_FAMILY15H_TN == TRUE
832 #define OPT_F15_TN_CPU
833 #define OPT_F15_TN_ID
834 #endif // OPTION_FAMILY15H_TN == TRUE
835#else // defined (OPTION_FAMILY15H_TN)
836 #define OPT_F15_TN_CPU
837 #define OPT_F15_TN_ID
838#endif // defined (OPTION_FAMILY15H_TN)
839
840
841
842/*
843 * Install unknown family 15h support
844 */
845
846#ifdef OPTION_FAMILY15H_UNKNOWN
847 #if OPTION_FAMILY15H_UNKNOWN == TRUE
848 #if USES_REGISTER_TABLES == TRUE
849 CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
850 {
851 #if BASE_FAMILY_PCI == TRUE
852 &F15PciRegisterTable,
853 #endif
854 #if BASE_FAMILY_MSR == TRUE
855 &F15MsrRegisterTable,
856 #endif
857 // the end.
858 NULL
859 };
860 #endif
861
862 #if USES_REGISTER_TABLES == TRUE
863 CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
864 {
865 {MsrRegister, SetRegisterForMsrEntry},
866 {PciRegister, SetRegisterForPciEntry},
867 {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
868 {HtPhyRegister, SetRegisterForHtPhyEntry},
869 {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
870 {DeemphasisRegister, SetRegisterForDeemphasisEntry},
871 {ProfileFixup, SetRegisterForPerformanceProfileEntry},
872 {HtHostPciRegister, SetRegisterForHtHostEntry},
873 {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
874 {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
875 {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
876 {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
877 {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
878 {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
879 {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
880 // End
881 {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
882 };
883 #endif
884
885
886 CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
887 {
888 0,
889 #if DISABLE_PSTATE == TRUE
890 F15DisablePstate,
891 #else
892 (PF_CPU_DISABLE_PSTATE) CommonAssert,
893 #endif
894 #if TRANSITION_PSTATE == TRUE
895 F15TransitionPstate,
896 #else
897 (PF_CPU_TRANSITION_PSTATE) CommonAssert,
898 #endif
899 #if PROC_IDD_MAX == TRUE
900 (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
901 #else
902 (PF_CPU_GET_IDD_MAX) CommonAssert,
903 #endif
904 #if GET_TSC_RATE == TRUE
905 F15GetTscRate,
906 #else
907 (PF_CPU_GET_TSC_RATE) CommonAssert,
908 #endif
909 #if GET_NB_FREQ == TRUE
910 (PF_CPU_GET_NB_FREQ) CommonAssert,
911 #else
912 (PF_CPU_GET_NB_FREQ) CommonAssert,
913 #endif
914 #if GET_NB_FREQ == TRUE
915 (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
916 #else
917 (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
918 #endif
919 #if GET_NB_FREQ == TRUE
920 (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
921 #else
922 (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
923 #endif
924 #if IS_NBCOF_INIT_NEEDED == TRUE
925 (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
926 #else
927 (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
928 #endif
929 #if GET_NB_IDD_MAX == TRUE
930 (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
931 #else
932 (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
933 #endif
934 #if AP_INITIAL_LAUNCH == TRUE
935 F15LaunchApCore,
936 #else
937 (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
938 #endif
939 #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
940 (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
941 #else
942 (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
943 #endif
944 #if GET_AP_MAILBOX_FROM_HW == TRUE
945 (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
946 #else
947 (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
948 #endif
949 #if SET_AP_CORE_NUMBER == TRUE
950 (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
951 #else
952 (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
953 #endif
954 #if GET_AP_CORE_NUMBER == TRUE
955 (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
956 #else
957 (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
958 #endif
959 #if TRANSFER_AP_CORE_NUMBER == TRUE
960 (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
961 #else
962 (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
963 #endif
964 #if ID_POSITION_INITIAL_APICID == TRUE
965 F15CpuAmdCoreIdPositionInInitialApicId,
966 #else
967 (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
968 #endif
969 #if SAVE_FEATURES == TRUE
970 // F15SaveFeatures,
971 (PF_CPU_SAVE_FEATURES) CommonVoid,
972 #else
973 (PF_CPU_SAVE_FEATURES) CommonAssert,
974 #endif
975 #if WRITE_FEATURES == TRUE
976 // F15WriteFeatures,
977 (PF_CPU_WRITE_FEATURES) CommonVoid,
978 #else
979 (PF_CPU_WRITE_FEATURES) CommonAssert,
980 #endif
981 #if SET_WARM_RESET_FLAG == TRUE
982 F15SetAgesaWarmResetFlag,
983 #else
984 (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
985 #endif
986 #if GET_WARM_RESET_FLAG == TRUE
987 F15GetAgesaWarmResetFlag,
988 #else
989 (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
990 #endif
991 #if BRAND_STRING1 == TRUE
992 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
993 #else
994 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
995 #endif
996 #if BRAND_STRING2 == TRUE
997 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
998 #else
999 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1000 #endif
1001 #if GET_PATCHES == TRUE
1002 GetEmptyArray,
1003 #else
1004 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1005 #endif
1006 #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
1007 GetEmptyArray,
1008 #else
1009 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1010 #endif
1011 #if GET_CACHE_INFO == TRUE
1012 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
1013 #else
1014 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1015 #endif
1016 #if GET_SYSTEM_PM_TABLE == TRUE
1017 GetEmptyArray,
1018 #else
1019 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1020 #endif
1021 #if GET_WHEA_INIT == TRUE
1022 GetF15WheaInitData,
1023 #else
1024 (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
1025 #endif
1026 #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
1027 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
1028 #else
1029 (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
1030 #endif
1031 #if IS_NB_PSTATE_ENABLED == TRUE
1032 F15IsNbPstateEnabled,
1033 #else
1034 (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
1035 #endif
1036 #if (BASE_FAMILY_HT_PCI == TRUE)
1037 F15NextLinkHasHtPhyFeats,
1038 #else
1039 (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
1040 #endif
1041 #if (BASE_FAMILY_HT_PCI == TRUE)
1042 F15SetHtPhyRegister,
1043 #else
1044 (PF_SET_HT_PHY_REGISTER) CommonVoid,
1045 #endif
1046 #if BASE_FAMILY_PCI == TRUE
1047 F15GetNextHtLinkFeatures,
1048 #else
1049 (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
1050 #endif
1051 #if USES_REGISTER_TABLES == TRUE
1052 (REGISTER_TABLE **) F15UnknownRegisterTables,
1053 #else
1054 NULL,
1055 #endif
1056 #if USES_REGISTER_TABLES == TRUE
1057 (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
1058 #else
1059 NULL,
1060 #endif
1061 NULL,
1062 NULL,
1063 InitCacheEnabled,
1064 #if AGESA_ENTRY_INIT_EARLY == TRUE
1065 (PF_GET_EARLY_INIT_TABLE) CommonVoid
1066 #else
1067 (PF_GET_EARLY_INIT_TABLE) CommonVoid
1068 #endif
1069 };
1070
1071 #define OPT_F15_UNKNOWN_CPU {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , &cpuF15UnknownServices},
1072
1073 #else // OPTION_FAMILY15H_UNKNOWN == TRUE
1074 #define OPT_F15_UNKNOWN_CPU
1075 #define OPT_F15_UNKNOWN_ID
1076 #endif // OPTION_FAMILY15H_UNKNOWN == TRUE
1077#else // defined OPTION_FAMILY15H_UNKNOWN
1078 #define OPT_F15_UNKNOWN_CPU
1079 #define OPT_F15_UNKNOWN_ID
1080#endif // defined OPTION_FAMILY15H_UNKNOWN
1081
1082
1083// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
1084#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
1085 #undef FAMILY_MMIO_BASE_MASK
1086 #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
1087#endif
1088
1089
1090#undef OPT_F15_ID_TABLE
1091#define OPT_F15_ID_TABLE {0x15, {(AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , (AMD_FAMILY_UNKNOWN | AMD_F15_OR_B2 | AMD_F15_TN_A0 | 0x0000000000100000ull ) }, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
1092
1093#undef OPT_F15_TABLE
1094#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_TN_CPU {0, NULL}, OPT_F15_UNKNOWN_CPU
1095
1096#if OPTION_G34_SOCKET_SUPPORT == TRUE
1097 #define F15_G34_BRANDSTRING1 NULL,
1098 #define F15_G34_BRANDSTRING2 NULL,
1099#else
1100 #define F15_G34_BRANDSTRING1
1101 #define F15_G34_BRANDSTRING2
1102#endif
1103#if OPTION_C32_SOCKET_SUPPORT == TRUE
1104 #define F15_C32_BRANDSTRING1 NULL,
1105 #define F15_C32_BRANDSTRING2 NULL,
1106#else
1107 #define F15_C32_BRANDSTRING1
1108 #define F15_C32_BRANDSTRING2
1109#endif
1110#if OPTION_AM3_SOCKET_SUPPORT == TRUE
1111 #define F15_AM3_BRANDSTRING1 NULL,
1112 #define F15_AM3_BRANDSTRING2 NULL,
1113#else
1114 #define F15_AM3_BRANDSTRING1
1115 #define F15_AM3_BRANDSTRING2
1116#endif
1117#if OPTION_FS1_SOCKET_SUPPORT == TRUE
1118 #define F15_FS1_BRANDSTRING1 NULL,
1119 #define F15_FS1_BRANDSTRING2 NULL,
1120#else
1121 #define F15_FS1_BRANDSTRING1
1122 #define F15_FS1_BRANDSTRING2
1123#endif
1124#if OPTION_FM2_SOCKET_SUPPORT == TRUE
1125 #define F15_FM2_BRANDSTRING1 NULL,
1126 #define F15_FM2_BRANDSTRING2 NULL,
1127#else
1128 #define F15_FM2_BRANDSTRING1
1129 #define F15_FM2_BRANDSTRING2
1130#endif
1131#if OPTION_FP2_SOCKET_SUPPORT == TRUE
1132 #define F15_FP2_BRANDSTRING1 NULL,
1133 #define F15_FP2_BRANDSTRING2 NULL,
1134#else
1135 #define F15_FP2_BRANDSTRING1
1136 #define F15_FP2_BRANDSTRING2
1137#endif
1138
1139
1140#if BRAND_STRING1 == TRUE
1141 CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
1142 {
1143 F15_G34_BRANDSTRING1
1144 F15_C32_BRANDSTRING1
1145 F15_AM3_BRANDSTRING1
1146 F15_FS1_BRANDSTRING1
1147 NULL,
1148 F15_FM2_BRANDSTRING1
1149 NULL,
1150 F15_FP2_BRANDSTRING1
1151 };
1152
1153 CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
1154#endif
1155
1156#if BRAND_STRING2 == TRUE
1157 CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
1158 {
1159 F15_G34_BRANDSTRING2
1160 F15_C32_BRANDSTRING2
1161 F15_AM3_BRANDSTRING2
1162 F15_FS1_BRANDSTRING2
1163 NULL,
1164 F15_FM2_BRANDSTRING2
1165 NULL,
1166 F15_FP2_BRANDSTRING2
1167 };
1168
1169 CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
1170#endif
1171
1172CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
1173{
1174 OPT_F15_OR_ID
1175 OPT_F15_TN_ID
1176 NULL
1177};
1178
1179#endif // _OPTION_FAMILY_15H_INSTALL_H_