Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
Felix Held | 8d1ef73 | 2022-12-06 21:29:49 +0100 | [diff] [blame^] | 6 | #include <gpio.h> |
Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 7 | |
| 8 | /* GPIO configuration in ramstage*/ |
| 9 | static const struct soc_amd_gpio base_gpio_table[] = { |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 10 | /* PWR_BTN_L */ |
| 11 | PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), |
| 12 | /* SYS_RESET_L */ |
| 13 | PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), |
| 14 | /* WAKE_L */ |
| 15 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), |
| 16 | /* SOC_PEN_DETECT_ODL */ |
| 17 | PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3), |
| 18 | /* EN_PWR_FP */ |
Moises Garcia | e046062 | 2022-06-21 15:05:08 -0700 | [diff] [blame] | 19 | PAD_GPO(GPIO_4, LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 20 | /* EN_PP3300_TCHPAD */ |
| 21 | PAD_GPO(GPIO_5, HIGH), |
| 22 | /* SSD_AUX_RESET_L */ |
| 23 | PAD_GPO(GPIO_6, HIGH), |
| 24 | /* WLAN_AUX_RST_L */ |
| 25 | PAD_GPO(GPIO_7, HIGH), |
| 26 | /* EN_PWR_WWAN_X */ |
Karthikeyan Ramasubramanian | a2bba5b | 2022-05-02 13:38:23 -0600 | [diff] [blame] | 27 | PAD_GPO(GPIO_8, LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 28 | /* EN_PP3300_WLAN */ |
| 29 | PAD_GPO(GPIO_9, HIGH), |
| 30 | /* BT_DISABLE */ |
| 31 | PAD_GPO(GPIO_10, LOW), |
| 32 | /* EC_SOC_WAKE_ODL */ |
| 33 | PAD_SCI(GPIO_11, PULL_NONE, EDGE_LOW), |
| 34 | /* SOC_FP_RST_L */ |
| 35 | PAD_GPO(GPIO_12, LOW), |
| 36 | /* GPIO_13 - GPIO_15: Not available */ |
| 37 | /* USB_OC0_L */ |
| 38 | PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), |
| 39 | /* SOC_SAR_INT_L */ |
| 40 | PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW), |
| 41 | /* GSC_SOC_INT_L */ |
Raul E Rangel | 7496392 | 2022-03-16 11:20:54 -0600 | [diff] [blame] | 42 | PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 43 | /* I2C3_SCL */ |
| 44 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 45 | /* I2C3_SDA */ |
| 46 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
| 47 | /* WLAN_DISABLE */ |
| 48 | PAD_GPO(GPIO_21, LOW), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 49 | /* ESPI_ALERT_L */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 50 | PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), |
| 51 | /* AC_PRES */ |
| 52 | PAD_NF(GPIO_23, AC_PRES, PULL_UP), |
| 53 | /* SOC_FP_INT_L */ |
Frank Wu | c904341 | 2022-10-21 10:32:30 +0800 | [diff] [blame] | 54 | PAD_SCI(GPIO_24, PULL_NONE, LEVEL_LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 55 | /* GPIO_25: Not available */ |
| 56 | /* PCIE_RST0_L */ |
| 57 | PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), |
| 58 | /* SD_AUX_RESET_L */ |
Ian Feng | be91874 | 2022-04-20 17:32:01 +0800 | [diff] [blame] | 59 | PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 60 | /* GPIO_28: Not available */ |
Ian Feng | e204690 | 2022-04-12 15:06:25 +0800 | [diff] [blame] | 61 | /* TCHSCR_INT_ODL */ |
| 62 | PAD_GPI(GPIO_29, PULL_NONE), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 63 | /* ESPI_CS_L */ |
| 64 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 65 | /* Unused */ |
| 66 | PAD_NC(GPIO_31), |
| 67 | /* LPC_RST_L */ |
Jon Murphy | d42d8ea | 2022-03-09 13:35:43 -0700 | [diff] [blame] | 68 | PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 69 | /* GPIO_33 - GPIO_39: Not available */ |
| 70 | /* SOC_TCHPAD_INT_ODL */ |
EricKY Cheng | 849d57a | 2022-09-22 18:08:38 +0800 | [diff] [blame] | 71 | PAD_SCI(GPIO_40, PULL_NONE, LEVEL_LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 72 | /* GPIO_41: Not available */ |
| 73 | /* WWAN_RST_L */ |
| 74 | PAD_GPO(GPIO_42, HIGH), |
| 75 | /* GPIO_43 - GPIO_66: Not available */ |
| 76 | /* GPIO_67 */ |
| 77 | PAD_GPI(GPIO_67, PULL_NONE), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 78 | /* ESPI1_DATA2 */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 79 | PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 80 | /* ESPI1_DATA3 */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 81 | PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 82 | /* SOC_DISABLE_DISP_BL */ |
| 83 | PAD_GPO(GPIO_74, LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 84 | /* TCHSCR_REPORT_EN */ |
| 85 | PAD_GPO(GPIO_76, LOW), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 86 | /* ESPI_CLK */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 87 | PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), |
| 88 | /* EN_PP3300_CAM */ |
| 89 | PAD_GPO(GPIO_78, HIGH), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 90 | /* ESPI1_DATA1 */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 91 | PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), |
Raul E Rangel | cc1426b | 2022-03-24 16:51:21 -0600 | [diff] [blame] | 92 | /* ESPI1_DATA0 */ |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 93 | PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), |
| 94 | /* EC_SOC_INT_ODL */ |
| 95 | PAD_GPI(GPIO_84, PULL_NONE), |
| 96 | /* RAM_ID_1 / DEV_BEEP_DATA */ |
| 97 | PAD_GPI(GPIO_85, PULL_NONE), |
| 98 | /* RAM_ID_2 / DEV_BEEP_LRCLK */ |
| 99 | PAD_GPI(GPIO_89, PULL_NONE), |
| 100 | /* HP_INT_ODL */ |
| 101 | PAD_GPI(GPIO_90, PULL_NONE), |
| 102 | /* RAM_ID_3 / DEV_BEEP_BCLK */ |
| 103 | PAD_GPI(GPIO_91, PULL_NONE), |
| 104 | /* CLK_REQ0_L / SSD */ |
| 105 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
| 106 | /* I2C2_SCL */ |
| 107 | PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), |
| 108 | /* I2C2_SDA */ |
| 109 | PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), |
| 110 | /* CLK_REQ1_L / SD */ |
| 111 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
| 112 | /* CLK_REQ2_L / WLAN */ |
| 113 | PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), |
| 114 | /* SOC_FPMCU_BOOT0 */ |
| 115 | PAD_GPO(GPIO_130, LOW), |
Matt DeVillier | f90ff45 | 2022-09-22 14:41:22 -0500 | [diff] [blame] | 116 | /* Enable touchscreen, release from reset */ |
Ian Feng | e204690 | 2022-04-12 15:06:25 +0800 | [diff] [blame] | 117 | /* EN_PP3300_TCHSCR */ |
Matt DeVillier | f90ff45 | 2022-09-22 14:41:22 -0500 | [diff] [blame] | 118 | PAD_GPO(GPIO_131, HIGH), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 119 | /* TCHSCR_RESET_L */ |
Matt DeVillier | f90ff45 | 2022-09-22 14:41:22 -0500 | [diff] [blame] | 120 | PAD_GPO(GPIO_136, HIGH), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 121 | /* SOC_BIOS_WP_L */ |
| 122 | PAD_GPI(GPIO_138, PULL_NONE), |
| 123 | /* EN_SPKR */ |
Ian Feng | 2c89d08a | 2022-04-22 16:29:05 +0800 | [diff] [blame] | 124 | PAD_GPO(GPIO_139, LOW), |
Jon Murphy | d287375 | 2022-02-16 06:43:58 -0700 | [diff] [blame] | 125 | /* RAM_ID_0 / DEV_BEEP_EN */ |
| 126 | PAD_GPI(GPIO_144, PULL_NONE), |
| 127 | /* UART1_TXD / FP */ |
| 128 | PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), |
| 129 | /* UART0_RXD / DBG */ |
| 130 | PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), |
| 131 | /* UART1_RXD / FP*/ |
| 132 | PAD_NF(GPIO_142, UART1_RXD, PULL_NONE), |
| 133 | /* UART0_TXD / DBG */ |
| 134 | PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), |
| 135 | /* I2C0_SCL */ |
| 136 | PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), |
| 137 | /* I2C0_SDA */ |
| 138 | PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), |
| 139 | /* I2C1_SCL */ |
| 140 | PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), |
| 141 | /* I2C1_SDA */ |
| 142 | PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), |
Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 143 | }; |
| 144 | |
Raul E Rangel | 96839d1 | 2022-03-24 16:55:44 -0600 | [diff] [blame] | 145 | static const struct soc_amd_gpio espi_gpio_table[] = { |
| 146 | /* ESPI_CS_L */ |
| 147 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
| 148 | /* ESPI_CLK */ |
| 149 | PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), |
| 150 | /* ESPI1_DATA0 */ |
| 151 | PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), |
| 152 | /* ESPI1_DATA1 */ |
| 153 | PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), |
| 154 | /* ESPI1_DATA2 */ |
| 155 | PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), |
| 156 | /* ESPI1_DATA3 */ |
| 157 | PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), |
| 158 | /* ESPI_ALERT_L */ |
| 159 | PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), |
| 160 | }; |
| 161 | |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 162 | static const struct soc_amd_gpio tpm_gpio_table[] = { |
| 163 | /* I2C3_SCL */ |
| 164 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 165 | /* I2C3_SDA */ |
| 166 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
| 167 | /* GSC_SOC_INT_L */ |
| 168 | PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
| 169 | }; |
| 170 | |
Jon Murphy | 2a7445a | 2022-02-16 06:46:47 -0700 | [diff] [blame] | 171 | /* GPIO configuration for sleep */ |
| 172 | static const struct soc_amd_gpio sleep_gpio_table[] = { |
| 173 | /* TODO: Fill sleep gpio configuration */ |
| 174 | }; |
| 175 | |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 176 | /* GPIO configuration in bootblock */ |
Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 177 | static const struct soc_amd_gpio bootblock_gpio_table[] = { |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 178 | /* Enable WLAN */ |
| 179 | /* WLAN_DISABLE */ |
| 180 | PAD_GPO(GPIO_21, LOW), |
Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 181 | }; |
| 182 | |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 183 | /* Early GPIO configuration */ |
| 184 | static const struct soc_amd_gpio early_gpio_table[] = { |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 185 | /* WLAN_AUX_RESET_L (ACTIVE LOW) */ |
| 186 | PAD_GPO(GPIO_7, LOW), |
| 187 | /* Power on WLAN */ |
| 188 | /* EN_PP3300_WLAN */ |
| 189 | PAD_GPO(GPIO_9, HIGH), |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 190 | }; |
| 191 | |
Matt DeVillier | cfec5dd | 2022-09-23 14:25:41 -0500 | [diff] [blame] | 192 | /* Romstage GPIO configuration */ |
| 193 | static const struct soc_amd_gpio romstage_gpio_table[] = { |
| 194 | /* PCIE_RST needs to be brought high before FSP-M runs */ |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 195 | /* Deassert all AUX_RESET lines & PCIE_RST */ |
| 196 | /* WLAN_AUX_RESET_L (ACTIVE LOW) */ |
| 197 | PAD_GPO(GPIO_7, HIGH), |
| 198 | /* PCIE_RST0_L */ |
| 199 | PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), |
Ian Feng | 4852c11 | 2022-05-03 14:52:20 +0800 | [diff] [blame] | 200 | /* SD_AUX_RESET_L */ |
| 201 | PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), |
Jon Murphy | 156aa9b | 2022-08-05 10:41:02 -0600 | [diff] [blame] | 202 | /* SSD_AUX_RESET_L */ |
| 203 | PAD_GPO(GPIO_6, HIGH), |
Matt DeVillier | f90ff45 | 2022-09-22 14:41:22 -0500 | [diff] [blame] | 204 | /* Enable touchscreen, hold in reset */ |
| 205 | /* EN_PP3300_TCHSCR */ |
| 206 | PAD_GPO(GPIO_131, HIGH), |
| 207 | /* TCHSCR_RESET_L */ |
| 208 | PAD_GPO(GPIO_136, LOW), |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 209 | }; |
| 210 | |
Matt DeVillier | 5f69b86 | 2022-09-23 14:51:12 -0500 | [diff] [blame] | 211 | void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 212 | { |
Matt DeVillier | cfec5dd | 2022-09-23 14:25:41 -0500 | [diff] [blame] | 213 | *size = ARRAY_SIZE(romstage_gpio_table); |
| 214 | *gpio = romstage_gpio_table; |
Jon Murphy | 9df0085 | 2022-02-17 22:42:57 -0700 | [diff] [blame] | 215 | } |
| 216 | |
Matt DeVillier | 5f69b86 | 2022-09-23 14:51:12 -0500 | [diff] [blame] | 217 | __weak void variant_romstage_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 218 | { |
| 219 | *size = 0; |
| 220 | *gpio = NULL; |
| 221 | } |
| 222 | |
Matt DeVillier | 4236e2a | 2022-09-23 13:33:00 -0500 | [diff] [blame] | 223 | void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
Jon Murphy | 9042427 | 2022-02-16 06:34:39 -0700 | [diff] [blame] | 224 | { |
| 225 | *size = ARRAY_SIZE(base_gpio_table); |
| 226 | *gpio = base_gpio_table; |
| 227 | } |
| 228 | |
| 229 | __weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 230 | { |
| 231 | *size = 0; |
| 232 | *gpio = NULL; |
| 233 | } |
| 234 | |
| 235 | __weak void variant_bootblock_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 236 | { |
| 237 | *size = ARRAY_SIZE(bootblock_gpio_table); |
| 238 | *gpio = bootblock_gpio_table; |
| 239 | } |
Jon Murphy | 2a7445a | 2022-02-16 06:46:47 -0700 | [diff] [blame] | 240 | |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 241 | __weak void variant_early_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 242 | { |
| 243 | *size = ARRAY_SIZE(early_gpio_table); |
| 244 | *gpio = early_gpio_table; |
| 245 | } |
| 246 | |
| 247 | __weak void variant_early_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 248 | { |
| 249 | *size = 0; |
| 250 | *gpio = NULL; |
| 251 | } |
| 252 | |
Jon Murphy | 2a7445a | 2022-02-16 06:46:47 -0700 | [diff] [blame] | 253 | __weak void variant_sleep_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 254 | { |
| 255 | *size = ARRAY_SIZE(sleep_gpio_table); |
| 256 | *gpio = sleep_gpio_table; |
| 257 | } |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 258 | |
Raul E Rangel | 96839d1 | 2022-03-24 16:55:44 -0600 | [diff] [blame] | 259 | __weak void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 260 | { |
| 261 | *size = ARRAY_SIZE(espi_gpio_table); |
| 262 | *gpio = espi_gpio_table; |
| 263 | } |
| 264 | |
Jon Murphy | 0bc013b | 2022-02-17 21:05:19 -0700 | [diff] [blame] | 265 | __weak void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) |
| 266 | { |
| 267 | *size = ARRAY_SIZE(tpm_gpio_table); |
| 268 | *gpio = tpm_gpio_table; |
| 269 | } |