Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
| 3 | External(\_SB.ALIB, MethodObj) |
| 4 | |
| 5 | /* System Bus */ |
| 6 | /* _SB.PCI0 */ |
| 7 | |
| 8 | /* Operating System Capabilities Method */ |
| 9 | Method(_OSC,4) |
| 10 | { |
| 11 | /* Check for proper PCI/PCIe UUID */ |
| 12 | If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 13 | { |
| 14 | /* Let OS control everything */ |
| 15 | Return (Arg3) |
| 16 | } Else { |
| 17 | CreateDWordField(Arg3,0,CDW1) |
| 18 | Or(CDW1,4,CDW1) // Unrecognized UUID |
| 19 | Return(Arg3) |
| 20 | } |
| 21 | } |
| 22 | |
| 23 | /* Describe the Southbridge devices */ |
| 24 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 25 | /* 0:14.0 - SMBUS */ |
| 26 | Device(SBUS) { |
| 27 | Name(_ADR, 0x00140000) |
| 28 | } /* end SBUS */ |
| 29 | |
| 30 | #include "usb.asl" |
| 31 | |
| 32 | /* 0:14.2 - I2S Audio */ |
| 33 | |
| 34 | /* 0:14.3 - LPC */ |
| 35 | #include <soc/amd/common/acpi/lpc.asl> |
| 36 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 37 | Name(CRES, ResourceTemplate() { |
| 38 | /* Set the Bus number and Secondary Bus number for the PCI0 device |
| 39 | * The Secondary bus range for PCI0 lets the system |
| 40 | * know what bus values are allowed on the downstream |
| 41 | * side of this PCI bus if there is a PCI-PCI bridge. |
| 42 | * PCI busses can have 256 secondary busses which |
| 43 | * range from [0-0xFF] but they do not need to be |
| 44 | * sequential. |
| 45 | */ |
| 46 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 47 | 0x0000, /* address granularity */ |
| 48 | 0x0000, /* range minimum */ |
| 49 | 0x00ff, /* range maximum */ |
| 50 | 0x0000, /* translation */ |
| 51 | 0x0100, /* length */ |
| 52 | ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ |
| 53 | |
| 54 | IO(Decode16, 0x0cf8, 0x0cf8, 1, 8) |
| 55 | |
| 56 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 57 | 0x0000, /* address granularity */ |
| 58 | 0x0000, /* range minimum */ |
| 59 | 0x0cf7, /* range maximum */ |
| 60 | 0x0000, /* translation */ |
| 61 | 0x0cf8 /* length */ |
| 62 | ) |
| 63 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 64 | 0x0000, /* address granularity */ |
| 65 | 0x03b0, /* range minimum */ |
| 66 | 0x03df, /* range maximum */ |
| 67 | 0x0000, /* translation */ |
| 68 | 0x0030 /* length */ |
| 69 | ) |
| 70 | |
| 71 | WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 72 | 0x0000, /* address granularity */ |
| 73 | 0x0d00, /* range minimum */ |
| 74 | 0xffff, /* range maximum */ |
| 75 | 0x0000, /* translation */ |
| 76 | 0xf300 /* length */ |
| 77 | ) |
| 78 | |
| 79 | Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ |
| 80 | Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ |
| 81 | |
| 82 | /* memory space for PCI BARs below 4GB */ |
| 83 | Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) |
| 84 | }) /* End Name(_SB.PCI0.CRES) */ |
| 85 | |
| 86 | Method(_CRS, 0) { |
| 87 | /* DBGO("\\_SB\\PCI0\\_CRS\n") */ |
| 88 | CreateDWordField(CRES, ^MMIO._BAS, MM1B) |
| 89 | CreateDWordField(CRES, ^MMIO._LEN, MM1L) |
| 90 | |
| 91 | /* |
| 92 | * Declare memory between TOM1 and 4GB as available |
| 93 | * for PCI MMIO. |
| 94 | * Use ShiftLeft to avoid 64bit constant (for XP). |
| 95 | * This will work even if the OS does 32bit arithmetic, as |
| 96 | * 32bit (0x00000000 - TOM1) will wrap and give the same |
| 97 | * result as 64bit (0x100000000 - TOM1). |
| 98 | */ |
| 99 | Store(TOM1, MM1B) |
| 100 | ShiftLeft(0x10000000, 4, Local0) |
| 101 | Subtract(Local0, TOM1, Local0) |
| 102 | Store(Local0, MM1L) |
| 103 | |
Aaron Durbin | 8c28e51 | 2020-06-23 13:49:21 -0600 | [diff] [blame^] | 104 | CreateWordField(CRES, ^PSB0._MAX, BMAX) |
| 105 | CreateWordField(CRES, ^PSB0._LEN, BLEN) |
| 106 | Store(CONFIG_MMCONF_BUS_NUMBER - 1, BMAX) |
| 107 | Store(CONFIG_MMCONF_BUS_NUMBER, BLEN) |
| 108 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 109 | Return(CRES) /* note to change the Name buffer */ |
| 110 | } /* end of Method(_SB.PCI0._CRS) */ |
| 111 | |
| 112 | /* |
| 113 | * |
| 114 | * FIRST METHOD CALLED UPON BOOT |
| 115 | * |
| 116 | * 1. If debugging, print current OS and ACPI interpreter. |
| 117 | * 2. Get PCI Interrupt routing from ACPI VSM, this |
| 118 | * value is based on user choice in BIOS setup. |
| 119 | */ |
| 120 | Method(_INI, 0, Serialized) { |
| 121 | /* DBGO("\\_SB\\_INI\n") */ |
| 122 | /* DBGO(" DSDT.ASL code from ") */ |
| 123 | /* DBGO(__DATE__) */ |
| 124 | /* DBGO(" ") */ |
| 125 | /* DBGO(__TIME__) */ |
| 126 | /* DBGO("\n Sleep states supported: ") */ |
| 127 | /* DBGO("\n") */ |
| 128 | /* DBGO(" \\_OS=") */ |
| 129 | /* DBGO(\_OS) */ |
| 130 | /* DBGO("\n \\_REV=") */ |
| 131 | /* DBGO(\_REV) */ |
| 132 | /* DBGO("\n") */ |
| 133 | |
| 134 | /* Determine the OS we're running on */ |
| 135 | OSFL() |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 136 | } /* End Method(_SB._INI) */ |
| 137 | |
| 138 | Method(OSFL, 0){ |
| 139 | |
| 140 | if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ |
| 141 | |
| 142 | if (CondRefOf(\_OSI)) |
| 143 | { |
| 144 | Store(1, OSVR) /* Assume some form of XP */ |
| 145 | if (\_OSI("Windows 2006")) /* Vista */ |
| 146 | { |
| 147 | Store(2, OSVR) |
| 148 | } |
| 149 | } else { |
| 150 | If(WCMP(\_OS,"Linux")) { |
| 151 | Store(3, OSVR) /* Linux */ |
| 152 | } Else { |
| 153 | Store(4, OSVR) /* Gotta be WinCE */ |
| 154 | } |
| 155 | } |
| 156 | Return(OSVR) |
| 157 | } |
| 158 | |
| 159 | OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) |
| 160 | Field( SMIC, ByteAcc, NoLock, Preserve) { |
| 161 | /* MISC registers */ |
| 162 | offset (0x03ee), |
| 163 | U3PS, 2, /* Usb3PowerSel */ |
| 164 | |
| 165 | offset (0x0e28), |
| 166 | ,29 , |
| 167 | SARP, 1, /* Sata Ref Clock Powerdown */ |
| 168 | U2RP, 1, /* Usb2 Ref Clock Powerdown */ |
| 169 | U3RP, 1, /* Usb3 Ref Clock Powerdown */ |
| 170 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 171 | /* AOAC Registers */ |
| 172 | offset (0x1e4a), /* I2C0 D3 Control */ |
| 173 | I0TD, 2, |
| 174 | , 1, |
| 175 | I0PD, 1, |
| 176 | offset (0x1e4b), /* I2C0 D3 State */ |
| 177 | I0DS, 3, |
| 178 | |
| 179 | offset (0x1e4c), /* I2C1 D3 Control */ |
| 180 | I1TD, 2, |
| 181 | , 1, |
| 182 | I1PD, 1, |
| 183 | offset (0x1e4d), /* I2C1 D3 State */ |
| 184 | I1DS, 3, |
| 185 | |
| 186 | offset (0x1e4e), /* I2C2 D3 Control */ |
| 187 | I2TD, 2, |
| 188 | , 1, |
| 189 | I2PD, 1, |
| 190 | offset (0x1e4f), /* I2C2 D3 State */ |
| 191 | I2DS, 3, |
| 192 | |
| 193 | offset (0x1e50), /* I2C3 D3 Control */ |
| 194 | I3TD, 2, |
| 195 | , 1, |
| 196 | I3PD, 1, |
| 197 | offset (0x1e51), /* I2C3 D3 State */ |
| 198 | I3DS, 3, |
| 199 | |
| 200 | offset (0x1e56), /* UART0 D3 Control */ |
| 201 | U0TD, 2, |
| 202 | , 1, |
| 203 | U0PD, 1, |
| 204 | offset (0x1e57), /* UART0 D3 State */ |
| 205 | U0DS, 3, |
| 206 | |
| 207 | offset (0x1e58), /* UART1 D3 Control */ |
| 208 | U1TD, 2, |
| 209 | , 1, |
| 210 | U1PD, 1, |
| 211 | offset (0x1e59), /* UART1 D3 State */ |
| 212 | U1DS, 3, |
| 213 | |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 214 | offset (0x1e60), /* UART2 D3 Control */ |
| 215 | U2TD, 2, |
| 216 | , 1, |
| 217 | U2PD, 1, |
| 218 | offset (0x1e61), /* UART2 D3 State */ |
| 219 | U2DS, 3, |
| 220 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 221 | offset (0x1e71), /* SD D3 State */ |
| 222 | SDDS, 3, |
| 223 | |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 224 | offset (0x1e74), /* UART3 D3 Control */ |
| 225 | U3TD, 2, |
| 226 | , 1, |
| 227 | U3PD, 1, |
| 228 | offset (0x1e75), /* UART3 D3 State */ |
| 229 | U3DS, 3, |
| 230 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 231 | offset (0x1e80), /* Shadow Register Request */ |
| 232 | , 15, |
| 233 | RQ15, 1, |
| 234 | , 2, |
| 235 | RQ18, 1, |
| 236 | , 4, |
| 237 | RQ23, 1, |
| 238 | RQ24, 1, |
| 239 | , 5, |
| 240 | RQTY, 1, |
| 241 | offset (0x1e84), /* Shadow Register Status */ |
| 242 | , 15, |
| 243 | SASR, 1, /* SATA 15 Shadow Reg Request Status Register */ |
| 244 | , 2, |
| 245 | U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */ |
| 246 | , 4, |
| 247 | U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ |
| 248 | SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ |
| 249 | |
| 250 | offset (0x1ea0), /* PwrGood Control */ |
| 251 | PG1A, 1, |
| 252 | PG2_, 1, |
| 253 | ,1, |
| 254 | U3PG, 1, /* Usb3 Power Good BIT3 */ |
| 255 | |
| 256 | offset (0x1ea3), /* PwrGood Control b[31:24] */ |
| 257 | PGA3, 8 , |
| 258 | } |
| 259 | |
| 260 | OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000) |
| 261 | Field(FCFG, DwordAcc, NoLock, Preserve) |
| 262 | { |
| 263 | /* XHCI */ |
| 264 | Offset(0x00080010), /* Base address */ |
| 265 | XHBA, 32, |
| 266 | Offset(0x0008002c), /* Subsystem ID / Vendor ID */ |
| 267 | XH2C, 32, |
| 268 | |
| 269 | Offset(0x00080048), /* Indirect PCI Index Register */ |
| 270 | IDEX, 32, |
| 271 | DATA, 32, |
| 272 | Offset(0x00080054), /* PME Control / Status */ |
| 273 | U_PS, 2, |
| 274 | |
| 275 | /* EHCI */ |
| 276 | Offset(0x00090004), /* Control */ |
| 277 | , 1, |
| 278 | EHME, 1, |
| 279 | Offset(0x00090010), /* Base address */ |
| 280 | EHBA, 32, |
| 281 | Offset(0x0009002c), /* Subsystem ID / Vendor ID */ |
| 282 | EH2C, 32, |
| 283 | Offset(0x00090054), /* EHCI Spare 1 */ |
| 284 | EH54, 8, |
| 285 | Offset(0x00090064), /* Misc Control 2 */ |
| 286 | EH64, 8, |
| 287 | |
| 288 | Offset(0x000900c4), /* PME Control / Status */ |
| 289 | E_PS, 2, |
| 290 | |
| 291 | /* LPC Bridge */ |
| 292 | Offset(0x000a30cb), /* ClientRomProtect[31:24] */ |
| 293 | , 7, |
| 294 | AUSS, 1, /* AutoSizeStart */ |
| 295 | } |
| 296 | |
| 297 | /* |
| 298 | * Arg0:device: |
| 299 | * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1, |
Marshall Dawson | 5f3c465 | 2019-09-17 11:22:31 -0600 | [diff] [blame] | 300 | * 18=EHCI, 23=xHCI, 24=SD |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 301 | * Arg1:D-state |
| 302 | */ |
| 303 | Mutex (FDAS, 0) /* FCH Device AOAC Semophore */ |
| 304 | Method(FDDC, 2, Serialized) |
| 305 | { |
| 306 | Acquire(FDAS, 0xffff) |
| 307 | |
| 308 | if(LEqual(Arg1, 0)) { |
| 309 | Switch(ToInteger(Arg0)) { |
| 310 | Case(Package() {5, 15, 24}) { |
| 311 | Store(One, PG1A) |
| 312 | } |
| 313 | Case(Package() {6, 7, 8, 11, 12, 18}) { |
| 314 | Store(One, PG2_) |
| 315 | } |
| 316 | } |
| 317 | /* put device into D0 */ |
| 318 | Switch(ToInteger(Arg0)) |
| 319 | { |
| 320 | Case(5) { |
| 321 | Store(0x00, I0TD) |
| 322 | Store(One, I0PD) |
| 323 | Store(I0DS, Local0) |
| 324 | while(LNotEqual(Local0,0x7)) { |
| 325 | Store(I0DS, Local0) |
| 326 | } |
| 327 | } |
| 328 | Case(6) { |
| 329 | Store(0x00, I1TD) |
| 330 | Store(One, I1PD) |
| 331 | Store(I1DS, Local0) |
| 332 | while(LNotEqual(Local0,0x7)) { |
| 333 | Store(I1DS, Local0) |
| 334 | } |
| 335 | } |
| 336 | Case(7) { |
| 337 | Store(0x00, I2TD) |
| 338 | Store(One, I2PD) |
| 339 | Store(I2DS, Local0) |
| 340 | while(LNotEqual(Local0,0x7)) { |
| 341 | Store(I2DS, Local0) |
| 342 | } |
| 343 | } |
| 344 | Case(8) {Store(0x00, I3TD) |
| 345 | Store(One, I3PD) |
| 346 | Store(I3DS, Local0) |
| 347 | while(LNotEqual(Local0,0x7)) { |
| 348 | Store(I3DS, Local0) |
| 349 | } |
| 350 | } |
| 351 | Case(11) { |
| 352 | Store(0x00, U0TD) |
| 353 | Store(One, U0PD) |
| 354 | Store(U0DS, Local0) |
| 355 | while(LNotEqual(Local0,0x7)) { |
| 356 | Store(U0DS, Local0) |
| 357 | } |
| 358 | } |
| 359 | Case(12) { |
| 360 | Store(0x00, U1TD) |
| 361 | Store(One, U1PD) |
| 362 | Store(U1DS, Local0) |
| 363 | while(LNotEqual(Local0,0x7)) { |
| 364 | Store(U1DS, Local0) |
| 365 | } |
| 366 | } |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 367 | Case(16) { |
| 368 | Store(0x00, U2TD) |
| 369 | Store(One, U2PD) |
| 370 | Store(U2DS, Local0) |
| 371 | while(LNotEqual(Local0,0x7)) { |
| 372 | Store(U2DS, Local0) |
| 373 | } |
| 374 | } |
| 375 | Case(26) { |
| 376 | Store(0x00, U3TD) |
| 377 | Store(One, U3PD) |
| 378 | Store(U3DS, Local0) |
| 379 | while(LNotEqual(Local0,0x7)) { |
| 380 | Store(U3DS, Local0) |
| 381 | } |
| 382 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 383 | } |
| 384 | } else { |
| 385 | /* put device into D3cold */ |
| 386 | Switch(ToInteger(Arg0)) |
| 387 | { |
| 388 | Case(5) { |
| 389 | Store(Zero, I0PD) |
| 390 | Store(I0DS, Local0) |
| 391 | while(LNotEqual(Local0,0x0)) { |
| 392 | Store(I0DS, Local0) |
| 393 | } |
| 394 | Store(0x03, I0TD) |
| 395 | } |
| 396 | Case(6) { |
| 397 | Store(Zero, I1PD) |
| 398 | Store(I1DS, Local0) |
| 399 | while(LNotEqual(Local0,0x0)) { |
| 400 | Store(I1DS, Local0) |
| 401 | } |
| 402 | Store(0x03, I1TD) |
| 403 | } |
| 404 | Case(7) { |
| 405 | Store(Zero, I2PD) |
| 406 | Store(I2DS, Local0) |
| 407 | while(LNotEqual(Local0,0x0)) { |
| 408 | Store(I2DS, Local0) |
| 409 | } |
| 410 | Store(0x03, I2TD)} |
| 411 | Case(8) { |
| 412 | Store(Zero, I3PD) |
| 413 | Store(I3DS, Local0) |
| 414 | while(LNotEqual(Local0,0x0)) { |
| 415 | Store(I3DS, Local0) |
| 416 | } |
| 417 | Store(0x03, I3TD) |
| 418 | } |
| 419 | Case(11) { |
| 420 | Store(Zero, U0PD) |
| 421 | Store(U0DS, Local0) |
| 422 | while(LNotEqual(Local0,0x0)) { |
| 423 | Store(U0DS, Local0) |
| 424 | } |
| 425 | Store(0x03, U0TD) |
| 426 | } |
| 427 | Case(12) { |
| 428 | Store(Zero, U1PD) |
| 429 | Store(U1DS, Local0) |
| 430 | while(LNotEqual(Local0,0x0)) { |
| 431 | Store(U1DS, Local0) |
| 432 | } |
| 433 | Store(0x03, U1TD) |
| 434 | } |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 435 | Case(16) { |
| 436 | Store(Zero, U2PD) |
| 437 | Store(U2DS, Local0) |
| 438 | while(LNotEqual(Local0,0x0)) { |
| 439 | Store(U2DS, Local0) |
| 440 | } |
| 441 | Store(0x03, U2TD) |
| 442 | } |
| 443 | Case(26) { |
| 444 | Store(Zero, U3PD) |
| 445 | Store(U3DS, Local0) |
| 446 | while(LNotEqual(Local0,0x0)) { |
| 447 | Store(U3DS, Local0) |
| 448 | } |
| 449 | Store(0x03, U3TD) |
| 450 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 451 | } |
| 452 | if(LEqual(I1TD, 3)) { |
| 453 | if(LEqual(I2TD, 3)) { |
| 454 | if(LEqual(I3TD, 3)) { |
| 455 | if(LEqual(U0TD, 3)) { |
| 456 | if(LEqual(U1TD, 3)) { |
Marshall Dawson | e0fd9a6 | 2019-07-09 18:12:03 -0500 | [diff] [blame] | 457 | Store(Zero, PG2_) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 458 | } |
| 459 | } |
| 460 | } |
| 461 | } |
| 462 | } |
| 463 | } |
| 464 | Release(FDAS) |
| 465 | } |
| 466 | |
| 467 | Method(FPTS,0, Serialized) /* FCH _PTS */ |
| 468 | { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | Method(FWAK,0, Serialized) /* FCH _WAK */ |
| 472 | { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 473 | if(LEqual(\UT0E, zero)) { |
| 474 | if(LNotEqual(U0TD, 0x03)) { |
| 475 | FDDC(11, 3) |
| 476 | } |
| 477 | } |
| 478 | if(LEqual(\UT1E, zero)) { |
| 479 | if(LNotEqual(U1TD, 0x03)) { |
| 480 | FDDC(12, 3) |
| 481 | } |
| 482 | } |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 483 | if(LEqual(\IC2E, zero)) { |
| 484 | if(LNotEqual(I2TD, 0x03)) { |
| 485 | FDDC(7, 3) |
| 486 | } |
| 487 | } |
| 488 | if(LEqual(\IC3E, zero)) { |
| 489 | if(LNotEqual(I3TD, 0x03)) { |
| 490 | FDDC(8, 3) |
| 491 | } |
| 492 | } |
| 493 | } |
| 494 | |
| 495 | /* |
| 496 | * Helper for setting a bit in AOACxA0 PwrGood Control |
| 497 | * Arg0: bit to set or clear |
| 498 | * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0] |
| 499 | */ |
| 500 | Method(PWGC,2, Serialized) |
| 501 | { |
| 502 | And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */ |
| 503 | if(Arg1) { |
| 504 | Or(Arg0, Local0, Local0) |
| 505 | } else { |
| 506 | Not(Arg0, Local1) |
| 507 | And(Local1, Local0, Local0) |
| 508 | } |
| 509 | Store(Local0, PGA3) |
| 510 | if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */ |
| 511 | Store(PGA3, Local0) |
| 512 | And(Arg0, Local0, Local0) |
| 513 | while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */ |
| 514 | Store(PGA3, Local0) |
| 515 | And(Arg0, Local0, Local0) |
| 516 | } |
| 517 | } |
| 518 | } |