Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <delay.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 9 | #include <string.h> |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 10 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 11 | #include "chip.h" |
| 12 | #include "pch.h" |
| 13 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 14 | int pch_silicon_revision(void) |
| 15 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 16 | static int pch_revision_id = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 17 | |
Antonello Dettori | dac8240 | 2016-09-02 09:14:39 +0200 | [diff] [blame] | 18 | #ifdef __SIMPLE_DEVICE__ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 19 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 20 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 21 | struct device *dev = pcidev_on_root(0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 22 | #endif |
| 23 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 24 | if (pch_revision_id < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 25 | pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 26 | return pch_revision_id; |
| 27 | } |
| 28 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 29 | int pch_silicon_type(void) |
| 30 | { |
Felix Held | 82bd0c3 | 2016-08-13 23:27:15 +0200 | [diff] [blame] | 31 | static int pch_type = -1; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 32 | |
Antonello Dettori | dac8240 | 2016-09-02 09:14:39 +0200 | [diff] [blame] | 33 | #ifdef __SIMPLE_DEVICE__ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 34 | pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 35 | #else |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 36 | struct device *dev = pcidev_on_root(0x1f, 0); |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 37 | #endif |
| 38 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 39 | if (pch_type < 0) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 40 | pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 41 | return pch_type; |
| 42 | } |
| 43 | |
Angel Pons | d703c5b | 2020-08-10 15:25:26 +0200 | [diff] [blame] | 44 | static int pch_silicon_supported(int type, int rev) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 45 | { |
| 46 | int cur_type = pch_silicon_type(); |
| 47 | int cur_rev = pch_silicon_revision(); |
| 48 | |
| 49 | switch (type) { |
| 50 | case PCH_TYPE_CPT: |
| 51 | /* CougarPoint minimum revision */ |
| 52 | if (cur_type == PCH_TYPE_CPT && cur_rev >= rev) |
| 53 | return 1; |
| 54 | /* PantherPoint any revision */ |
| 55 | if (cur_type == PCH_TYPE_PPT) |
| 56 | return 1; |
| 57 | break; |
| 58 | |
| 59 | case PCH_TYPE_PPT: |
| 60 | /* PantherPoint minimum revision */ |
| 61 | if (cur_type == PCH_TYPE_PPT && cur_rev >= rev) |
| 62 | return 1; |
| 63 | break; |
| 64 | } |
| 65 | |
| 66 | return 0; |
| 67 | } |
| 68 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 69 | #define IOBP_RETRY 1000 |
| 70 | static inline int iobp_poll(void) |
| 71 | { |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 72 | unsigned int try = IOBP_RETRY; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 73 | u32 data; |
| 74 | |
| 75 | while (try--) { |
| 76 | data = RCBA32(IOBPS); |
| 77 | if ((data & 1) == 0) |
| 78 | return 1; |
| 79 | udelay(10); |
| 80 | } |
| 81 | |
| 82 | printk(BIOS_ERR, "IOBP timeout\n"); |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) |
| 87 | { |
| 88 | u32 data; |
| 89 | |
| 90 | /* Set the address */ |
| 91 | RCBA32(IOBPIRI) = address; |
| 92 | |
| 93 | /* READ OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 94 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 95 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 96 | else |
| 97 | RCBA32(IOBPS) = IOBPS_READ_AX; |
| 98 | if (!iobp_poll()) |
| 99 | return; |
| 100 | |
| 101 | /* Read IOBP data */ |
| 102 | data = RCBA32(IOBPD); |
| 103 | if (!iobp_poll()) |
| 104 | return; |
| 105 | |
| 106 | /* Check for successful transaction */ |
| 107 | if ((RCBA32(IOBPS) & 0x6) != 0) { |
| 108 | printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address); |
| 109 | return; |
| 110 | } |
| 111 | |
| 112 | /* Update the data */ |
| 113 | data &= andvalue; |
| 114 | data |= orvalue; |
| 115 | |
| 116 | /* WRITE OPCODE */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 117 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0)) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 118 | RCBA32(IOBPS) = IOBPS_RW_BX; |
| 119 | else |
| 120 | RCBA32(IOBPS) = IOBPS_WRITE_AX; |
| 121 | if (!iobp_poll()) |
| 122 | return; |
| 123 | |
| 124 | /* Write IOBP data */ |
| 125 | RCBA32(IOBPD) = data; |
| 126 | if (!iobp_poll()) |
| 127 | return; |
| 128 | } |
| 129 | |
Kyösti Mälkki | 21d6a27 | 2019-11-05 18:50:38 +0200 | [diff] [blame] | 130 | #ifndef __SIMPLE_DEVICE__ |
Frans Hendriks | e6bf51f | 2019-05-01 10:48:31 +0200 | [diff] [blame] | 131 | /* Set bit in function disable register to hide this device */ |
Martin Roth | ff744bf | 2019-10-23 21:46:03 -0600 | [diff] [blame] | 132 | static void pch_hide_devfn(unsigned int devfn) |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 133 | { |
| 134 | switch (devfn) { |
Patrick Rudolph | 403f433 | 2019-07-14 17:43:52 +0200 | [diff] [blame] | 135 | case PCI_DEVFN(20, 0): /* xHCI */ |
| 136 | if (pch_silicon_type() == PCH_TYPE_PPT) { |
| 137 | /* on CPT this bit is reserved */ |
| 138 | RCBA32_OR(FD, PCH_DISABLE_XHCI); |
| 139 | } |
| 140 | break; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 141 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 142 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 143 | break; |
| 144 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 145 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 146 | break; |
| 147 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 148 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 149 | break; |
| 150 | case PCI_DEVFN(22, 3): /* KT */ |
| 151 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 152 | break; |
| 153 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
Nico Huber | 6760e0b | 2019-11-17 02:34:53 +0100 | [diff] [blame] | 154 | /* BUC is already handled in `early_pch.c`. */ |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 155 | break; |
| 156 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 157 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 158 | break; |
| 159 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 160 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 161 | break; |
| 162 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 163 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 164 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 165 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 166 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 167 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 168 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 169 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 170 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 171 | break; |
| 172 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 173 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 174 | break; |
| 175 | case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ |
| 176 | RCBA32_OR(FD, PCH_DISABLE_P2P); |
| 177 | break; |
| 178 | case PCI_DEVFN(31, 0): /* LPC */ |
| 179 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 180 | break; |
| 181 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 182 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 183 | break; |
| 184 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 185 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 186 | break; |
| 187 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 188 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 189 | break; |
| 190 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 191 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 192 | break; |
| 193 | } |
| 194 | } |
| 195 | |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 196 | /* Check if any port in set X to X+3 is enabled */ |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 197 | static int pch_pcie_check_set_enabled(struct device *dev) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 198 | { |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 199 | struct device *port; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 200 | int port_func; |
| 201 | int dev_func = PCI_FUNC(dev->path.pci.devfn); |
| 202 | |
| 203 | printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev)); |
| 204 | |
| 205 | /* Go through static device tree list of devices |
| 206 | * because enumeration is still in progress */ |
| 207 | for (port = all_devices; port; port = port->next) { |
| 208 | /* Only care about PCIe root ports */ |
| 209 | if (PCI_SLOT(port->path.pci.devfn) != |
| 210 | PCI_SLOT(dev->path.pci.devfn)) |
| 211 | continue; |
| 212 | |
| 213 | /* Check if port is in range and enabled */ |
| 214 | port_func = PCI_FUNC(port->path.pci.devfn); |
| 215 | if (port_func >= dev_func && |
| 216 | port_func < (dev_func + 4) && |
| 217 | port->enabled) |
| 218 | return 1; |
| 219 | } |
| 220 | |
| 221 | /* None of the ports in this set are enabled */ |
| 222 | return 0; |
| 223 | } |
| 224 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 225 | /* RPFN is a write-once register so keep a copy until it is written */ |
| 226 | static u32 new_rpfn; |
| 227 | |
| 228 | /* Swap function numbers assigned to two PCIe Root Ports */ |
| 229 | static void pch_pcie_function_swap(u8 old_fn, u8 new_fn) |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 230 | { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 231 | u32 old_rpfn = new_rpfn; |
| 232 | |
| 233 | printk(BIOS_DEBUG, "PCH: Remap PCIe function %d to %d\n", |
| 234 | old_fn, new_fn); |
| 235 | |
| 236 | new_rpfn &= ~(RPFN_FNMASK(old_fn) | RPFN_FNMASK(new_fn)); |
| 237 | |
| 238 | /* Old function set to new function and disabled */ |
| 239 | new_rpfn |= RPFN_FNSET(old_fn, RPFN_FNGET(old_rpfn, new_fn)); |
| 240 | new_rpfn |= RPFN_FNSET(new_fn, RPFN_FNGET(old_rpfn, old_fn)); |
| 241 | } |
| 242 | |
| 243 | /* Update devicetree with new Root Port function number assignment */ |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 244 | static void pch_pcie_devicetree_update( |
| 245 | struct southbridge_intel_bd82x6x_config *config) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 246 | { |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 247 | struct device *dev; |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 248 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 249 | /* |
| 250 | * hotplug map should also be updated along with their |
| 251 | * corresponding port |
| 252 | */ |
| 253 | u8 new_hotplug_map[sizeof(config->pcie_hotplug_map)]; |
| 254 | |
| 255 | /* |
| 256 | * Slots that didn't move need the hotplug setting copied too, |
| 257 | * so "new_hotplug_map" is initialized with the values of the old map. |
| 258 | */ |
| 259 | memcpy(new_hotplug_map, config->pcie_hotplug_map, |
| 260 | sizeof(new_hotplug_map)); |
| 261 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 262 | /* Update the function numbers in the static devicetree */ |
| 263 | for (dev = all_devices; dev; dev = dev->next) { |
| 264 | u8 new_devfn; |
| 265 | |
| 266 | /* Only care about PCH PCIe root ports */ |
| 267 | if (PCI_SLOT(dev->path.pci.devfn) != |
| 268 | PCH_PCIE_DEV_SLOT) |
| 269 | continue; |
| 270 | |
| 271 | /* Determine the new devfn for this port */ |
| 272 | new_devfn = PCI_DEVFN(PCH_PCIE_DEV_SLOT, |
| 273 | RPFN_FNGET(new_rpfn, |
| 274 | PCI_FUNC(dev->path.pci.devfn))); |
| 275 | |
| 276 | if (dev->path.pci.devfn != new_devfn) { |
| 277 | printk(BIOS_DEBUG, |
| 278 | "PCH: PCIe map %02x.%1x -> %02x.%1x\n", |
| 279 | PCI_SLOT(dev->path.pci.devfn), |
| 280 | PCI_FUNC(dev->path.pci.devfn), |
| 281 | PCI_SLOT(new_devfn), PCI_FUNC(new_devfn)); |
| 282 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 283 | /* |
| 284 | * Copy the flag to its new position along with |
| 285 | * the corresponding port |
| 286 | */ |
| 287 | new_hotplug_map[PCI_FUNC(new_devfn)] = |
| 288 | config->pcie_hotplug_map |
| 289 | [PCI_FUNC(dev->path.pci.devfn)]; |
| 290 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 291 | dev->path.pci.devfn = new_devfn; |
| 292 | } |
| 293 | } |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 294 | |
| 295 | /* Copy the updated map back to its place */ |
| 296 | memcpy(config->pcie_hotplug_map, new_hotplug_map, |
| 297 | sizeof(new_hotplug_map)); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 298 | } |
| 299 | |
| 300 | /* Special handling for PCIe Root Port devices */ |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 301 | static void pch_pcie_enable(struct device *dev) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 302 | { |
| 303 | struct southbridge_intel_bd82x6x_config *config = dev->chip_info; |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 304 | |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 305 | if (!config) |
| 306 | return; |
| 307 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 308 | /* |
| 309 | * Save a copy of the Root Port Function Number map when |
| 310 | * starting to walk the list of PCIe Root Ports so it can |
| 311 | * be updated locally and written out when the last port |
| 312 | * has been processed. |
| 313 | */ |
| 314 | if (PCI_FUNC(dev->path.pci.devfn) == 0) { |
| 315 | new_rpfn = RCBA32(RPFN); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 316 | |
| 317 | /* |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 318 | * Enable Root Port coalescing if the first port is disabled |
| 319 | * or the other devices will not be enumerated by the OS. |
| 320 | */ |
| 321 | if (!dev->enabled) |
Angel Pons | af4bd56 | 2021-12-28 13:05:56 +0100 | [diff] [blame] | 322 | config->pcie_port_coalesce = true; |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 323 | |
| 324 | if (config->pcie_port_coalesce) |
| 325 | printk(BIOS_INFO, |
| 326 | "PCH: PCIe Root Port coalescing is enabled\n"); |
| 327 | } |
| 328 | |
| 329 | if (!dev->enabled) { |
Marc Jones | ef6b08c | 2012-06-15 23:03:15 -0600 | [diff] [blame] | 330 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 331 | |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 332 | /* |
| 333 | * PCIE Power Savings for PantherPoint and CougarPoint/B1+ |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 334 | * |
| 335 | * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1 |
| 336 | * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1 |
| 337 | * |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 338 | * This check is done here instead of PCIe driver |
| 339 | * because the PCIe driver enable() handler is not |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 340 | * called unless the device is enabled. |
| 341 | */ |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 342 | if ((PCI_FUNC(dev->path.pci.devfn) == 0 || |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 343 | PCI_FUNC(dev->path.pci.devfn) == 4)) { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 344 | /* Handle workaround for PPT and CPT/B1+ */ |
| 345 | if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && |
| 346 | !pch_pcie_check_set_enabled(dev)) { |
Angel Pons | c803f65 | 2020-06-07 22:09:01 +0200 | [diff] [blame] | 347 | pci_or_config8(dev, 0xe2, 1); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 348 | } |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 349 | |
| 350 | /* |
| 351 | * Enable Clock Gating for shared PCIe resources |
| 352 | * before disabling this particular port. |
| 353 | */ |
| 354 | pci_write_config8(dev, 0xe1, 0x3c); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | /* Ensure memory, io, and bus master are all disabled */ |
Angel Pons | c803f65 | 2020-06-07 22:09:01 +0200 | [diff] [blame] | 358 | pci_and_config16(dev, PCI_COMMAND, |
| 359 | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 360 | |
| 361 | /* Do not claim downstream transactions for PCIe ports */ |
| 362 | new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); |
| 363 | |
| 364 | /* Hide this device if possible */ |
| 365 | pch_hide_devfn(dev->path.pci.devfn); |
| 366 | } else { |
| 367 | int fn; |
| 368 | |
| 369 | /* |
| 370 | * Check if there is a lower disabled port to swap with this |
| 371 | * port in order to maintain linear order starting at zero. |
| 372 | */ |
| 373 | if (config->pcie_port_coalesce) { |
| 374 | for (fn=0; fn < PCI_FUNC(dev->path.pci.devfn); fn++) { |
| 375 | if (!(new_rpfn & RPFN_HIDE(fn))) |
| 376 | continue; |
| 377 | |
| 378 | /* Swap places with this function */ |
| 379 | pch_pcie_function_swap( |
| 380 | PCI_FUNC(dev->path.pci.devfn), fn); |
| 381 | break; |
| 382 | } |
| 383 | } |
| 384 | |
| 385 | /* Enable SERR */ |
Elyes HAOUAS | 729c069 | 2020-04-28 19:50:44 +0200 | [diff] [blame] | 386 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 387 | } |
| 388 | |
| 389 | /* |
| 390 | * When processing the last PCIe root port we can now |
| 391 | * update the Root Port Function Number and Hide register. |
| 392 | */ |
| 393 | if (PCI_FUNC(dev->path.pci.devfn) == 7) { |
| 394 | printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n", |
| 395 | RCBA32(RPFN), new_rpfn); |
| 396 | RCBA32(RPFN) = new_rpfn; |
| 397 | |
| 398 | /* Update static devictree with new function numbers */ |
| 399 | if (config->pcie_port_coalesce) |
Bill XIE | 8c57d09 | 2017-08-25 22:07:12 +0800 | [diff] [blame] | 400 | pch_pcie_devicetree_update(config); |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 401 | } |
| 402 | } |
| 403 | |
Elyes HAOUAS | dc03528 | 2018-09-18 13:28:49 +0200 | [diff] [blame] | 404 | void pch_enable(struct device *dev) |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 405 | { |
Duncan Laurie | b9fe01c | 2012-04-27 10:30:51 -0700 | [diff] [blame] | 406 | /* PCH PCIe Root Ports get special handling */ |
| 407 | if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) |
| 408 | return pch_pcie_enable(dev); |
| 409 | |
| 410 | if (!dev->enabled) { |
| 411 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 412 | |
| 413 | /* Ensure memory, io, and bus master are all disabled */ |
Angel Pons | c803f65 | 2020-06-07 22:09:01 +0200 | [diff] [blame] | 414 | pci_and_config16(dev, PCI_COMMAND, |
| 415 | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 416 | |
| 417 | /* Hide this device if possible */ |
| 418 | pch_hide_devfn(dev->path.pci.devfn); |
| 419 | } else { |
| 420 | /* Enable SERR */ |
Elyes HAOUAS | 729c069 | 2020-04-28 19:50:44 +0200 | [diff] [blame] | 421 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 422 | } |
| 423 | } |
| 424 | |
| 425 | struct chip_operations southbridge_intel_bd82x6x_ops = { |
Stefan Reinauer | 9ca1c0a | 2012-07-25 16:10:36 -0700 | [diff] [blame] | 426 | CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge") |
Stefan Reinauer | 8e07382 | 2012-04-04 00:07:22 +0200 | [diff] [blame] | 427 | .enable_dev = pch_enable, |
| 428 | }; |
Marc Jones | 783f226 | 2013-02-11 14:36:35 -0700 | [diff] [blame] | 429 | #endif |