commit dc0352835525598e0c72d6fbcfba428113847e59
author Elyes HAOUAS <ehaouas@noos.fr> Tue Sep 18 13:28:49 2018 +0200
committer Martin Roth <martinroth@google.com> Fri Sep 21 14:13:02 2018 +0000
tree 64b95047aa790594ce7e29a3f8226b0844834b72
parent 756a0bd2fe05ce187b3702805cfc78f60cc64477

sb/intel/bd82x6x: Don't use device_t

Use of device_t is deprecated.

Change-Id: I4909ebffc978f537bbf6269d9e27dbaca43daa10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

src/southbridge/intel/bd82x6x/pch.c

diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 79cf6bf..00265d0 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -208,9 +208,9 @@
 }
 
 /* Check if any port in set X to X+3 is enabled */
-static int pch_pcie_check_set_enabled(device_t dev)
+static int pch_pcie_check_set_enabled(struct device *dev)
 {
-	device_t port;
+	struct device *port;
 	int port_func;
 	int dev_func = PCI_FUNC(dev->path.pci.devfn);
 
@@ -258,7 +258,7 @@
 static void pch_pcie_devicetree_update(
 		struct southbridge_intel_bd82x6x_config *config)
 {
-	device_t dev;
+	struct device *dev;
 
 	/*
 	 * hotplug map should also be updated along with their
@@ -312,7 +312,7 @@
 }
 
 /* Special handling for PCIe Root Port devices */
-static void pch_pcie_enable(device_t dev)
+static void pch_pcie_enable(struct device *dev)
 {
 	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 	u32 reg32;
@@ -422,7 +422,7 @@
 	}
 }
 
-void pch_enable(device_t dev)
+void pch_enable(struct device *dev)
 {
 	u32 reg32;