| Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Arthur Heymans | d0310fa | 2019-10-02 00:21:01 +0200 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/pci_ops.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_def.h> |
| 9 | #include "pch.h" |
| 10 | |
| 11 | /* Set bit in function disable register to hide this device */ |
| 12 | static void pch_disable_devfn(struct device *dev) |
| 13 | { |
| 14 | switch (dev->path.pci.devfn) { |
| 15 | case PCI_DEVFN(22, 0): /* MEI #1 */ |
| 16 | RCBA32_OR(FD2, PCH_DISABLE_MEI1); |
| 17 | break; |
| 18 | case PCI_DEVFN(22, 1): /* MEI #2 */ |
| 19 | RCBA32_OR(FD2, PCH_DISABLE_MEI2); |
| 20 | break; |
| 21 | case PCI_DEVFN(22, 2): /* IDE-R */ |
| 22 | RCBA32_OR(FD2, PCH_DISABLE_IDER); |
| 23 | break; |
| 24 | case PCI_DEVFN(22, 3): /* KT */ |
| 25 | RCBA32_OR(FD2, PCH_DISABLE_KT); |
| 26 | break; |
| 27 | case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ |
| 28 | RCBA32_OR(BUC, PCH_DISABLE_GBE); |
| 29 | break; |
| 30 | case PCI_DEVFN(26, 0): /* EHCI #2 */ |
| 31 | RCBA32_OR(FD, PCH_DISABLE_EHCI2); |
| 32 | break; |
| 33 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 34 | RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); |
| 35 | break; |
| 36 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 37 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 38 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 39 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 40 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 41 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 42 | case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ |
| 43 | case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ |
| 44 | RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); |
| 45 | break; |
| 46 | case PCI_DEVFN(29, 0): /* EHCI #1 */ |
| 47 | RCBA32_OR(FD, PCH_DISABLE_EHCI1); |
| 48 | break; |
| 49 | case PCI_DEVFN(31, 0): /* LPC */ |
| 50 | RCBA32_OR(FD, PCH_DISABLE_LPC); |
| 51 | break; |
| 52 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 53 | RCBA32_OR(FD, PCH_DISABLE_SATA1); |
| 54 | break; |
| 55 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 56 | RCBA32_OR(FD, PCH_DISABLE_SMBUS); |
| 57 | break; |
| 58 | case PCI_DEVFN(31, 5): /* SATA #22 */ |
| 59 | RCBA32_OR(FD, PCH_DISABLE_SATA2); |
| 60 | break; |
| 61 | case PCI_DEVFN(31, 6): /* Thermal Subsystem */ |
| 62 | RCBA32_OR(FD, PCH_DISABLE_THERMAL); |
| 63 | break; |
| 64 | } |
| 65 | } |
| 66 | |
| 67 | void pch_enable(struct device *dev) |
| 68 | { |
| 69 | u32 reg32; |
| 70 | |
| 71 | if (!dev->enabled) { |
| 72 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 73 | |
| 74 | /* Ensure memory, io, and bus master are all disabled */ |
| 75 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 76 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 77 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 78 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 79 | |
| 80 | /* Disable this device if possible */ |
| 81 | pch_disable_devfn(dev); |
| 82 | } else { |
| 83 | /* Enable SERR */ |
| 84 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 85 | reg32 |= PCI_COMMAND_SERR; |
| 86 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | struct chip_operations southbridge_intel_ibexpeak_ops = { |
| 91 | CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge") |
| 92 | .enable_dev = pch_enable, |
| 93 | }; |