Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 5 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or modify |
| 8 | ## it under the terms of the GNU General Public License as published by |
| 9 | ## the Free Software Foundation; version 2 of the License. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 16 | |
| 17 | config SOC_INTEL_FSP_BAYTRAIL |
| 18 | bool |
| 19 | help |
| 20 | Bay Trail I part support using the Intel FSP. |
| 21 | |
| 22 | if SOC_INTEL_FSP_BAYTRAIL |
| 23 | |
| 24 | config CPU_SPECIFIC_OPTIONS |
| 25 | def_bool y |
Aaron Durbin | 15e439a | 2016-07-13 23:22:01 -0500 | [diff] [blame] | 26 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 27 | select ARCH_BOOTBLOCK_X86_32 |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 28 | select ARCH_VERSTAGE_X86_32 |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 29 | select ARCH_ROMSTAGE_X86_32 |
| 30 | select ARCH_RAMSTAGE_X86_32 |
Kayalvizhi Dhandapani | 454625c | 2014-10-07 14:34:01 -0400 | [diff] [blame] | 31 | select HAVE_SMI_HANDLER |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 32 | select SOUTHBRIDGE_INTEL_COMMON_RESET |
Kyösti Mälkki | 7904e72 | 2018-06-03 14:55:10 +0300 | [diff] [blame] | 33 | select NO_RELOCATABLE_RAMSTAGE |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 34 | select PARALLEL_MP |
| 35 | select REG_SCRIPT |
| 36 | select SMP |
| 37 | select SPI_FLASH |
| 38 | select SSE2 |
| 39 | select TSC_CONSTANT_RATE |
| 40 | select TSC_SYNC_MFENCE |
| 41 | select UDELAY_TSC |
Kyösti Mälkki | c804f31 | 2019-07-06 06:49:37 +0300 | [diff] [blame] | 42 | select TSC_MONOTONIC_TIMER |
Alexandru Gagniuc | eb73a21 | 2015-02-18 14:18:01 -0600 | [diff] [blame] | 43 | select SUPPORT_CPU_UCODE_IN_CBFS |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 44 | select MICROCODE_BLOB_NOT_HOOKED_UP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 45 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame] | 46 | select HAVE_SPI_CONSOLE_SUPPORT |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 47 | |
Martin Roth | 0307e0a | 2015-11-05 08:06:54 -0700 | [diff] [blame] | 48 | # Microcode header files are delivered in FSP package |
| 49 | select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN |
| 50 | |
Philipp Deppenwiese | 405a0f5 | 2018-07-30 01:31:33 +0200 | [diff] [blame] | 51 | config VBOOT |
| 52 | select VBOOT_STARTS_IN_ROMSTAGE |
| 53 | |
Werner Zeh | b5a374d | 2015-02-10 10:16:12 +0100 | [diff] [blame] | 54 | config SOC_INTEL_FSP_BAYTRAIL_MD |
| 55 | bool |
| 56 | default n |
| 57 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 58 | config BOOTBLOCK_CPU_INIT |
| 59 | string |
| 60 | default "soc/intel/fsp_baytrail/bootblock/bootblock.c" |
| 61 | |
| 62 | config MMCONF_BASE_ADDRESS |
| 63 | hex |
Martin Roth | e96f4b1 | 2014-06-22 22:05:24 -0600 | [diff] [blame] | 64 | default 0xe0000000 |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 65 | |
| 66 | config MAX_CPUS |
| 67 | int |
| 68 | default 4 |
| 69 | |
| 70 | config CPU_ADDR_BITS |
| 71 | int |
| 72 | default 36 |
| 73 | |
| 74 | config SMM_TSEG_SIZE |
| 75 | hex |
David Imhoff | 326a037 | 2015-04-22 17:24:26 +0200 | [diff] [blame] | 76 | default 0x800000 |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 77 | help |
| 78 | This is set by the FSP |
| 79 | |
| 80 | config SMM_RESERVED_SIZE |
| 81 | hex |
| 82 | default 0x100000 |
| 83 | |
| 84 | config VGA_BIOS_ID |
| 85 | string |
| 86 | default "8086,0f31" |
| 87 | help |
| 88 | This is the default PCI ID for the Bay Trail graphics |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 89 | devices. This string names the vbios ROM in cbfs. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 90 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 91 | config ENABLE_BUILTIN_COM1 |
| 92 | bool "Enable built-in legacy Serial Port" |
| 93 | help |
| 94 | The Baytrail SOC has one legacy serial port. Choose this option to |
| 95 | configure the pads and enable it. This serial port can be used for |
| 96 | the debug console. |
| 97 | |
| 98 | config VGA_BIOS_FILE |
| 99 | string |
Martin Roth | 0baaa2d | 2014-06-12 12:20:26 -0600 | [diff] [blame] | 100 | default "../intel/cpu/baytrail/vbios/Vga.dat" if VGA_BIOS |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 101 | |
Martin Roth | 0307e0a | 2015-11-05 08:06:54 -0700 | [diff] [blame] | 102 | config CPU_MICROCODE_HEADER_FILES |
| 103 | string |
| 104 | default "../intel/cpu/baytrail/microcode/M0130673322.h ../intel/cpu/baytrail/microcode/M0130679901.h ../intel/cpu/baytrail/microcode/M0230672228.h" |
| 105 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 106 | ## Baytrail Specific FSP Kconfig |
| 107 | source src/soc/intel/fsp_baytrail/fsp/Kconfig |
| 108 | |
| 109 | endif #SOC_INTEL_FSP_BAYTRAIL |