blob: 7ddf6257ac0ad697ec3b81d1ea64cf8387f2c54e [file] [log] [blame]
Angel Pons32abdd62020-04-05 15:47:03 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Aamir Bohra3ee54bb2018-10-17 11:55:01 +05302
Aamir Bohra2ee8fe02018-06-30 23:39:27 +05303#include <assert.h>
Aamir Bohra3ee54bb2018-10-17 11:55:01 +05304#include <console/console.h>
5#include <fsp/util.h>
Michael Niewöhner7736bfc2019-10-22 23:05:06 +02006#include <intelblocks/cpulib.h>
Aamir Bohra2ee8fe02018-06-30 23:39:27 +05307#include <soc/iomap.h>
8#include <soc/pci_devs.h>
Aamir Bohra3ee54bb2018-10-17 11:55:01 +05309#include <soc/romstage.h>
Subrata Banikdf29d232019-07-05 16:00:38 +053010#include <soc/soc_chip.h>
Aamir Bohra3ee54bb2018-10-17 11:55:01 +053011
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053012static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
13 const struct soc_intel_icelake_config *config)
14{
15 unsigned int i;
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053016 uint32_t mask = 0;
17
Subrata Banik1a5d4122021-06-21 18:07:50 +053018 /*
19 * If IGD is enabled, set IGD stolen size to 60MB.
20 * Otherwise, skip IGD init in FSP.
21 */
22 m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
23 m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
Subrata Banik9fe5dde2019-07-12 18:32:55 +053024
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053025 m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
26 m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
27 m_cfg->SaGv = config->SaGv;
28 m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
29 m_cfg->RMT = config->RMT;
30 m_cfg->SkipMbpHob = 1;
Subrata Banikc796a8f2019-07-01 10:21:11 +053031
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053032 /* If Audio Codec is enabled, enable FSP UPD */
Subrata Banik1a5d4122021-06-21 18:07:50 +053033 m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053034
35 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
36 if (config->PcieRpEnable[i])
37 mask |= (1 << i);
38 }
39 m_cfg->PcieRpEnableMask = mask;
Michael Niewöhner490546f2020-09-15 12:20:08 +020040 m_cfg->PrmrrSize = get_valid_prmrr_size();
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053041 m_cfg->EnableC6Dram = config->enable_c6dram;
42 /* Disable BIOS Guard */
43 m_cfg->BiosGuard = 0;
44 /* Disable Cpu Ratio Override temporary. */
45 m_cfg->CpuRatio = 0;
46 m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
47 m_cfg->PcdDebugInterfaceFlags =
48 CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
49
50 /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
51 m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
52}
53
Aamir Bohra3ee54bb2018-10-17 11:55:01 +053054void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
55{
Kyösti Mälkki8950cfb2019-07-13 22:16:25 +030056 const struct soc_intel_icelake_config *config;
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053057 FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
58
Kyösti Mälkkid5f645c2019-09-28 00:20:27 +030059 config = config_of_soc();
Kyösti Mälkki8950cfb2019-07-13 22:16:25 +030060
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053061 soc_memory_init_params(m_cfg, config);
62
63 /* Enable SMBus controller based on config */
64 m_cfg->SmbusEnable = config->SmbusEnable;
65 /* Set debug probe type */
Subrata Banik56626cf2020-02-27 19:39:22 +053066 m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT;
Aamir Bohra2ee8fe02018-06-30 23:39:27 +053067
68 /* Vt-D config */
69 m_cfg->VtdDisable = 0;
70
71 mainboard_memory_init_params(mupd);
Aamir Bohra3ee54bb2018-10-17 11:55:01 +053072}
73
74__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
75{
76 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
77}