Angel Pons | 32abdd6 | 2020-04-05 15:47:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 6 | #include <fsp/api.h> |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 7 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 8 | #include <option.h> |
Aamir Bohra | b9c1850 | 2019-07-08 18:23:37 +0530 | [diff] [blame] | 9 | #include <intelblocks/lpss.h> |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 10 | #include <intelblocks/xdci.h> |
| 11 | #include <soc/intel/common/vbt.h> |
| 12 | #include <soc/pci_devs.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | #include <soc/ramstage.h> |
Subrata Banik | df29d23 | 2019-07-05 16:00:38 +0530 | [diff] [blame] | 14 | #include <soc/soc_chip.h> |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 15 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 16 | #include <types.h> |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 17 | #include <fsp/ppi/mp_service_ppi.h> |
| 18 | |
| 19 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 20 | { |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 21 | const struct soc_intel_icelake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 22 | config = config_of_soc(); |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 23 | |
| 24 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
| 25 | params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
| 26 | |
| 27 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
| 28 | params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 29 | params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 30 | params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
| 31 | } |
| 32 | |
| 33 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
| 34 | params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
| 35 | } |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 36 | |
| 37 | /* UPD parameters to be initialized before SiliconInit */ |
| 38 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 39 | { |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 40 | int i; |
| 41 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 42 | |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 43 | struct soc_intel_icelake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 44 | config = config_of_soc(); |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 45 | |
| 46 | /* Parse device tree and enable/disable devices */ |
| 47 | parse_devicetree(params); |
| 48 | |
| 49 | /* Load VBT before devicetree-specific config. */ |
| 50 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 51 | |
Subrata Banik | 19895f8 | 2020-07-30 16:15:10 +0530 | [diff] [blame] | 52 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 53 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 54 | params->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 55 | |
| 56 | mainboard_silicon_init_params(params); |
| 57 | |
Subrata Banik | 1a5d412 | 2021-06-21 18:07:50 +0530 | [diff] [blame] | 58 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Subrata Banik | 9fe5dde | 2019-07-12 18:32:55 +0530 | [diff] [blame] | 59 | |
Benjamin Doron | bbb8123 | 2020-06-28 02:43:53 +0000 | [diff] [blame] | 60 | params->PavpEnable = CONFIG(PAVP); |
| 61 | |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 62 | /* Unlock upper 8 bytes of RTC RAM */ |
| 63 | params->PchLockDownRtcMemoryLock = 0; |
| 64 | |
| 65 | params->CnviBtAudioOffload = config->CnviBtAudioOffload; |
| 66 | /* SATA */ |
Subrata Banik | 1a5d412 | 2021-06-21 18:07:50 +0530 | [diff] [blame] | 67 | params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 68 | if (params->SataEnable) { |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 69 | params->SataMode = config->SataMode; |
| 70 | params->SataSalpSupport = config->SataSalpSupport; |
| 71 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 72 | sizeof(params->SataPortsEnable)); |
| 73 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 74 | sizeof(params->SataPortsDevSlp)); |
| 75 | } |
| 76 | |
| 77 | /* Lan */ |
Subrata Banik | 1a5d412 | 2021-06-21 18:07:50 +0530 | [diff] [blame] | 78 | params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 79 | |
| 80 | /* Audio */ |
| 81 | params->PchHdaDspEnable = config->PchHdaDspEnable; |
| 82 | params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; |
| 83 | params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; |
| 84 | params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; |
| 85 | params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; |
| 86 | params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; |
| 87 | params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; |
| 88 | params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; |
| 89 | params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; |
| 90 | params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; |
| 91 | params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; |
| 92 | |
| 93 | /* disable Legacy PME */ |
| 94 | memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |
| 95 | |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 96 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 97 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 98 | params->Enable8254ClockGating = !use_8254; |
| 99 | params->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 100 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 101 | /* |
| 102 | * Legacy PM ACPI Timer (and TCO Timer) |
| 103 | * This *must* be 1 in any case to keep FSP from |
| 104 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 105 | * 2) disabling the PM ACPI Timer. |
| 106 | * We handle both by ourself! |
| 107 | */ |
| 108 | params->EnableTcoTimer = 1; |
| 109 | |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 110 | /* S0ix */ |
| 111 | params->PchPmSlpS0Enable = config->s0ix_enable; |
| 112 | |
| 113 | /* USB */ |
| 114 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 115 | params->PortUsb20Enable[i] = |
| 116 | config->usb2_ports[i].enable; |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 117 | params->Usb2PhyPetxiset[i] = |
| 118 | config->usb2_ports[i].pre_emp_bias; |
| 119 | params->Usb2PhyTxiset[i] = |
| 120 | config->usb2_ports[i].tx_bias; |
| 121 | params->Usb2PhyPredeemp[i] = |
| 122 | config->usb2_ports[i].tx_emp_enable; |
| 123 | params->Usb2PhyPehalfbit[i] = |
| 124 | config->usb2_ports[i].pre_emp_bit; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 125 | |
| 126 | if (config->usb2_ports[i].enable) |
| 127 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 128 | else |
| 129 | params->Usb2OverCurrentPin[i] = 0xff; |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 133 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 134 | if (config->usb3_ports[i].enable) { |
| 135 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
| 136 | } else { |
| 137 | params->Usb3OverCurrentPin[i] = 0xff; |
| 138 | } |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 139 | if (config->usb3_ports[i].tx_de_emp) { |
| 140 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 141 | params->Usb3HsioTxDeEmph[i] = |
| 142 | config->usb3_ports[i].tx_de_emp; |
| 143 | } |
| 144 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 145 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 146 | params->Usb3HsioTxDownscaleAmp[i] = |
| 147 | config->usb3_ports[i].tx_downscale_amp; |
| 148 | } |
| 149 | } |
| 150 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 151 | params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 152 | |
| 153 | /* PCI Express */ |
| 154 | for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { |
| 155 | if (config->PcieClkSrcUsage[i] == 0) |
| 156 | config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; |
| 157 | } |
| 158 | memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, |
| 159 | sizeof(config->PcieClkSrcUsage)); |
| 160 | memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, |
| 161 | sizeof(config->PcieClkSrcClkReq)); |
| 162 | |
| 163 | /* eMMC */ |
Subrata Banik | 1a5d412 | 2021-06-21 18:07:50 +0530 | [diff] [blame] | 164 | params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
| 165 | if (params->ScsEmmcEnabled) { |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 166 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 167 | params->EmmcUseCustomDlls = config->EmmcUseCustomDlls; |
| 168 | if (config->EmmcUseCustomDlls == 1) { |
| 169 | params->EmmcTxCmdDelayRegValue = |
| 170 | config->EmmcTxCmdDelayRegValue; |
| 171 | params->EmmcTxDataDelay1RegValue = |
| 172 | config->EmmcTxDataDelay1RegValue; |
| 173 | params->EmmcTxDataDelay2RegValue = |
| 174 | config->EmmcTxDataDelay2RegValue; |
| 175 | params->EmmcRxCmdDataDelay1RegValue = |
| 176 | config->EmmcRxCmdDataDelay1RegValue; |
| 177 | params->EmmcRxCmdDataDelay2RegValue = |
| 178 | config->EmmcRxCmdDataDelay2RegValue; |
| 179 | params->EmmcRxStrobeDelayRegValue = |
| 180 | config->EmmcRxStrobeDelayRegValue; |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | /* SD */ |
Subrata Banik | 1a5d412 | 2021-06-21 18:07:50 +0530 | [diff] [blame] | 185 | params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); |
| 186 | params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; |
Aamir Bohra | 2ee8fe0 | 2018-06-30 23:39:27 +0530 | [diff] [blame] | 187 | |
| 188 | params->Heci3Enabled = config->Heci3Enabled; |
| 189 | params->Device4Enable = config->Device4Enable; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | /* Mainboard GPIO Configuration */ |
| 193 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 194 | { |
| 195 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 196 | } |