Angel Pons | 32abdd6 | 2020-04-05 15:47:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 6 | #include <intelblocks/cfg.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 7 | #include <drivers/i2c/designware/dw_i2c.h> |
Subrata Banik | dd5fa02 | 2019-05-15 21:04:37 +0530 | [diff] [blame] | 8 | #include <intelblocks/gpio.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 9 | #include <intelblocks/gspi.h> |
| 10 | #include <stdint.h> |
Subrata Banik | 2df5abc | 2018-11-06 17:07:01 +0530 | [diff] [blame] | 11 | #include <soc/gpe.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 12 | #include <soc/gpio.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | #include <soc/pch.h> |
| 14 | #include <soc/gpio_defs.h> |
| 15 | #include <soc/pci_devs.h> |
| 16 | #include <soc/pmc.h> |
| 17 | #include <soc/serialio.h> |
| 18 | #include <soc/usb.h> |
| 19 | |
| 20 | struct soc_intel_icelake_config { |
| 21 | |
| 22 | /* Common struct containing soc config data required by common code */ |
| 23 | struct soc_intel_common_config common_soc_config; |
| 24 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 25 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 26 | * of the form GPP_[A:G] or GPD. */ |
| 27 | uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 28 | uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 29 | uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 30 | |
| 31 | /* Generic IO decode ranges */ |
| 32 | uint32_t gen1_dec; |
| 33 | uint32_t gen2_dec; |
| 34 | uint32_t gen3_dec; |
| 35 | uint32_t gen4_dec; |
| 36 | |
| 37 | /* Enable S0iX support */ |
| 38 | int s0ix_enable; |
| 39 | /* Enable DPTF support */ |
| 40 | int dptf_enable; |
| 41 | |
| 42 | /* Deep SX enable for both AC and DC */ |
| 43 | int deep_s3_enable_ac; |
| 44 | int deep_s3_enable_dc; |
| 45 | int deep_s5_enable_ac; |
| 46 | int deep_s5_enable_dc; |
| 47 | |
| 48 | /* Deep Sx Configuration |
| 49 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 50 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 51 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 52 | uint32_t deep_sx_config; |
| 53 | |
| 54 | /* TCC activation offset */ |
| 55 | uint32_t tcc_offset; |
| 56 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 57 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
| 58 | * When enabled memory will be training at two different frequencies. |
| 59 | * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ |
| 60 | enum { |
| 61 | SaGv_Disabled, |
| 62 | SaGv_FixedLow, |
| 63 | SaGv_FixedMid, |
| 64 | SaGv_FixedHigh, |
| 65 | SaGv_Enabled, |
| 66 | } SaGv; |
| 67 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 68 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 69 | uint8_t RMT; |
| 70 | |
| 71 | /* USB related */ |
| 72 | struct usb2_port_config usb2_ports[16]; |
| 73 | struct usb3_port_config usb3_ports[10]; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 74 | /* Wake Enable Bitmap for USB2 ports */ |
| 75 | uint16_t usb2_wake_enable_bitmap; |
| 76 | /* Wake Enable Bitmap for USB3 ports */ |
| 77 | uint16_t usb3_wake_enable_bitmap; |
| 78 | |
| 79 | /* SATA related */ |
Aamir Bohra | df47e1c | 2018-07-01 00:13:29 +0530 | [diff] [blame] | 80 | uint8_t SataEnable; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 81 | uint8_t SataMode; |
| 82 | uint8_t SataSalpSupport; |
| 83 | uint8_t SataPortsEnable[8]; |
| 84 | uint8_t SataPortsDevSlp[8]; |
| 85 | |
| 86 | /* Audio related */ |
| 87 | uint8_t PchHdaEnable; |
| 88 | uint8_t PchHdaDspEnable; |
| 89 | |
| 90 | /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ |
| 91 | uint8_t PchHdaAudioLinkHda; |
| 92 | uint8_t PchHdaAudioLinkDmic0; |
| 93 | uint8_t PchHdaAudioLinkDmic1; |
| 94 | uint8_t PchHdaAudioLinkSsp0; |
| 95 | uint8_t PchHdaAudioLinkSsp1; |
| 96 | uint8_t PchHdaAudioLinkSsp2; |
| 97 | uint8_t PchHdaAudioLinkSndw1; |
| 98 | uint8_t PchHdaAudioLinkSndw2; |
| 99 | uint8_t PchHdaAudioLinkSndw3; |
| 100 | uint8_t PchHdaAudioLinkSndw4; |
| 101 | |
| 102 | /* PCIe Root Ports */ |
| 103 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 104 | /* PCIe output clocks type to PCIe devices. |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 105 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 106 | * 0xFF: not used */ |
| 107 | uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; |
| 108 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 109 | * clksrc. */ |
| 110 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; |
| 111 | |
| 112 | /* SMBus */ |
| 113 | uint8_t SmbusEnable; |
| 114 | |
| 115 | /* eMMC and SD */ |
| 116 | uint8_t ScsEmmcHs400Enabled; |
| 117 | /* Need to update DLL setting to get Emmc running at HS400 speed */ |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 118 | uint8_t EmmcUseCustomDlls; |
| 119 | uint32_t EmmcTxCmdDelayRegValue; |
| 120 | uint32_t EmmcTxDataDelay1RegValue; |
| 121 | uint32_t EmmcTxDataDelay2RegValue; |
| 122 | uint32_t EmmcRxCmdDataDelay1RegValue; |
| 123 | uint32_t EmmcRxCmdDataDelay2RegValue; |
| 124 | uint32_t EmmcRxStrobeDelayRegValue; |
| 125 | |
| 126 | /* Enable if SD Card Power Enable Signal is Active High */ |
| 127 | uint8_t SdCardPowerEnableActiveHigh; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 128 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 129 | /* Heci related */ |
| 130 | uint8_t Heci3Enabled; |
| 131 | |
| 132 | /* Gfx related */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 133 | uint8_t SkipExtGfxScan; |
| 134 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 135 | uint8_t Device4Enable; |
| 136 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 137 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 138 | uint8_t eist_enable; |
| 139 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 140 | /* Enable C6 DRAM */ |
| 141 | uint8_t enable_c6dram; |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 142 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 143 | /* |
| 144 | * SerialIO device mode selection: |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 145 | * PchSerialIoDisabled, |
| 146 | * PchSerialIoPci, |
| 147 | * PchSerialIoHidden, |
| 148 | * PchSerialIoLegacyUart, |
| 149 | * PchSerialIoSkipInit |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 150 | */ |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 151 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 152 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 153 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 154 | /* |
| 155 | * GSPIn Default Chip Select Mode: |
| 156 | * 0:Hardware Mode, |
| 157 | * 1:Software Mode |
| 158 | */ |
| 159 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 160 | /* |
| 161 | * GSPIn Default Chip Select State: |
| 162 | * 0: Low, |
| 163 | * 1: High |
| 164 | */ |
| 165 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 166 | |
| 167 | /* GPIO SD card detect pin */ |
| 168 | unsigned int sdcard_cd_gpio; |
| 169 | |
| 170 | /* Enable Pch iSCLK */ |
| 171 | uint8_t pch_isclk; |
| 172 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 173 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 174 | bool CnviBtAudioOffload; |
Subrata Banik | dd5fa02 | 2019-05-15 21:04:37 +0530 | [diff] [blame] | 175 | |
| 176 | /* |
| 177 | * Override GPIO PM configuration: |
| 178 | * 0: Use FSP default GPIO PM program, |
| 179 | * 1: coreboot to override GPIO PM program |
| 180 | */ |
| 181 | uint8_t gpio_override_pm; |
| 182 | |
| 183 | /* |
| 184 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 185 | * Bit 6-7: Reserved |
| 186 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 187 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 188 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 189 | * Bit 2: MISCCFG_GSXLCGEN |
| 190 | * Bit 1: MISCCFG_GPDPCGEN |
| 191 | * Bit 0: MISCCFG_GPDLCGEN |
| 192 | */ |
| 193 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | typedef struct soc_intel_icelake_config config_t; |
| 197 | |
| 198 | #endif |