Angel Pons | 32abdd6 | 2020-04-05 15:47:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 2 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 3 | #include <device/mmio.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 4 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 6 | #include <intelblocks/fast_spi.h> |
| 7 | #include <intelblocks/gspi.h> |
| 8 | #include <intelblocks/lpc_lib.h> |
| 9 | #include <intelblocks/p2sb.h> |
| 10 | #include <intelblocks/pcr.h> |
| 11 | #include <intelblocks/pmclib.h> |
| 12 | #include <intelblocks/rtc.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | #include <soc/bootblock.h> |
| 14 | #include <soc/iomap.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 15 | #include <soc/p2sb.h> |
| 16 | #include <soc/pch.h> |
| 17 | #include <soc/pci_devs.h> |
| 18 | #include <soc/pcr_ids.h> |
| 19 | #include <soc/pm.h> |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 20 | |
Aamir Bohra | c726763 | 2018-06-30 12:38:43 +0530 | [diff] [blame] | 21 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 22 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 23 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 24 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 25 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 26 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 27 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 28 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 29 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 30 | static void soc_config_pwrmbase(void) |
| 31 | { |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 32 | /* |
| 33 | * Assign Resources to PWRMBASE |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 34 | * Clear BIT 1-2 Command Register |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 35 | */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 36 | pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 37 | |
| 38 | /* Program PWRM Base */ |
| 39 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 40 | |
| 41 | /* Enable Bus Master and MMIO Space */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 42 | pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 43 | |
| 44 | /* Enable PWRM in PMC */ |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 45 | setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | void bootblock_pch_early_init(void) |
| 49 | { |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 50 | /* |
| 51 | * Perform P2SB configuration before any another controller initialization as the |
| 52 | * controller might want to perform PCR settings. |
| 53 | */ |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 54 | p2sb_enable_bar(); |
| 55 | p2sb_configure_hpet(); |
| 56 | |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame] | 57 | fast_spi_early_init(SPI_BASE_ADDRESS); |
| 58 | gspi_early_bar_init(); |
| 59 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 60 | /* |
| 61 | * Enabling PWRM Base for accessing |
| 62 | * Global Reset Cause Register. |
| 63 | */ |
| 64 | soc_config_pwrmbase(); |
| 65 | } |
| 66 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 67 | static void soc_config_acpibase(void) |
| 68 | { |
| 69 | uint32_t pmc_reg_value; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 70 | |
Aamir Bohra | c726763 | 2018-06-30 12:38:43 +0530 | [diff] [blame] | 71 | pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + |
| 72 | PCR_PSFX_TO_SHDW_BAR4); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 73 | |
| 74 | if (pmc_reg_value != 0xFFFFFFFF) { |
| 75 | /* Disable Io Space before changing the address */ |
Aamir Bohra | c726763 | 2018-06-30 12:38:43 +0530 | [diff] [blame] | 76 | pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 77 | PCR_PSFX_T0_SHDW_PCIEN, |
| 78 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 79 | /* Program ABASE in PSF3 PMC space BAR4*/ |
Aamir Bohra | c726763 | 2018-06-30 12:38:43 +0530 | [diff] [blame] | 80 | pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 81 | PCR_PSFX_TO_SHDW_BAR4, |
| 82 | ACPI_BASE_ADDRESS); |
| 83 | /* Enable IO Space */ |
Aamir Bohra | c726763 | 2018-06-30 12:38:43 +0530 | [diff] [blame] | 84 | pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 85 | PCR_PSFX_T0_SHDW_PCIEN, |
| 86 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 87 | } |
| 88 | } |
| 89 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 90 | void pch_early_iorange_init(void) |
| 91 | { |
Subrata Banik | 1c329a0 | 2018-11-26 15:43:18 +0530 | [diff] [blame] | 92 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 93 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 94 | |
| 95 | /* IO Decode Range */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 96 | if (CONFIG(DRIVERS_UART_8250IO)) |
Subrata Banik | 1c329a0 | 2018-11-26 15:43:18 +0530 | [diff] [blame] | 97 | lpc_io_setup_comm_a_b(); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 98 | |
| 99 | /* IO Decode Enable */ |
Michael Niewöhner | 33c0aac | 2021-01-24 12:56:12 +0100 | [diff] [blame] | 100 | lpc_enable_fixed_io_ranges(io_enables); |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 101 | |
| 102 | /* Program generic IO Decode Range */ |
| 103 | pch_enable_lpc(); |
| 104 | } |
| 105 | |
Angel Pons | 4ace49c | 2021-02-19 20:15:43 +0100 | [diff] [blame] | 106 | void bootblock_pch_init(void) |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 107 | { |
| 108 | /* |
| 109 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 110 | * GPE0_STS, GPE0_EN registers. |
| 111 | */ |
| 112 | soc_config_acpibase(); |
| 113 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 114 | /* Set up GPE configuration */ |
| 115 | pmc_gpe_init(); |
| 116 | |
| 117 | enable_rtc_upper_bank(); |
| 118 | } |