Angel Pons | 60ec365 | 2020-04-03 01:22:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 6efa5c3 | 2018-11-06 11:37:44 +0530 | [diff] [blame] | 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
Kyösti Mälkki | 9a3bde0 | 2021-11-06 16:13:15 +0200 | [diff] [blame] | 5 | #include <types.h> |
Kyösti Mälkki | 91c077f | 2021-11-03 18:34:14 +0200 | [diff] [blame] | 6 | #include <vendorcode/google/chromeos/chromeos.h> |
Aamir Bohra | 6efa5c3 | 2018-11-06 11:37:44 +0530 | [diff] [blame] | 7 | |
Paul Menzel | 6c307d7 | 2021-12-20 08:05:12 +0100 | [diff] [blame] | 8 | /* Pad configuration in ramstage */ |
Aamir Bohra | 6efa5c3 | 2018-11-06 11:37:44 +0530 | [diff] [blame] | 9 | static const struct pad_config gpio_table[] = { |
| 10 | /* I2S2_SCLK */ |
| 11 | PAD_CFG_GPI(GPP_A7, NONE, PLTRST), |
| 12 | /* I2S2_RXD */ |
| 13 | PAD_CFG_GPI(GPP_A10, NONE, PLTRST), |
| 14 | /* TCH_PNL2_RST_N */ |
| 15 | PAD_CFG_GPO(GPP_A13, 1, DEEP), |
| 16 | /* ONBOARD_X4_PCIE_SLOT1_PWREN_N */ |
| 17 | PAD_CFG_GPO(GPP_A14, 0, DEEP), |
| 18 | /* TCH_PNL2_INT_N */ |
| 19 | PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST), |
| 20 | /* TC_RETIMER_FORCE_PWR */ |
| 21 | PAD_CFG_GPO(GPP_B4, 0, DEEP), |
| 22 | /* FPS_RST_N */ |
| 23 | PAD_CFG_GPO(GPP_B14, 1, DEEP), |
| 24 | /* WIFI_RF_KILL_N */ |
| 25 | PAD_CFG_GPO(GPP_B15, 1, PLTRST), |
| 26 | /* M2_SSD_PWREN_N */ |
| 27 | PAD_CFG_GPO(GPP_B16, 1, DEEP), |
| 28 | /* WWAN_PERST_N */ |
| 29 | PAD_CFG_GPO(GPP_B17, 1, DEEP), |
| 30 | /* BT_RF_KILL_N */ |
| 31 | PAD_CFG_GPO(GPP_B18, 1, PLTRST), |
| 32 | /* CRD_CAM_PWREN_1 */ |
| 33 | PAD_CFG_GPO(GPP_B23, 1, PLTRST), |
| 34 | /* WF_CAM_CLK_EN */ |
| 35 | PAD_CFG_GPO(GPP_C2, 1, PLTRST), |
| 36 | /* ONBOARD_X4_PCIE_SLOT1_RESET_N */ |
| 37 | PAD_CFG_GPO(GPP_C5, 1, DEEP), |
| 38 | /* TCH_PAD_INT_N */ |
| 39 | PAD_CFG_GPI_APIC_EDGE_LOW(GPP_C8, NONE, PLTRST), |
| 40 | /* WWAN_RST_N */ |
| 41 | PAD_CFG_GPO(GPP_C10, 1, DEEP), |
| 42 | /* WWAN_FCP_OFF_N */ |
| 43 | PAD_CFG_GPO(GPP_C11, 1, DEEP), |
| 44 | /* CODEC_INT_N */ |
| 45 | PAD_CFG_GPI_APIC_LOW(GPP_C12, NONE, PLTRST), |
| 46 | /* SPKR_PD_N */ |
| 47 | PAD_CFG_GPO(GPP_C13, 1, PLTRST), |
| 48 | /* WF_CAM_RST_N */ |
| 49 | PAD_CFG_GPO(GPP_C15, 1, PLTRST), |
| 50 | /* CRD_CAM_STROBE_1 */ |
| 51 | PAD_CFG_GPO(GPP_C22, 0, PLTRST), |
| 52 | /* CRD_CAM_PRIVACY_LED_1 */ |
| 53 | PAD_CFG_GPO(GPP_C23, 0, PLTRST), |
| 54 | /* FLASH_DES_SEC_OVERRIDEs */ |
| 55 | PAD_CFG_GPO(GPP_D13, 0, DEEP), |
| 56 | /* TCH_PAD_LS_EN */ |
| 57 | PAD_CFG_GPO(GPP_D14, 1, PLTRST), |
| 58 | /* ONBOARD_X4_PCIE_SLOT1_DGPU_SEL */ |
| 59 | PAD_CFG_GPO(GPP_D15, 0, DEEP), |
| 60 | /* MFR_MODE_DET_STRAP */ |
| 61 | PAD_CFG_GPI(GPP_D16, NONE, PLTRST), |
| 62 | /* TBT_CIO_PWR_EN */ |
| 63 | PAD_CFG_GPO(GPP_E0, 1, DEEP), |
| 64 | /* FPS_INT */ |
| 65 | PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, NONE), |
| 66 | /* EC_SLP_S0_CS_N */ |
| 67 | PAD_CFG_GPO(GPP_E6, 1, DEEP), |
| 68 | /* EC_SMI_N */ |
| 69 | PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), |
| 70 | /* TBT_CIO_PLUG_EVENT_N */ |
| 71 | PAD_CFG_GPI_SCI(GPP_E17, NONE, DEEP, EDGE_SINGLE, NONE), |
| 72 | /* DISP_AUX_P_BIAS_GPIO */ |
| 73 | PAD_CFG_GPO(GPP_E22, 0, PLTRST), |
| 74 | /* DISP_AUX_N_BIAS_GPIO */ |
| 75 | PAD_CFG_GPO(GPP_E23, 1, DEEP), |
| 76 | /* SATA_HDD_PWREN */ |
| 77 | PAD_CFG_GPO(GPP_F4, 1, PLTRST), |
| 78 | /* BIOS_REC */ |
| 79 | PAD_CFG_GPI(GPP_F5, NONE, PLTRST), |
| 80 | /* SD_CD# */ |
| 81 | PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), |
| 82 | /* SD_WP */ |
| 83 | PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), |
| 84 | /* M2_SSD_RST_N */ |
| 85 | PAD_CFG_GPO(GPP_H0, 1, DEEP), |
| 86 | }; |
| 87 | |
| 88 | /* Early pad configuration in bootblock */ |
| 89 | static const struct pad_config early_gpio_table[] = { |
Michael Niewöhner | beee666 | 2020-12-21 03:46:58 +0100 | [diff] [blame] | 90 | /* UART2 RX */ |
| 91 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 92 | /* UART2 TX */ |
| 93 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
Aamir Bohra | 6efa5c3 | 2018-11-06 11:37:44 +0530 | [diff] [blame] | 94 | }; |
| 95 | |
| 96 | const struct pad_config *variant_gpio_table(size_t *num) |
| 97 | { |
| 98 | *num = ARRAY_SIZE(gpio_table); |
| 99 | return gpio_table; |
| 100 | } |
| 101 | |
| 102 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 103 | { |
| 104 | *num = ARRAY_SIZE(early_gpio_table); |
| 105 | return early_gpio_table; |
| 106 | } |
Aamir Bohra | b5ba8b6 | 2019-12-05 17:49:39 +0530 | [diff] [blame] | 107 | |
| 108 | static const struct cros_gpio cros_gpios[] = { |
| 109 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 110 | }; |
| 111 | |
Kyösti Mälkki | 4ff218a | 2021-11-02 13:03:06 +0200 | [diff] [blame] | 112 | DECLARE_CROS_GPIOS(cros_gpios); |