Angel Pons | 60ec365 | 2020-04-03 01:22:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | 3c37b5a | 2018-06-29 22:33:25 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | 9c561c9 | 2018-11-27 19:32:06 +0530 | [diff] [blame] | 3 | #include <console/console.h> |
Aamir Bohra | 3c37b5a | 2018-06-29 22:33:25 +0530 | [diff] [blame] | 4 | #include <fsp/api.h> |
| 5 | #include <soc/romstage.h> |
Aamir Bohra | 3c37b5a | 2018-06-29 22:33:25 +0530 | [diff] [blame] | 6 | #include <spd_bin.h> |
Aamir Bohra | 9c561c9 | 2018-11-27 19:32:06 +0530 | [diff] [blame] | 7 | #include "board_id.h" |
Elyes HAOUAS | 351e3e5 | 2019-04-05 18:11:19 +0200 | [diff] [blame] | 8 | #include "spd/spd.h" |
| 9 | |
Aamir Bohra | 3c37b5a | 2018-06-29 22:33:25 +0530 | [diff] [blame] | 10 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 11 | { |
Aamir Bohra | 9c561c9 | 2018-11-27 19:32:06 +0530 | [diff] [blame] | 12 | FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; |
| 13 | u8 spd_index = (get_board_id() & 0x1F) & 0x7; |
| 14 | printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); |
| 15 | |
| 16 | if (spd_index > 0 && spd_index != 2) { |
Julius Werner | a9b44f4 | 2021-02-05 17:27:45 -0800 | [diff] [blame] | 17 | mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; |
Aamir Bohra | 9c561c9 | 2018-11-27 19:32:06 +0530 | [diff] [blame] | 18 | |
| 19 | /* Memory leak is ok since we have memory mapped boot media */ |
Julius Werner | a9b44f4 | 2021-02-05 17:27:45 -0800 | [diff] [blame] | 20 | mem_cfg->MemorySpdPtr00 = spd_cbfs_map(spd_index); |
| 21 | if (!mem_cfg->MemorySpdPtr00) |
| 22 | die("spd.bin not found\n"); |
Aamir Bohra | 9c561c9 | 2018-11-27 19:32:06 +0530 | [diff] [blame] | 23 | mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; |
| 24 | |
| 25 | mem_cfg->SpdAddressTable[0] = 0x0; |
| 26 | mem_cfg->SpdAddressTable[1] = 0x0; |
| 27 | mem_cfg->SpdAddressTable[2] = 0x0; |
| 28 | mem_cfg->SpdAddressTable[3] = 0x0; |
| 29 | } else { |
| 30 | mem_cfg->MemorySpdPtr00 = 0; |
| 31 | mem_cfg->MemorySpdPtr01 = 0; |
| 32 | mem_cfg->MemorySpdPtr10 = 0; |
| 33 | mem_cfg->MemorySpdPtr11 = 0; |
| 34 | |
| 35 | mem_cfg->SpdAddressTable[0] = 0xA0; |
| 36 | mem_cfg->SpdAddressTable[1] = 0xA2; |
| 37 | mem_cfg->SpdAddressTable[2] = 0xA4; |
| 38 | mem_cfg->SpdAddressTable[3] = 0xA6; |
| 39 | } |
| 40 | mem_cfg->DqPinsInterleaved = 0; |
| 41 | mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ |
| 42 | mem_cfg->ECT = 1; /* Early Command Training Enabled */ |
| 43 | mem_cfg->RefClk = 0; /* Auto Select CLK freq */ |
| 44 | |
| 45 | mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); |
| 46 | mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); |
| 47 | mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); |
| 48 | mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); |
| 49 | mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); |
| 50 | mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); |
Aamir Bohra | 3c37b5a | 2018-06-29 22:33:25 +0530 | [diff] [blame] | 51 | } |