Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 4 | #include <arch/ioapic.h> |
John Zhao | f6f1f73 | 2020-06-26 10:00:02 -0700 | [diff] [blame] | 5 | #include <assert.h> |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <console/console.h> |
| 8 | #include <cpu/amd/msr.h> |
| 9 | #include <cpu/amd/mtrr.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
| 13 | #include <fsp/util.h> |
| 14 | #include <stdint.h> |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 15 | #include <soc/memmap.h> |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 16 | #include <soc/iomap.h> |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 17 | #include "chip.h" |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 18 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 19 | enum { |
| 20 | ALIB_DPTCI_FUNCTION_ID = 0xc, |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 21 | THERMAL_CONTROL_LIMIT_ID = 0x3, |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 22 | SUSTAINED_POWER_LIMIT_PARAM_ID = 0x5, |
| 23 | FAST_PPT_LIMIT_PARAM_ID = 0x6, |
| 24 | SLOW_PPT_LIMIT_PARAM_ID = 0x7, |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 25 | DPTC_TOTAL_UPDATE_PARAMS = 4, |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 26 | }; |
| 27 | |
| 28 | struct dptc_param { |
| 29 | uint8_t id; |
| 30 | uint32_t value; |
| 31 | } __packed; |
| 32 | |
| 33 | struct dptc_input { |
| 34 | uint16_t size; |
| 35 | struct dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
| 36 | } __packed; |
| 37 | |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 38 | #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 39 | { \ |
| 40 | .size = sizeof(struct dptc_input), \ |
| 41 | .params = { \ |
| 42 | { \ |
Kevin Chiu | cdd9f5c | 2020-09-18 17:30:30 +0800 | [diff] [blame] | 43 | .id = THERMAL_CONTROL_LIMIT_ID, \ |
| 44 | .value = _thermctllmit, \ |
| 45 | }, \ |
| 46 | { \ |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 47 | .id = SUSTAINED_POWER_LIMIT_PARAM_ID, \ |
| 48 | .value = _sustained, \ |
| 49 | }, \ |
| 50 | { \ |
| 51 | .id = FAST_PPT_LIMIT_PARAM_ID, \ |
| 52 | .value = _fast, \ |
| 53 | }, \ |
| 54 | { \ |
| 55 | .id = SLOW_PPT_LIMIT_PARAM_ID, \ |
| 56 | .value = _slow, \ |
| 57 | }, \ |
| 58 | }, \ |
| 59 | } |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 60 | /* |
| 61 | * |
| 62 | * +--------------------------------+ |
| 63 | * | | |
| 64 | * | | |
| 65 | * | | |
| 66 | * | | |
| 67 | * | | |
| 68 | * | | |
| 69 | * | | |
| 70 | * reserved_dram_end +--------------------------------+ |
| 71 | * | | |
| 72 | * | verstage (if reqd) | |
| 73 | * | (VERSTAGE_SIZE) | |
| 74 | * +--------------------------------+ VERSTAGE_ADDR |
| 75 | * | | |
| 76 | * | FSP-M | |
| 77 | * | (FSP_M_SIZE) | |
| 78 | * +--------------------------------+ FSP_M_ADDR |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 79 | * | romstage | |
| 80 | * | (ROMSTAGE_SIZE) | |
Kyösti Mälkki | b3621f8 | 2020-12-04 19:51:17 +0200 | [diff] [blame] | 81 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 82 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 83 | * | bootblock | |
| 84 | * | (C_ENV_BOOTBLOCK_SIZE) | |
Kyösti Mälkki | b3621f8 | 2020-12-04 19:51:17 +0200 | [diff] [blame] | 85 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 86 | * | Unused hole | |
| 87 | * | (86KiB) | |
| 88 | * +--------------------------------+ |
| 89 | * | FMAP cache (FMAP_SIZE) | |
| 90 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 91 | * | Early Timestamp region (512B) | |
| 92 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 93 | * | Preram CBMEM console | |
| 94 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 95 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 96 | * | PSP shared (vboot workbuf) | |
| 97 | * | (PSP_SHAREDMEM_SIZE) | |
| 98 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 99 | * | APOB (64KiB) | |
| 100 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 101 | * | Early BSP stack | |
| 102 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 103 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 104 | * | DRAM | |
| 105 | * +--------------------------------+ 0x100000 |
| 106 | * | Option ROM | |
| 107 | * +--------------------------------+ 0xc0000 |
| 108 | * | Legacy VGA | |
| 109 | * +--------------------------------+ 0xa0000 |
| 110 | * | DRAM | |
| 111 | * +--------------------------------+ 0x0 |
| 112 | */ |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 113 | static void read_resources(struct device *dev) |
| 114 | { |
| 115 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
| 116 | unsigned int idx = 0; |
| 117 | const struct hob_header *hob = fsp_get_hob_list(); |
| 118 | const struct hob_resource *res; |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 119 | struct resource *gnb_apic; |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 120 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 121 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 122 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 123 | |
| 124 | early_reserved_dram_start = e->base; |
| 125 | early_reserved_dram_end = e->base + e->size; |
| 126 | |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 127 | /* 0x0 - 0x9ffff */ |
| 128 | ram_resource(dev, idx++, 0, 0xa0000 / KiB); |
| 129 | |
| 130 | /* 0xa0000 - 0xbffff: legacy VGA */ |
| 131 | mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); |
| 132 | |
| 133 | /* 0xc0000 - 0xfffff: Option ROM */ |
| 134 | reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); |
| 135 | |
Furquan Shaikh | bc45650 | 2020-06-10 16:37:23 -0700 | [diff] [blame] | 136 | /* 1MB - bottom of DRAM reserved for early coreboot usage */ |
| 137 | ram_resource(dev, idx++, (1 * MiB) / KiB, |
| 138 | (early_reserved_dram_start - (1 * MiB)) / KiB); |
| 139 | |
| 140 | /* DRAM reserved for early coreboot usage */ |
| 141 | reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, |
| 142 | (early_reserved_dram_end - early_reserved_dram_start) / KiB); |
| 143 | |
| 144 | /* top of DRAM consumed early - low top usable RAM |
| 145 | * cbmem_top() accounts for low UMA and TSEG if they are used. */ |
| 146 | ram_resource(dev, idx++, early_reserved_dram_end / KiB, |
| 147 | (mem_usable - early_reserved_dram_end) / KiB); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 148 | |
| 149 | mmconf_resource(dev, MMIO_CONF_BASE); |
| 150 | |
| 151 | if (!hob) { |
| 152 | printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", |
| 153 | __func__); |
| 154 | return; |
| 155 | } |
| 156 | |
| 157 | for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { |
| 158 | |
| 159 | if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) |
| 160 | continue; |
| 161 | |
| 162 | res = fsp_hob_header_to_resource(hob); |
| 163 | |
| 164 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) |
| 165 | continue; /* 0 through low usable was set above */ |
| 166 | if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) |
| 167 | continue; /* Done separately */ |
| 168 | |
| 169 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) |
| 170 | ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 171 | else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) |
| 172 | reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 173 | else |
| 174 | printk(BIOS_ERR, "Error: failed to set resources for type %d\n", |
| 175 | res->type); |
| 176 | } |
Marshall Dawson | 39c64b0 | 2020-09-04 12:07:27 -0600 | [diff] [blame] | 177 | |
| 178 | /* GNB IOAPIC resource */ |
| 179 | gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); |
| 180 | gnb_apic->base = GNB_IO_APIC_ADDR; |
| 181 | gnb_apic->size = 0x00001000; |
| 182 | gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 183 | } |
| 184 | |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 185 | static void root_complex_init(struct device *dev) |
| 186 | { |
| 187 | setup_ioapic((u8 *)GNB_IO_APIC_ADDR, CONFIG_PICASSO_GNB_IOAPIC_ID); |
| 188 | } |
| 189 | |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 190 | static void dptc_call_alib(const char *buf_name, uint8_t *buffer, size_t size) |
| 191 | { |
| 192 | /* Name (buf_name, Buffer(size) {...} */ |
| 193 | acpigen_write_name(buf_name); |
| 194 | acpigen_write_byte_buffer(buffer, size); |
| 195 | |
| 196 | /* \_SB.ALIB(0xc, buf_name) */ |
| 197 | acpigen_emit_namestring("\\_SB.ALIB"); |
| 198 | acpigen_write_integer(ALIB_DPTCI_FUNCTION_ID); |
| 199 | acpigen_emit_namestring(buf_name); |
| 200 | } |
| 201 | |
| 202 | static void acipgen_dptci(void) |
| 203 | { |
Felix Held | 507fc03 | 2020-12-05 01:55:27 +0100 | [diff] [blame] | 204 | const struct soc_amd_picasso_config *config = config_of_soc(); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 205 | |
| 206 | if (!config->dptc_enable) |
| 207 | return; |
| 208 | |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 209 | struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, |
| 210 | config->sustained_power_limit_mW, |
| 211 | config->fast_ppt_limit_mW, |
| 212 | config->slow_ppt_limit_mW); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 213 | struct dptc_input tablet_mode_input = DPTC_INPUTS( |
Zheng Bao | 795d73c | 2020-10-27 15:36:55 +0800 | [diff] [blame] | 214 | config->thermctl_limit_tablet_mode_degreeC, |
| 215 | config->sustained_power_limit_tablet_mode_mW, |
| 216 | config->fast_ppt_limit_tablet_mode_mW, |
| 217 | config->slow_ppt_limit_tablet_mode_mW); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 218 | /* Scope (\_SB) */ |
| 219 | acpigen_write_scope("\\_SB"); |
| 220 | |
| 221 | /* Method(DPTC, 0, Serialized) */ |
| 222 | acpigen_write_method_serialized("DPTC", 0); |
| 223 | |
| 224 | /* If (LEqual ("\_SB.PCI0.LPCB.EC0.TBMD", 1)) */ |
| 225 | acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.LPCB.EC0.TBMD", 1); |
| 226 | |
| 227 | dptc_call_alib("TABB", (uint8_t *)(void *)&tablet_mode_input, |
| 228 | sizeof(tablet_mode_input)); |
| 229 | |
| 230 | acpigen_pop_len(); /* If */ |
| 231 | |
| 232 | /* Else */ |
| 233 | acpigen_write_else(); |
| 234 | |
| 235 | dptc_call_alib("DEFB", (uint8_t *)(void *)&default_input, sizeof(default_input)); |
| 236 | |
| 237 | acpigen_pop_len(); /* Else */ |
| 238 | |
| 239 | acpigen_pop_len(); /* Method DPTC */ |
| 240 | acpigen_pop_len(); /* Scope \_SB */ |
| 241 | } |
| 242 | |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 243 | /* Used by \_SB.PCI0._CRS */ |
| 244 | static void root_complex_fill_ssdt(const struct device *device) |
| 245 | { |
| 246 | msr_t msr; |
John Zhao | f6f1f73 | 2020-06-26 10:00:02 -0700 | [diff] [blame] | 247 | const char *scope; |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 248 | |
John Zhao | f6f1f73 | 2020-06-26 10:00:02 -0700 | [diff] [blame] | 249 | assert(device); |
Felix Held | 3858fb1 | 2020-06-27 15:11:36 +0200 | [diff] [blame] | 250 | |
John Zhao | f6f1f73 | 2020-06-26 10:00:02 -0700 | [diff] [blame] | 251 | scope = acpi_device_scope(device); |
| 252 | assert(scope); |
| 253 | acpigen_write_scope(scope); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 254 | |
| 255 | msr = rdmsr(TOP_MEM); |
| 256 | acpigen_write_name_dword("TOM1", msr.lo); |
| 257 | msr = rdmsr(TOP_MEM2); |
| 258 | /* |
| 259 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 260 | * here. |
| 261 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 262 | * slide 22ff. |
| 263 | * Shift value right by 20 bit to make it fit into 32bit, |
| 264 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 265 | */ |
| 266 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 267 | acpigen_pop_len(); |
Chris Wang | 4735b1c | 2020-07-13 23:29:29 +0800 | [diff] [blame] | 268 | acipgen_dptci(); |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | static struct device_operations root_complex_operations = { |
| 272 | .read_resources = read_resources, |
Felix Held | 9541d17 | 2021-01-05 00:56:10 +0100 | [diff] [blame] | 273 | .set_resources = noop_set_resources, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 274 | .enable_resources = pci_dev_enable_resources, |
Felix Held | f9608cd | 2020-12-03 16:57:02 +0100 | [diff] [blame] | 275 | .init = root_complex_init, |
Marshall Dawson | eb72487 | 2019-07-16 15:46:35 -0600 | [diff] [blame] | 276 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
| 277 | }; |
| 278 | |
| 279 | static const struct pci_driver family17_root_complex __pci_driver = { |
| 280 | .ops = &root_complex_operations, |
| 281 | .vendor = PCI_VENDOR_ID_AMD, |
| 282 | .device = PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB, |
| 283 | }; |