Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <stdint.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/hypertransport.h> |
| 27 | #include <stdlib.h> |
| 28 | #include <string.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 29 | #include <cpu/cpu.h> |
| 30 | #include <boot/tables.h> |
| 31 | #include <arch/acpi.h> |
| 32 | #include <cbmem.h> |
| 33 | #include "chip.h" |
| 34 | #include "gm45.h" |
| 35 | |
| 36 | /* Reserve everything between A segment and 1MB: |
| 37 | * |
| 38 | * 0xa0000 - 0xbffff: legacy VGA |
| 39 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 40 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 41 | */ |
| 42 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 43 | static const int legacy_hole_size_k = 384; |
| 44 | |
| 45 | static int decode_pcie_bar(u32 *const base, u32 *const len) |
| 46 | { |
| 47 | *base = 0; |
| 48 | *len = 0; |
| 49 | |
| 50 | const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 51 | if (!dev) |
| 52 | return 0; |
| 53 | |
| 54 | const u32 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); |
| 55 | |
| 56 | if (!(pciexbar_reg & (1 << 0))) |
| 57 | return 0; |
| 58 | |
| 59 | switch ((pciexbar_reg >> 1) & 3) { |
| 60 | case 0: /* 256MB */ |
| 61 | *base = pciexbar_reg & (0x0f << 28); |
| 62 | *len = 256 * 1024 * 1024; |
| 63 | return 1; |
| 64 | case 1: /* 128M */ |
| 65 | *base = pciexbar_reg & (0x1f << 27); |
| 66 | *len = 128 * 1024 * 1024; |
| 67 | return 1; |
| 68 | case 2: /* 64M */ |
| 69 | *base = pciexbar_reg & (0x3f << 26); |
| 70 | *len = 64 * 1024 * 1024; |
| 71 | return 1; |
| 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static void mch_domain_read_resources(device_t dev) |
| 78 | { |
| 79 | u64 tom, touud; |
| 80 | u32 tomk, tolud, uma_sizek = 0; |
| 81 | u32 pcie_config_base, pcie_config_size; |
| 82 | |
| 83 | /* Total Memory 2GB example: |
| 84 | * |
| 85 | * 00000000 0000MB-2014MB 2014MB RAM (writeback) |
| 86 | * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached) |
| 87 | * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached) |
| 88 | * 80000000 2048MB TOLUD |
| 89 | * 80000000 2048MB TOM |
| 90 | * |
| 91 | * Total Memory 4GB example: |
| 92 | * |
| 93 | * 00000000 0000MB-3038MB 3038MB RAM (writeback) |
| 94 | * bde00000 3038MB-3040MB 2MB GFX GTT (uncached) |
| 95 | * be000000 3040MB-3072MB 32MB GFX UMA (uncached) |
| 96 | * be000000 3072MB TOLUD |
| 97 | * 100000000 4096MB TOM |
| 98 | * 100000000 4096MB-5120MB 1024MB RAM (writeback) |
| 99 | * 140000000 5120MB TOUUD |
| 100 | */ |
| 101 | |
| 102 | pci_domain_read_resources(dev); |
| 103 | |
| 104 | /* Top of Upper Usable DRAM, including remap */ |
| 105 | touud = pci_read_config16(dev, D0F0_TOUUD); |
| 106 | touud <<= 20; |
| 107 | |
| 108 | /* Top of Lower Usable DRAM */ |
| 109 | tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; |
| 110 | tolud <<= 16; |
| 111 | |
| 112 | /* Top of Memory - does not account for any UMA */ |
| 113 | tom = pci_read_config16(dev, D0F0_TOM) & 0x1ff; |
| 114 | tom <<= 27; |
| 115 | |
| 116 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 117 | touud, tolud, tom); |
| 118 | |
| 119 | tomk = tolud >> 10; |
| 120 | |
| 121 | /* Graphics memory comes next */ |
| 122 | const u16 ggc = pci_read_config16(dev, D0F0_GGC); |
| 123 | if (!(ggc & 2)) { |
| 124 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 125 | |
| 126 | /* Graphics memory */ |
| 127 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 128 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 129 | tomk -= gms_sizek; |
| 130 | |
| 131 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 132 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 133 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 134 | tomk -= gsm_sizek; |
| 135 | |
| 136 | uma_sizek = gms_sizek + gsm_sizek; |
| 137 | } |
| 138 | |
| 139 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
| 140 | |
| 141 | /* Report the memory regions */ |
| 142 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 143 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
| 144 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
| 145 | |
| 146 | /* |
| 147 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 148 | * is remapped above TOM, TOUUD will account for both |
| 149 | */ |
| 150 | touud >>= 10; /* Convert to KB */ |
| 151 | if (touud > 4096 * 1024) { |
| 152 | ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); |
| 153 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 154 | (touud >> 10) - 4096); |
| 155 | } |
| 156 | |
| 157 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 158 | "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10); |
| 159 | /* Don't use uma_resource() as our UMA touches the PCI hole. */ |
| 160 | fixed_mem_resource(dev, 6, tomk, uma_sizek, IORESOURCE_RESERVE); |
| 161 | |
| 162 | if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { |
| 163 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 164 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 165 | fixed_mem_resource(dev, 7, pcie_config_base >> 10, |
| 166 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 167 | } |
| 168 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 169 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 170 | high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE; |
| 171 | high_tables_size = HIGH_MEMORY_SIZE; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | static void mch_domain_set_resources(device_t dev) |
| 175 | { |
| 176 | struct resource *resource; |
| 177 | int i; |
| 178 | |
| 179 | for (i = 3; i < 8; ++i) { |
| 180 | /* Report read resources. */ |
| 181 | resource = find_resource(dev, i); |
| 182 | if (resource) |
| 183 | report_resource_stored(dev, resource, ""); |
| 184 | } |
| 185 | |
| 186 | assign_resources(dev->link_list); |
| 187 | } |
| 188 | |
| 189 | static void mch_domain_init(device_t dev) |
| 190 | { |
| 191 | u32 reg32; |
| 192 | |
| 193 | /* Enable SERR */ |
| 194 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 195 | reg32 |= PCI_COMMAND_SERR; |
| 196 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 197 | } |
| 198 | |
| 199 | static struct device_operations pci_domain_ops = { |
| 200 | .read_resources = mch_domain_read_resources, |
| 201 | .set_resources = mch_domain_set_resources, |
| 202 | .enable_resources = NULL, |
| 203 | .init = mch_domain_init, |
| 204 | .scan_bus = pci_domain_scan_bus, |
Kyösti Mälkki | 872c922 | 2013-07-03 09:44:28 +0300 | [diff] [blame^] | 205 | .ops_pci_bus = pci_bus_default_ops, |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | |
| 209 | static void cpu_bus_init(device_t dev) |
| 210 | { |
| 211 | initialize_cpus(dev->link_list); |
| 212 | } |
| 213 | |
| 214 | static void cpu_bus_noop(device_t dev) |
| 215 | { |
| 216 | } |
| 217 | |
| 218 | static struct device_operations cpu_bus_ops = { |
| 219 | .read_resources = cpu_bus_noop, |
| 220 | .set_resources = cpu_bus_noop, |
| 221 | .enable_resources = cpu_bus_noop, |
| 222 | .init = cpu_bus_init, |
| 223 | .scan_bus = 0, |
| 224 | }; |
| 225 | |
| 226 | |
| 227 | static void enable_dev(device_t dev) |
| 228 | { |
| 229 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 230 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 231 | dev->ops = &pci_domain_ops; |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 232 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 233 | dev->ops = &cpu_bus_ops; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static void gm45_init(void *const chip_info) |
| 238 | { |
| 239 | int dev, fn, bit_base; |
| 240 | |
| 241 | struct device *const d0f0 = dev_find_slot(0, 0); |
| 242 | |
| 243 | /* Hide internal functions based on devicetree info. */ |
| 244 | for (dev = 3; dev > 0; --dev) { |
| 245 | switch (dev) { |
| 246 | case 3: /* ME */ |
| 247 | fn = 3; |
| 248 | bit_base = 6; |
| 249 | break; |
| 250 | case 2: /* IGD */ |
| 251 | fn = 1; |
| 252 | bit_base = 3; |
| 253 | break; |
| 254 | case 1: /* PEG */ |
| 255 | fn = 0; |
| 256 | bit_base = 1; |
| 257 | break; |
| 258 | } |
| 259 | for (; fn >= 0; --fn) { |
| 260 | const struct device *const d = |
| 261 | dev_find_slot(0, PCI_DEVFN(dev, fn)); |
| 262 | if (!d || d->enabled) continue; |
| 263 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 264 | pci_write_config32(d0f0, D0F0_DEVEN, |
| 265 | deven & ~(1 << (bit_base + fn))); |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 270 | if (!(deven & (0xf << 6))) |
| 271 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 272 | } |
| 273 | |
| 274 | struct chip_operations northbridge_intel_gm45_ops = { |
| 275 | CHIP_NAME("Intel GM45 Northbridge") |
| 276 | .enable_dev = enable_dev, |
| 277 | .init = gm45_init, |
| 278 | }; |