blob: b6b4b332b54989a6ac5a835f8422349d905c7cf0 [file] [log] [blame]
Zaolina823f9b2014-05-06 21:31:45 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright (C) 2014 Vladimir Serbinenko
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#define THINKPAD_EC_GPE 17
23#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
24#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
25#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
Nicolas Reinecke6d790f72014-08-22 15:10:49 +020026#define RP04_IS_EXPRESSCARD 1
Nicolas Reinecke85f2e122014-10-17 15:09:05 +020027#define EC_LENOVO_H8_ME_WORKAROUND 1
Vladimir Serbinenko91337fd2014-08-20 22:46:14 +020028#define HAVE_LCD_SCREEN 1
Zaolina823f9b2014-05-06 21:31:45 +020029
30DefinitionBlock(
31 "dsdt.aml",
32 "DSDT",
33 0x02, // DSDT revision: ACPI v2.0
34 "COREv4", // OEM id
35 "COREBOOT", // OEM table id
36 0x20110725 // OEM revision
37)
38{
39 // Some generic macros
40 #include "acpi/platform.asl"
41
42 // global NVS and variables
43 #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
44
45 // General Purpose Events
46 //#include "acpi/gpe.asl"
47
48 #include <cpu/intel/model_206ax/acpi/cpu.asl>
49
50 Scope (\_SB) {
51 Device (PCI0)
52 {
53 #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
54 #include <southbridge/intel/bd82x6x/acpi/pch.asl>
55 }
56 }
57
Zaolina823f9b2014-05-06 21:31:45 +020058 /* Chipset specific sleep states */
59 #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
60}