Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mns3on.c |
| 6 | * |
| 7 | * ON memory specific function to support S3 resume |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/ON) |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame^] | 12 | * @e \$Revision: 48511 $ @e \$Date: 2011-03-09 13:53:13 -0700 (Wed, 09 Mar 2011) $ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 13 | * |
| 14 | **/ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| 18 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 42 | * |
| 43 | * *************************************************************************** |
| 44 | * |
| 45 | */ |
| 46 | |
| 47 | /* |
| 48 | *---------------------------------------------------------------------------- |
| 49 | * MODULES USED |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | |
| 55 | |
| 56 | #include "AGESA.h" |
| 57 | #include "AdvancedApi.h" |
| 58 | #include "amdlib.h" |
| 59 | #include "Ids.h" |
| 60 | #include "OptionMemory.h" |
| 61 | #include "mm.h" |
| 62 | #include "mn.h" |
| 63 | #include "S3.h" |
| 64 | #include "mfs3.h" |
| 65 | #include "mnon.h" |
| 66 | #include "cpuRegisters.h" |
| 67 | #include "cpuFamRegisters.h" |
| 68 | #include "cpuFamilyTranslation.h" |
| 69 | #include "GeneralServices.h" |
| 70 | #include "cpuCommonF14Utilities.h" |
| 71 | #include "mnS3on.h" |
| 72 | #include "heapManager.h" |
| 73 | #include "Filecode.h" |
| 74 | #define FILECODE PROC_MEM_NB_ON_MNS3ON_FILECODE |
| 75 | |
| 76 | /*---------------------------------------------------------------------------- |
| 77 | * TYPEDEFS AND STRUCTURES |
| 78 | * |
| 79 | *---------------------------------------------------------------------------- |
| 80 | */ |
| 81 | |
| 82 | /*---------------------------------------------------------------------------- |
| 83 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 84 | * |
| 85 | *---------------------------------------------------------------------------- |
| 86 | */ |
| 87 | UINT16 |
| 88 | STATIC |
| 89 | MemNS3GetRegLstPtrON ( |
| 90 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 91 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 92 | ); |
| 93 | |
| 94 | AGESA_STATUS |
| 95 | STATIC |
| 96 | MemNS3GetDeviceRegLstON ( |
| 97 | IN UINT32 RegisterLstID, |
| 98 | OUT VOID **RegisterHeader |
| 99 | ); |
| 100 | |
| 101 | VOID |
| 102 | STATIC |
| 103 | MemNS3SetDfltPllLockTimeON ( |
| 104 | IN ACCESS_WIDTH AccessWidth, |
| 105 | IN PCI_ADDR Address, |
| 106 | IN OUT VOID *Value, |
| 107 | IN OUT VOID *ConfigPtr |
| 108 | ); |
| 109 | |
| 110 | BOOLEAN |
| 111 | STATIC |
| 112 | MemNS3ChangeNbFrequencyWrapON ( |
| 113 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 114 | IN UINT32 NBPstate |
| 115 | ); |
| 116 | |
| 117 | VOID |
| 118 | STATIC |
| 119 | MemNS3GetConPCIMaskON ( |
| 120 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 121 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 122 | ); |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame^] | 123 | |
| 124 | BOOLEAN |
| 125 | MemS3ResumeConstructNBBlockON ( |
| 126 | IN OUT VOID *S3NBPtr, |
| 127 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 128 | IN UINT8 NodeID |
| 129 | ); |
| 130 | |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 131 | /*---------------------------------------------------------------------------- |
| 132 | * DEFINITIONS AND MACROS |
| 133 | * |
| 134 | *---------------------------------------------------------------------------- |
| 135 | */ |
| 136 | PCI_SPECIAL_CASE PciSpecialCaseFuncON[] = { |
| 137 | {MemNS3GetCSRNb, MemNS3SetCSRNb}, |
| 138 | {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, |
| 139 | {MemNS3DisNbPsDbgNb, MemNS3DisNbPsDbgNb}, |
| 140 | {MemNS3EnNbPsDbg1Nb, MemNS3EnNbPsDbg1Nb}, |
| 141 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDfltPllLockTimeON}, |
| 142 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDisAutoCompUnb}, |
| 143 | { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetDynModeChangeNb}, |
| 144 | {MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb} |
| 145 | }; |
| 146 | |
| 147 | PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = { |
| 148 | {{0, 2, 0}, FUNC_2, 0x110, 0x00000708}, |
| 149 | {{0, 0, 0}, FUNC_1, 0x40, 0x0FFF0003}, |
| 150 | {{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0000}, |
| 151 | {{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF81}, |
| 152 | {{0, 2, 0}, FUNC_2, 0x114, 0x00000200}, |
| 153 | {{0, 0, 0}, FUNC_2, 0x118, 0x0F00CFFF}, |
| 154 | {{0, 0, 0}, FUNC_2, 0x11C, 0x61CC507C}, |
| 155 | {{0, 0, 0}, FUNC_2, 0x40, 0x1FF83FED}, |
| 156 | {{0, 0, 0}, FUNC_2, 0x44, 0x1FF83FED}, |
| 157 | {{0, 0, 0}, FUNC_2, 0x48, 0x1FF83FED}, |
| 158 | {{0, 0, 0}, FUNC_2, 0x4C, 0x1FF83FED}, |
| 159 | {{0, 0, 0}, FUNC_2, 0x60, 0x1FF83FE0}, |
| 160 | {{0, 0, 0}, FUNC_2, 0x64, 0x1FF83FE0}, |
| 161 | {{0, 1, 0}, FUNC_2, 0x80, 0x000000FF}, |
| 162 | {{0, 0, 0}, FUNC_2, 0x84, 0x00FC2FFF}, |
| 163 | {{0, 0, 0}, FUNC_2, 0x88, 0xFF00000F}, |
| 164 | {{0, 0, 0}, FUNC_2, 0x8C, 0x03F7FCFF}, |
| 165 | {{0, 0, 0}, FUNC_2, 0x90, 0x0EF20003}, |
| 166 | {{0, 1, 0}, FUNC_2, 0xA4, 0x00000007}, |
| 167 | {{0, 0, 0}, FUNC_2, 0xA8, 0x0078FF1F}, |
| 168 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x06), 0x00000F8F}, |
| 169 | {{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x16), 0x0000000F}, |
| 170 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x40), 0x3F1F0F0F}, |
| 171 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x41), 0x00070707}, |
| 172 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x83), 0x00007177}, |
| 173 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x180), 0x0F0F0F0F}, |
| 174 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x182), 0x0F0F0F0F}, |
| 175 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x200), 0x00001F0F}, |
| 176 | |
| 177 | // Phy Initialization |
| 178 | {{6, 3, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0B), 0}, |
| 179 | // 3. Phy voltage related |
| 180 | {{1, 1, 1}, DCT0, BFDataRxVioLvl, 0x00000018}, |
| 181 | {{1, 1, 1}, DCT0, BFClkRxVioLvl, 0x00000018}, |
| 182 | {{1, 2, 1}, DCT0, BFCmpVioLvl, 0x0000C000}, |
| 183 | {{1, 1, 1}, DCT0, BFCmdRxVioLvl, 0x00000018}, |
| 184 | {{1, 1, 1}, DCT0, BFAddrRxVioLvl, 0x00000018}, |
| 185 | // 4. Frequency Change |
| 186 | {{4, 3, 1}, DCT0, BFPllLockTime, 0}, |
efdesign98 | 84cbce2 | 2011-08-04 12:09:17 -0600 | [diff] [blame^] | 187 | {{1, 2, 1}, DCT0, BFDllCSRBisaTrimDByte, 0x7000}, |
| 188 | {{1, 2, 1}, DCT0, BFDllCSRBisaTrimClk, 0x7000}, |
| 189 | {{1, 2, 1}, DCT0, BFDllCSRBisaTrimCsOdt, 0x7000}, |
| 190 | {{1, 2, 1}, DCT0, BFDllCSRBisaTrimAByte2, 0x7000}, |
| 191 | {{1, 2, 1}, DCT0, BFReduceLoop, 0x6000}, |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 192 | {{0, 0, 0}, FUNC_2, 0x94, 0xFFD1CC1F}, |
| 193 | // NB Pstate Related Register for Pstate 0 |
| 194 | {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF}, |
| 195 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF}, |
| 196 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF}, |
| 197 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F}, |
| 198 | // Access NB Pstate 1 |
| 199 | {{3, 3, 1}, FUNC_6, 0x98, 0}, |
| 200 | // NB Pstate Related Register for Pstate 1 |
| 201 | {{0, 0, 0}, FUNC_2, 0x78, 0xFFF63FCF}, |
| 202 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x30), 0x00001FFF}, |
| 203 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x31), 0x00001FFF}, |
| 204 | {{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_EXTRA_FLAG, 0, 0x32), 0x00009F9F}, |
| 205 | // Disable Access to NB Pstate 1 |
| 206 | {{2, 3, 1}, FUNC_6, 0x98, 0}, |
| 207 | {{1, 1, 1}, DCT0, BFMemClkFreqVal, 0}, |
| 208 | {{1, 2, 1}, DCT0, BFPllLockTime, 0}, |
| 209 | // 5. Phy Fence |
| 210 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0C), 0x7FFF3FFF}, |
| 211 | {{1, 2, 1}, DCT0, BFDataFence2, 0x00007FFF}, |
| 212 | {{1, 1, 1}, DCT0, BFClkFence2, 0x0000001F}, |
| 213 | {{1, 1, 1}, DCT0, BFCmdFence2, 0x0000001F}, |
| 214 | {{1, 1, 1}, DCT0, BFAddrFence2, 0x0000001F}, |
| 215 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x00), 0x70777777}, |
| 216 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x04), 0x003F3F3F}, |
| 217 | {{1, 1, 1}, DCT0, BFDQOdt03, 0x70}, |
| 218 | {{1, 1, 1}, DCT0, BFDQOdt47, 0x70}, |
| 219 | // 6. Phy Compensation Init |
| 220 | {{5, 3, 1}, DCT0, BFDisablePredriverCal, 0}, |
| 221 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad1, 0}, |
| 222 | {{1, 2, 1}, DCT0, BFDataByteTxPreDriverCal2Pad2, 0}, |
| 223 | {{7, 2, 1}, DCT0, BFDataByteTxPreDriverCal, 0}, |
| 224 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad1, 0}, |
| 225 | {{1, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCal2Pad2, 0}, |
| 226 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad1, 0}, |
| 227 | {{1, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCal2Pad2, 0}, |
| 228 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad1, 0}, |
| 229 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad2, 0}, |
| 230 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad3, 0}, |
| 231 | {{1, 2, 1}, DCT0, BFAddrTxPreDriverCal2Pad4, 0}, |
| 232 | {{7, 2, 1}, DCT0, BFCmdAddr0TxPreDriverCalPad0, 0}, |
| 233 | {{7, 2, 1}, DCT0, BFCmdAddr1TxPreDriverCalPad0, 0}, |
| 234 | {{7, 2, 1}, DCT0, BFAddrTxPreDriverCalPad0, 0}, |
| 235 | {{7, 2, 1}, DCT0, BFClock0TxPreDriverCalPad0, 0}, |
| 236 | {{7, 2, 1}, DCT0, BFClock1TxPreDriverCalPad0, 0}, |
| 237 | |
| 238 | {{1, 2, 1}, DCT0, BFDisablePredriverCal, 0x00006000} |
| 239 | }; |
| 240 | |
| 241 | CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = { |
| 242 | 0, |
| 243 | (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)), |
| 244 | S3PciPreSelfRefDescriptorON, |
| 245 | PciSpecialCaseFuncON |
| 246 | }; |
| 247 | |
| 248 | CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = { |
| 249 | // DCT0 |
| 250 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x01FF01FF, DCT0_MASK, 0x01}, |
| 251 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x01FF01FF, DCT0_MASK, 0x01}, |
| 252 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x01FF01FF, DCT0_MASK, 0x04}, |
| 253 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x01FF01FF, DCT0_MASK, 0x04}, |
| 254 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x01FF01FF, DCT0_MASK, 0x01}, |
| 255 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x01FF01FF, DCT0_MASK, 0x01}, |
| 256 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x01FF01FF, DCT0_MASK, 0x04}, |
| 257 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x24), 0x01FF01FF, DCT0_MASK, 0x04}, |
| 258 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
| 259 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01}, |
| 260 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
| 261 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04}, |
| 262 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 263 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01}, |
| 264 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 265 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x106), 0x3E3E3E3E, DCT0_MASK, 0x04}, |
| 266 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, |
| 267 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, |
| 268 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, |
| 269 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, |
| 270 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, |
| 271 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_DDR3_MASK, 0x01}, |
| 272 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, |
| 273 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x44), 0x00FF00FF, DCT0_DDR3_MASK, 0x04}, |
| 274 | {{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x0D), 0x037F037F, DCT0_MASK, ANY_DIMM_MASK}, |
| 275 | {{1, 1, 1}, DCT0, BFPhyClkConfig0, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, |
| 276 | {{1, 1, 1}, DCT0, BFPhyClkConfig1, 0x00000010, DCT0_MASK, ANY_DIMM_MASK}, |
| 277 | {{1, 1, 1}, DCT0, BFPhy0x0D0F0F13Bit0to7, 0x00000083, DCT0_MASK, ANY_DIMM_MASK}, |
| 278 | {{1, 1, 1}, DCT0, BFAddrCmdTri, 0x0000000B1, DCT0_MASK, ANY_DIMM_MASK}, |
| 279 | {{1, 2, 1}, DCT0, BFLowPowerDrvStrengthEn, 0x00000100, DCT0_MASK, ANY_DIMM_MASK}, |
| 280 | {{1, 2, 1}, DCT0, BFEnRxPadStandby, 0x000001000, DCT0_MASK, ANY_DIMM_MASK}, |
| 281 | {{1, 1, 1}, DCT0, BFDisDllShutdownSR, 0x00000001, DCT0_MASK, ANY_DIMM_MASK}, |
| 282 | |
| 283 | {{0, 0, 0}, FUNC_2, 0x1C0, 0x100000, DCT0_MASK, ANY_DIMM_MASK}, |
| 284 | {{0, 0, 0}, FUNC_3, 0x84, 0x00060006, DCT0_MASK, ANY_DIMM_MASK}, |
| 285 | {{0, 2, 0}, FUNC_4, 0x12C, 0x0000FFFF, DCT0_MASK, ANY_DIMM_MASK}, |
| 286 | {{0, 0, 0}, FUNC_4, 0x1A8, 0x3F000000, DCT0_MASK, ANY_DIMM_MASK}, |
| 287 | {{0, 0, 0}, FUNC_3, 0x188, 0x00400000, DCT0_MASK, ANY_DIMM_MASK}, |
| 288 | {{0, 2, 0}, FUNC_6, 0x78, 0x0000FF00, DCT0_MASK, ANY_DIMM_MASK}, |
| 289 | // Release NB P-state force |
| 290 | {{0, 0, 0}, FUNC_6, 0x90, 0x50000000, DCT0_MASK, ANY_DIMM_MASK}, |
| 291 | {{0, 0, 0}, FUNC_2, 0x118, 0x00080000, DCT0_MASK, ANY_DIMM_MASK} |
| 292 | }; |
| 293 | |
| 294 | CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = { |
| 295 | 0, |
| 296 | (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)), |
| 297 | S3CPciPostSelfDescriptorON, |
| 298 | PciSpecialCaseFuncON |
| 299 | }; |
| 300 | |
| 301 | MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = { |
| 302 | {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, |
| 303 | {{0, 0, 0}, 0xC001001A, 0x0000000FFF800000}, |
| 304 | {{0, 0, 0}, 0xC001001D, 0x0000000FFF800000}, |
| 305 | {{0, 0, 0}, 0xC001001F, 0x8480FC6A434243E0} |
| 306 | }; |
| 307 | |
| 308 | CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = { |
| 309 | 0, |
| 310 | (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)), |
| 311 | S3MSRPreSelfRefDescriptorON, |
| 312 | NULL |
| 313 | }; |
| 314 | |
| 315 | VOID *MemS3RegListON[] = { |
| 316 | (VOID *)&S3PciPreSelfRefON, |
| 317 | NULL, |
| 318 | NULL, |
| 319 | (VOID *)&S3CPciPostSelfRefON, |
| 320 | (VOID *)&S3MSRPreSelfRefON, |
| 321 | NULL, |
| 322 | NULL, |
| 323 | NULL |
| 324 | }; |
| 325 | |
| 326 | /*---------------------------------------------------------------------------- |
| 327 | * EXPORTED FUNCTIONS |
| 328 | * |
| 329 | *---------------------------------------------------------------------------- |
| 330 | */ |
| 331 | /* -----------------------------------------------------------------------------*/ |
| 332 | /** |
| 333 | * |
| 334 | * |
| 335 | * This function initializes the northbridge block for S3 resume |
| 336 | * |
| 337 | * @param[in,out] *S3NBPtr - Pointer to MEM_NB_BLOCK. |
| 338 | * @param[in,out] *MemPtr - Pointer to MEM_DATA_STRUCT. |
| 339 | * @param[in] NodeID - Node ID of the target node. |
| 340 | * |
| 341 | * @return BOOLEAN |
| 342 | * TRUE - This is the correct constructor for the targeted node. |
| 343 | * FALSE - This isn't the correct constructor for the targeted node. |
| 344 | */ |
| 345 | BOOLEAN |
| 346 | MemS3ResumeConstructNBBlockON ( |
| 347 | IN OUT VOID *S3NBPtr, |
| 348 | IN OUT MEM_DATA_STRUCT *MemPtr, |
| 349 | IN UINT8 NodeID |
| 350 | ) |
| 351 | { |
| 352 | INT32 i; |
| 353 | MEM_NB_BLOCK *NBPtr; |
| 354 | |
| 355 | NBPtr = ((S3_MEM_NB_BLOCK *)S3NBPtr)->NBPtr; |
| 356 | |
| 357 | // |
| 358 | // Determine if this is the expected NB Type |
| 359 | // |
| 360 | GetLogicalIdOfSocket (MemPtr->DiesPerSystem[NodeID].SocketId, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid), &(MemPtr->StdHeader)); |
| 361 | if (!MemNIsIdSupportedON (NBPtr, &(MemPtr->DiesPerSystem[NodeID].LogicalCpuid))) { |
| 362 | return FALSE; |
| 363 | } |
| 364 | |
| 365 | NBPtr->MemPtr = MemPtr; |
| 366 | NBPtr->MCTPtr = &(MemPtr->DiesPerSystem[NodeID]); |
| 367 | NBPtr->PciAddr.AddressValue = MemPtr->DiesPerSystem[NodeID].PciAddr.AddressValue; |
| 368 | MemNInitNBRegTableON (NBPtr, NBPtr->NBRegTable); |
| 369 | NBPtr->Node = ((UINT8) NBPtr->PciAddr.Address.Device) - 24; |
| 370 | NBPtr->Dct = 0; |
| 371 | NBPtr->Channel = 0; |
| 372 | NBPtr->Ganged = FALSE; |
| 373 | NBPtr->NodeCount = MAX_NODES_SUPPORTED_ON; |
| 374 | NBPtr->DctCount = MAX_DCTS_PER_NODE_ON; |
| 375 | |
| 376 | for (i = 0; i < EnumSize; i++) { |
| 377 | NBPtr->IsSupported[i] = FALSE; |
| 378 | } |
| 379 | |
| 380 | for (i = 0; i < NumberOfHooks; i++) { |
| 381 | NBPtr->FamilySpecificHook[i] = (BOOLEAN (*) (MEM_NB_BLOCK *, VOID *)) memDefTrue; |
| 382 | } |
| 383 | |
| 384 | LibAmdMemFill (NBPtr->DctCache, 0, sizeof (NBPtr->DctCache), &MemPtr->StdHeader); |
| 385 | |
| 386 | NBPtr->SwitchDCT = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; |
| 387 | NBPtr->SwitchChannel = (VOID (*) (MEM_NB_BLOCK*, UINT8)) memDefRet; |
| 388 | NBPtr->MemNCmnGetSetFieldNb = MemNCmnGetSetFieldON; |
| 389 | NBPtr->GetBitField = MemNGetBitFieldNb; |
| 390 | NBPtr->SetBitField = MemNSetBitFieldNb; |
| 391 | NBPtr->MemNIsIdSupportedNb = MemNIsIdSupportedON; |
| 392 | NBPtr->ChangeNbFrequencyWrap = MemNS3ChangeNbFrequencyWrapON; |
| 393 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3ExitSelfRefReg = (VOID (*) (MEM_NB_BLOCK *, AMD_CONFIG_PARAMS *)) memDefRet; |
| 394 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConPCIMask = MemNS3GetConPCIMaskON; |
| 395 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetConMSRMask = (VOID (*) (MEM_NB_BLOCK *, DESCRIPTOR_GROUP *)) memDefRet; |
| 396 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3Resume = MemNS3ResumeClientNb; |
| 397 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3RestoreScrub = (VOID (*) (MEM_NB_BLOCK *, UINT8)) memDefRet; |
| 398 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetRegLstPtr = MemNS3GetRegLstPtrON; |
| 399 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3GetDeviceRegLst = MemNS3GetDeviceRegLstON; |
| 400 | ((S3_MEM_NB_BLOCK *)S3NBPtr)->MemS3SpecialCaseHeapSize = 0; |
| 401 | |
| 402 | return TRUE; |
| 403 | } |
| 404 | |
| 405 | /*---------------------------------------------------------------------------- |
| 406 | * LOCAL FUNCTIONS |
| 407 | * |
| 408 | *----------------------------------------------------------------------------*/ |
| 409 | /* -----------------------------------------------------------------------------*/ |
| 410 | /** |
| 411 | * |
| 412 | * |
| 413 | * This function returns the conditional PCI device mask |
| 414 | * |
| 415 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 416 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 417 | * @return none |
| 418 | */ |
| 419 | VOID |
| 420 | STATIC |
| 421 | MemNS3GetConPCIMaskON ( |
| 422 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 423 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 424 | ) |
| 425 | { |
| 426 | BIT_FIELD_NAME bitfield; |
| 427 | UINT32 RegVal; |
| 428 | UINT8 DimmMask; |
| 429 | |
| 430 | DimmMask = 0; |
| 431 | for (bitfield = BFCSBaseAddr0Reg; bitfield <= BFCSBaseAddr3Reg; bitfield ++) { |
| 432 | RegVal = MemNGetBitFieldNb (NBPtr, bitfield); |
| 433 | if (RegVal & 0x1) { |
| 434 | DimmMask |= (UINT8) (1 << (((bitfield - BFCSBaseAddr0Reg) >> 1) << 1)); |
| 435 | } |
| 436 | } |
| 437 | |
| 438 | // Set mask before exit self refresh |
| 439 | DescriptPtr->CPCIDevice[PRESELFREF].Mask1 = 1; |
| 440 | // Set mask after exit self refresh |
| 441 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 = 1; |
| 442 | // Set DDR3 mask if Dimms present are DDR3 |
| 443 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 |= (DescriptPtr->CPCIDevice[POSTSELFREF].Mask1 << 4); |
| 444 | |
| 445 | // Set dimm mask |
| 446 | DescriptPtr->CPCIDevice[PRESELFREF].Mask2 = DimmMask; |
| 447 | DescriptPtr->CPCIDevice[POSTSELFREF].Mask2 = DimmMask; |
| 448 | } |
| 449 | |
| 450 | /* -----------------------------------------------------------------------------*/ |
| 451 | /** |
| 452 | * |
| 453 | * |
| 454 | * This function returns the register list for each device for LN |
| 455 | * |
| 456 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 457 | * @param[in, out] *DescriptPtr - Pointer to DESCRIPTOR_GROUP |
| 458 | * @return UINT16 - size of the device descriptor on the target node. |
| 459 | */ |
| 460 | UINT16 |
| 461 | STATIC |
| 462 | MemNS3GetRegLstPtrON ( |
| 463 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 464 | IN OUT DESCRIPTOR_GROUP *DescriptPtr |
| 465 | ) |
| 466 | { |
| 467 | UINT8 i; |
| 468 | UINT16 Size; |
| 469 | Size = 0; |
| 470 | for (i = PRESELFREF; i <= POSTSELFREF; i ++) { |
| 471 | DescriptPtr->PCIDevice[i].Type = (UINT8) (DEV_TYPE_PCI_PRE_ESR + i); |
| 472 | DescriptPtr->PCIDevice[i].Node = NBPtr->Node; |
| 473 | DescriptPtr->PCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 474 | if ((PCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[PCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { |
| 475 | DescriptPtr->PCIDevice[i].RegisterListID = PCI_LST_ESR_ON + i; |
| 476 | Size += sizeof (PCI_DEVICE_DESCRIPTOR); |
| 477 | } |
| 478 | DescriptPtr->CPCIDevice[i].Type = (UINT8) (DEV_TYPE_CPCI_PRE_ESR + i); |
| 479 | DescriptPtr->CPCIDevice[i].Node = NBPtr->Node; |
| 480 | DescriptPtr->CPCIDevice[i].RegisterListID = 0xFFFFFFFF; |
| 481 | if ((CPCI_REGISTER_BLOCK_HEADER *) MemS3RegListON[CPCI_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { |
| 482 | DescriptPtr->CPCIDevice[i].RegisterListID = CPCI_LST_ESR_ON + i; |
| 483 | Size += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); |
| 484 | } |
| 485 | DescriptPtr->MSRDevice[i].Type = (UINT8) (DEV_TYPE_MSR_PRE_ESR + i); |
| 486 | DescriptPtr->MSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 487 | if ((MSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[MSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { |
| 488 | DescriptPtr->MSRDevice[i].RegisterListID = MSR_LST_ESR_ON + i; |
| 489 | Size += sizeof (MSR_DEVICE_DESCRIPTOR); |
| 490 | } |
| 491 | DescriptPtr->CMSRDevice[i].Type = (UINT8) (DEV_TYPE_CMSR_PRE_ESR + i); |
| 492 | DescriptPtr->CMSRDevice[i].RegisterListID = 0xFFFFFFFF; |
| 493 | if ((CMSR_REGISTER_BLOCK_HEADER *) MemS3RegListON[CMSR_LST_ESR_ON - PCI_LST_ESR_ON + i] != NULL) { |
| 494 | DescriptPtr->CMSRDevice[i].RegisterListID = CMSR_LST_ESR_ON + i; |
| 495 | Size += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); |
| 496 | } |
| 497 | } |
| 498 | return Size; |
| 499 | } |
| 500 | |
| 501 | /* -----------------------------------------------------------------------------*/ |
| 502 | /** |
| 503 | * |
| 504 | * |
| 505 | * This function return the register list according to the register ID. |
| 506 | * |
| 507 | * @param[in] RegisterLstID - value of the Register list ID. |
| 508 | * @param[out] **RegisterHeader - pointer to the address of the register list. |
| 509 | * @return none |
| 510 | */ |
| 511 | AGESA_STATUS |
| 512 | STATIC |
| 513 | MemNS3GetDeviceRegLstON ( |
| 514 | IN UINT32 RegisterLstID, |
| 515 | OUT VOID **RegisterHeader |
| 516 | ) |
| 517 | { |
| 518 | if (RegisterLstID >= (sizeof (MemS3RegListON) / sizeof (VOID *))) { |
| 519 | ASSERT(FALSE); // RegisterListID exceeded size of Register list |
| 520 | return AGESA_FATAL; |
| 521 | } |
| 522 | if (MemS3RegListON[RegisterLstID] != NULL) { |
| 523 | *RegisterHeader = MemS3RegListON[RegisterLstID]; |
| 524 | return AGESA_SUCCESS; |
| 525 | } |
| 526 | ASSERT(FALSE); // Device regiser list error |
| 527 | return AGESA_FATAL; |
| 528 | } |
| 529 | |
| 530 | /* -----------------------------------------------------------------------------*/ |
| 531 | /** |
| 532 | * |
| 533 | * |
| 534 | * This function that set PllLockTime to default state. |
| 535 | * |
| 536 | * @param[in] AccessWidth - Access width of the register. |
| 537 | * @param[in] Address - address in PCI_ADDR format. |
| 538 | * @param[in, out] *Value - Pointer to the value to be written. |
| 539 | * @param[in, out] *ConfigPtr - Pointer to Config handle. |
| 540 | * @return none |
| 541 | */ |
| 542 | VOID |
| 543 | STATIC |
| 544 | MemNS3SetDfltPllLockTimeON ( |
| 545 | IN ACCESS_WIDTH AccessWidth, |
| 546 | IN PCI_ADDR Address, |
| 547 | IN OUT VOID *Value, |
| 548 | IN OUT VOID *ConfigPtr |
| 549 | ) |
| 550 | { |
| 551 | UINT16 RegValue; |
| 552 | |
| 553 | RegValue = 0x1838; |
| 554 | MemNS3SetBitFieldNb (AccessS3SaveWidth16, Address, &RegValue, ConfigPtr); |
| 555 | } |
| 556 | |
| 557 | /* -----------------------------------------------------------------------------*/ |
| 558 | /** |
| 559 | * |
| 560 | * This function is a wrapper to call a CPU routine to change NB P-state and |
| 561 | * update NB frequency. |
| 562 | * |
| 563 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 564 | * @param[in] *NBPstate - NB Pstate |
| 565 | * |
| 566 | * @return TRUE - Succeed |
| 567 | * @return FALSE - Fail |
| 568 | */ |
| 569 | |
| 570 | BOOLEAN |
| 571 | STATIC |
| 572 | MemNS3ChangeNbFrequencyWrapON ( |
| 573 | IN OUT MEM_NB_BLOCK *NBPtr, |
| 574 | IN UINT32 NBPstate |
| 575 | ) |
| 576 | { |
| 577 | BOOLEAN Status; |
| 578 | UINT32 NBFreq; |
| 579 | UINT32 Speed; |
| 580 | |
| 581 | Speed = MemNGetBitFieldNb (NBPtr, BFMemClkFreq); |
| 582 | Status = F14NbPstateInit (((Speed + 6) * 3335) / 100, |
| 583 | Speed, |
| 584 | NBPstate, |
| 585 | &NBFreq, |
| 586 | &(NBPtr->MemPtr->StdHeader)); |
| 587 | |
| 588 | return Status; |
| 589 | } |