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review.coreboot.org / coreboot / 834b3ecd7cbefbad8f09a9bda4f10cd7842cdbcd / . / src / mainboard / google / kahlee / variants / nuwani / mainboard.c
blob: ce98d62c18450e264667c0a168476d30bc614605 [file] [log] [blame]
Angel Ponsb5a2a522020-04-05 13:21:48 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Peichao Wangdbc95842020-03-05 17:02:58 +0800[diff] [blame]2
3#include <ec/google/chromeec/ec.h>
4#include <baseboard/variants.h>
5#include <boardid.h>
6#include <cbfs.h>
7#include <gpio.h>
8#include <smbios.h>
9#include <variant/gpio.h>
10#include <device/mmio.h>
11#include <device/pci.h>
12#include <device/pci_ops.h>
13#include <drivers/generic/bayhub/bh720.h>
14
15uint32_t sku_id(void)
16{
17 static int sku = -1;
18
19 if (sku == -1)
20 sku = google_chromeec_get_sku_id();
21
22 return sku;
23}
24
25uint8_t variant_board_sku(void)
26{
27 return sku_id();
28}
29
30void variant_mainboard_suspend_resume(void)
31{
32 /* Enable backlight - GPIO 133 active low */
33 gpio_set(GPIO_133, 0);
34}
35
36void board_bh720(struct device *dev)
37{
38 u32 sdbar;
39 u32 bh720_pcr_data;
40
41 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
42
43 /* Enable Memory Access Function */
44 write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
45 write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
46 write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
47
48 /* Set EMMC VCCQ 1.8V PCR 0x308[4] */
49 write32((void *)(sdbar + BH720_MEM_RW_ADR),
50 BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING);
51 bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
52 write32((void *)(sdbar + BH720_MEM_RW_DATA),
53 bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V);
54 write32((void *)(sdbar + BH720_MEM_RW_ADR),
55 BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
56
57 /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
58 write32((void *)(sdbar + BH720_MEM_RW_ADR),
59 BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
60 bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
61 bh720_pcr_data &= 0x0000FFFF;
62 bh720_pcr_data |= 0x2510 << 16;
63 write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
64 write32((void *)(sdbar + BH720_MEM_RW_ADR),
65 BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
66
67 /* Use PLL Base clock PCR 0x3E4[22] = 1 */
68 write32((void *)(sdbar + BH720_MEM_RW_ADR),
69 BH720_MEM_RW_READ | BH720_PCR_CSR);
70 bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
71 write32((void *)(sdbar + BH720_MEM_RW_DATA),
72 bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
73 write32((void *)(sdbar + BH720_MEM_RW_ADR),
74 BH720_MEM_RW_WRITE | BH720_PCR_CSR);
75
76 /* Disable Memory Access */
77 write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
78 write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
79 write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
80
81 /* Tune VIH */
82 pci_write_config32(dev, BH720_PROTECT,
83 BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
84 bh720_pcr_data = pci_read_config32(dev, BH720_PCR_DrvStrength_PLL);
85 bh720_pcr_data &= 0xFFFFFF00;
86 /* CLK = 3 and DAT = 2 */
87 bh720_pcr_data |= 0x35;
88 pci_write_config32(dev, BH720_PCR_DrvStrength_PLL, bh720_pcr_data);
89 pci_write_config32(dev, BH720_PROTECT,
90 BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
91}
92
Peichao Wangdbc95842020-03-05 17:02:58 +0800[diff] [blame]93const char *smbios_mainboard_manufacturer(void)
94{
95 static char oem_bin_data[11];
96 static const char *manuf;
97
98 if (!CONFIG(USE_OEM_BIN))
99 return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
100
101 if (manuf)
102 return manuf;
103
Julius Werner834b3ec2020-03-04 16:52:08 -0800[diff] [blame^]104 if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1))
Peichao Wangdbc95842020-03-05 17:02:58 +0800[diff] [blame]105 manuf = &oem_bin_data[0];
106 else
107 manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
108
109 return manuf;
110}