Angel Pons | b5a2a52 | 2020-04-05 13:21:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | ecb4491 | 2018-05-24 16:55:10 -0600 | [diff] [blame] | 2 | |
| 3 | #include <ec/google/chromeec/ec.h> |
| 4 | #include <baseboard/variants.h> |
Peichao Wang | 4510a8f | 2019-09-03 07:52:18 +0800 | [diff] [blame] | 5 | #include <boardid.h> |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 6 | #include <cbfs.h> |
Marc Jones | 290c445 | 2018-07-14 17:37:30 -0600 | [diff] [blame] | 7 | #include <gpio.h> |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 8 | #include <smbios.h> |
Marc Jones | 290c445 | 2018-07-14 17:37:30 -0600 | [diff] [blame] | 9 | #include <variant/gpio.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 10 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Kevin Chiu | 328ff7d | 2018-08-27 11:44:46 +0800 | [diff] [blame] | 12 | #include <drivers/generic/bayhub/bh720.h> |
Martin Roth | ecb4491 | 2018-05-24 16:55:10 -0600 | [diff] [blame] | 13 | |
Peichao Wang | 4510a8f | 2019-09-03 07:52:18 +0800 | [diff] [blame] | 14 | uint32_t sku_id(void) |
Martin Roth | ecb4491 | 2018-05-24 16:55:10 -0600 | [diff] [blame] | 15 | { |
| 16 | static int sku = -1; |
| 17 | |
| 18 | if (sku == -1) |
| 19 | sku = google_chromeec_get_sku_id(); |
| 20 | |
| 21 | return sku; |
| 22 | } |
Marc Jones | 290c445 | 2018-07-14 17:37:30 -0600 | [diff] [blame] | 23 | |
Peichao Wang | 4510a8f | 2019-09-03 07:52:18 +0800 | [diff] [blame] | 24 | uint8_t variant_board_sku(void) |
| 25 | { |
| 26 | return sku_id(); |
| 27 | } |
| 28 | |
Marc Jones | 290c445 | 2018-07-14 17:37:30 -0600 | [diff] [blame] | 29 | void variant_mainboard_suspend_resume(void) |
| 30 | { |
| 31 | /* Enable backlight - GPIO 133 active low */ |
| 32 | gpio_set(GPIO_133, 0); |
| 33 | } |
Kevin Chiu | 328ff7d | 2018-08-27 11:44:46 +0800 | [diff] [blame] | 34 | |
| 35 | void board_bh720(struct device *dev) |
| 36 | { |
| 37 | u32 sdbar; |
| 38 | u32 bh720_pcr_data; |
| 39 | |
| 40 | sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); |
| 41 | |
| 42 | /* Enable Memory Access Function */ |
| 43 | write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); |
| 44 | write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); |
| 45 | write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); |
| 46 | |
| 47 | /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ |
| 48 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 49 | BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); |
| 50 | bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); |
| 51 | write32((void *)(sdbar + BH720_MEM_RW_DATA), |
| 52 | bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); |
| 53 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 54 | BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); |
| 55 | |
Raul E Rangel | 1264d64 | 2019-06-12 16:38:15 -0600 | [diff] [blame] | 56 | /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ |
| 57 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 58 | BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); |
| 59 | bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); |
| 60 | bh720_pcr_data &= 0x0000FFFF; |
| 61 | bh720_pcr_data |= 0x2510 << 16; |
| 62 | write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); |
| 63 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 64 | BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); |
| 65 | |
| 66 | /* Use PLL Base clock PCR 0x3E4[22] = 1 */ |
Kevin Chiu | 328ff7d | 2018-08-27 11:44:46 +0800 | [diff] [blame] | 67 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 68 | BH720_MEM_RW_READ | BH720_PCR_CSR); |
| 69 | bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); |
| 70 | write32((void *)(sdbar + BH720_MEM_RW_DATA), |
Raul E Rangel | 1264d64 | 2019-06-12 16:38:15 -0600 | [diff] [blame] | 71 | bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); |
Kevin Chiu | 328ff7d | 2018-08-27 11:44:46 +0800 | [diff] [blame] | 72 | write32((void *)(sdbar + BH720_MEM_RW_ADR), |
| 73 | BH720_MEM_RW_WRITE | BH720_PCR_CSR); |
| 74 | |
| 75 | /* Disable Memory Access */ |
| 76 | write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); |
| 77 | write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); |
| 78 | write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); |
| 79 | } |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 80 | |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 81 | const char *smbios_mainboard_manufacturer(void) |
| 82 | { |
Kevin Chiu | 0fa007b | 2018-10-03 10:12:44 +0800 | [diff] [blame] | 83 | static char oem_bin_data[11]; |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 84 | static const char *manuf; |
| 85 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 86 | if (!CONFIG(USE_OEM_BIN)) |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 87 | return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; |
| 88 | |
| 89 | if (manuf) |
| 90 | return manuf; |
| 91 | |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame^] | 92 | if (cbfs_load("oem.bin", oem_bin_data, sizeof(oem_bin_data) - 1)) |
Martin Roth | 1f42a38 | 2018-09-24 15:39:12 -0600 | [diff] [blame] | 93 | manuf = &oem_bin_data[0]; |
| 94 | else |
Martin Roth | 4ae44fc | 2018-09-17 13:30:51 -0600 | [diff] [blame] | 95 | manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; |
| 96 | |
| 97 | return manuf; |
| 98 | } |