Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 2 | |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 3 | /* Microcode update for Intel PIII and later CPUs */ |
| 4 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 5 | #include <stdint.h> |
Vladimir Serbinenko | 2c88cc0 | 2013-03-30 12:04:23 +0100 | [diff] [blame] | 6 | #include <stddef.h> |
Aaron Durbin | a02bb65 | 2016-02-05 14:58:06 -0600 | [diff] [blame] | 7 | #include <cbfs.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 8 | #include <arch/cpu.h> |
Kyösti Mälkki | 92bb832 | 2019-09-24 22:40:43 +0300 | [diff] [blame] | 9 | #include <console/console.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 10 | #include <cpu/x86/msr.h> |
| 11 | #include <cpu/intel/microcode.h> |
Stefan Reinauer | a42e2f4 | 2012-10-15 13:18:06 -0700 | [diff] [blame] | 12 | #include <smp/spinlock.h> |
Kyösti Mälkki | 89c0ef7 | 2019-09-24 08:56:36 +0300 | [diff] [blame] | 13 | |
Stefan Reinauer | a42e2f4 | 2012-10-15 13:18:06 -0700 | [diff] [blame] | 14 | DECLARE_SPIN_LOCK(microcode_lock) |
Vadim Bendebury | 537b4e0 | 2012-06-19 12:56:57 -0700 | [diff] [blame] | 15 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 16 | struct microcode { |
Stefan Reinauer | c8f8a6c | 2010-05-26 12:53:43 +0000 | [diff] [blame] | 17 | u32 hdrver; /* Header Version */ |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 18 | u32 rev; /* Update Revision */ |
| 19 | u32 date; /* Date */ |
| 20 | u32 sig; /* Processor Signature */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 21 | |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 22 | u32 cksum; /* Checksum */ |
| 23 | u32 ldrver; /* Loader Revision */ |
| 24 | u32 pf; /* Processor Flags */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 25 | |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 26 | u32 data_size; /* Data Size */ |
| 27 | u32 total_size; /* Total Size */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 28 | |
Stefan Reinauer | c8f8a6c | 2010-05-26 12:53:43 +0000 | [diff] [blame] | 29 | u32 reserved[3]; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 30 | }; |
| 31 | |
Stefan Reinauer | c8f8a6c | 2010-05-26 12:53:43 +0000 | [diff] [blame] | 32 | static inline u32 read_microcode_rev(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 33 | { |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 34 | /* Some Intel CPUs can be very finicky about the |
Stefan Reinauer | c8f8a6c | 2010-05-26 12:53:43 +0000 | [diff] [blame] | 35 | * CPUID sequence used. So this is implemented in |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 36 | * assembly so that it works reliably. |
| 37 | */ |
| 38 | msr_t msr; |
Stefan Reinauer | 3f8989e | 2012-04-25 22:58:23 +0200 | [diff] [blame] | 39 | asm volatile ( |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 40 | "xorl %%eax, %%eax\n\t" |
| 41 | "xorl %%edx, %%edx\n\t" |
| 42 | "movl $0x8b, %%ecx\n\t" |
| 43 | "wrmsr\n\t" |
| 44 | "movl $0x01, %%eax\n\t" |
| 45 | "cpuid\n\t" |
| 46 | "movl $0x08b, %%ecx\n\t" |
Elyes HAOUAS | 7c8d74c | 2016-08-23 21:41:43 +0200 | [diff] [blame] | 47 | "rdmsr\n\t" |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 48 | : /* outputs */ |
| 49 | "=a" (msr.lo), "=d" (msr.hi) |
| 50 | : /* inputs */ |
| 51 | : /* trashed */ |
Stefan Reinauer | 3b5a9ed | 2012-05-02 16:41:55 -0700 | [diff] [blame] | 52 | "ebx", "ecx" |
Stefan Reinauer | c8f8a6c | 2010-05-26 12:53:43 +0000 | [diff] [blame] | 53 | ); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 54 | return msr.hi; |
| 55 | } |
| 56 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 57 | #define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" |
| 58 | |
| 59 | void intel_microcode_load_unlocked(const void *microcode_patch) |
| 60 | { |
| 61 | u32 current_rev; |
| 62 | msr_t msr; |
| 63 | const struct microcode *m = microcode_patch; |
| 64 | |
| 65 | if (!m) |
| 66 | return; |
| 67 | |
| 68 | current_rev = read_microcode_rev(); |
| 69 | |
| 70 | /* No use loading the same revision. */ |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 71 | if (current_rev == m->rev) { |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 72 | printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n"); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 73 | return; |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 74 | } |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 75 | |
Rizwan Qureshi | 30b755b | 2015-07-23 22:31:51 +0530 | [diff] [blame] | 76 | #if ENV_RAMSTAGE |
| 77 | /*SoC specific check to update microcode*/ |
| 78 | if (soc_skip_ucode_update(current_rev, m->rev)) { |
| 79 | printk(BIOS_DEBUG, "Skip microcode update\n"); |
| 80 | return; |
| 81 | } |
| 82 | #endif |
| 83 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 84 | msr.lo = (unsigned long)m + sizeof(struct microcode); |
| 85 | msr.hi = 0; |
Elyes HAOUAS | 603963e | 2018-09-28 09:06:43 +0200 | [diff] [blame] | 86 | wrmsr(IA32_BIOS_UPDT_TRIG, msr); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 87 | |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 88 | current_rev = read_microcode_rev(); |
| 89 | if (current_rev == m->rev) { |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 90 | printk(BIOS_INFO, "microcode: updated to revision " |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 91 | "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(), |
| 92 | m->date & 0xffff, (m->date >> 24) & 0xff, |
| 93 | (m->date >> 16) & 0xff); |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 94 | return; |
| 95 | } |
| 96 | |
Philipp Deppenwiese | b251c02 | 2018-11-27 14:02:15 +0100 | [diff] [blame] | 97 | printk(BIOS_INFO, "microcode: Update failed\n"); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 98 | } |
| 99 | |
Rizwan Qureshi | 0d39157 | 2018-07-02 21:12:40 +0530 | [diff] [blame] | 100 | uint32_t get_current_microcode_rev(void) |
| 101 | { |
| 102 | return read_microcode_rev(); |
| 103 | } |
| 104 | |
| 105 | uint32_t get_microcode_rev(const void *microcode) |
| 106 | { |
| 107 | return ((struct microcode *)microcode)->rev; |
| 108 | } |
| 109 | |
| 110 | uint32_t get_microcode_size(const void *microcode) |
| 111 | { |
| 112 | return ((struct microcode *)microcode)->total_size; |
| 113 | } |
| 114 | |
| 115 | uint32_t get_microcode_checksum(const void *microcode) |
| 116 | { |
| 117 | return ((struct microcode *)microcode)->cksum; |
| 118 | } |
| 119 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 120 | const void *intel_microcode_find(void) |
| 121 | { |
Aaron Durbin | e676767 | 2014-01-27 15:52:47 -0600 | [diff] [blame] | 122 | const struct microcode *ucode_updates; |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 123 | size_t microcode_len; |
| 124 | u32 eax; |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 125 | u32 pf, rev, sig, update_size; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 126 | unsigned int x86_model, x86_family; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 127 | msr_t msr; |
| 128 | |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame^] | 129 | ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, µcode_len); |
Aaron Durbin | 899d13d | 2015-05-15 23:39:23 -0500 | [diff] [blame] | 130 | if (ucode_updates == NULL) |
| 131 | return NULL; |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 132 | |
Elyes HAOUAS | 603963e | 2018-09-28 09:06:43 +0200 | [diff] [blame] | 133 | /* CPUID sets MSR 0x8B if a microcode update has been loaded. */ |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 134 | msr.lo = 0; |
| 135 | msr.hi = 0; |
Elyes HAOUAS | 603963e | 2018-09-28 09:06:43 +0200 | [diff] [blame] | 136 | wrmsr(IA32_BIOS_SIGN_ID, msr); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 137 | eax = cpuid_eax(1); |
Elyes HAOUAS | 603963e | 2018-09-28 09:06:43 +0200 | [diff] [blame] | 138 | msr = rdmsr(IA32_BIOS_SIGN_ID); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 139 | rev = msr.hi; |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 140 | x86_model = (eax >> 4) & 0x0f; |
| 141 | x86_family = (eax >> 8) & 0x0f; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 142 | sig = eax; |
| 143 | |
| 144 | pf = 0; |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 145 | if ((x86_model >= 5) || (x86_family > 6)) { |
Elyes HAOUAS | 603963e | 2018-09-28 09:06:43 +0200 | [diff] [blame] | 146 | msr = rdmsr(IA32_PLATFORM_ID); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 147 | pf = 1 << ((msr.hi >> 18) & 7); |
| 148 | } |
Kyösti Mälkki | 92bb832 | 2019-09-24 22:40:43 +0300 | [diff] [blame] | 149 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 150 | printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", |
| 151 | sig, pf, rev); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 152 | |
Aaron Durbin | e676767 | 2014-01-27 15:52:47 -0600 | [diff] [blame] | 153 | while (microcode_len >= sizeof(*ucode_updates)) { |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 154 | /* Newer microcode updates include a size field, whereas older |
| 155 | * containers set it at 0 and are exactly 2048 bytes long */ |
Aaron Durbin | e676767 | 2014-01-27 15:52:47 -0600 | [diff] [blame] | 156 | if (ucode_updates->total_size) { |
| 157 | update_size = ucode_updates->total_size; |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 158 | } else { |
Alexandru Gagniuc | 2c38f50 | 2013-12-06 23:14:54 -0600 | [diff] [blame] | 159 | printk(BIOS_SPEW, "Microcode size field is 0\n"); |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 160 | update_size = 2048; |
| 161 | } |
| 162 | |
| 163 | /* Checkpoint 1: The microcode update falls within CBFS */ |
Elyes HAOUAS | cbe7464c | 2016-08-23 21:07:28 +0200 | [diff] [blame] | 164 | if (update_size > microcode_len) { |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 165 | printk(BIOS_WARNING, "Microcode header corrupted!\n"); |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 166 | break; |
| 167 | } |
| 168 | |
Aaron Durbin | e676767 | 2014-01-27 15:52:47 -0600 | [diff] [blame] | 169 | if ((ucode_updates->sig == sig) && (ucode_updates->pf & pf)) |
| 170 | return ucode_updates; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 171 | |
Aaron Durbin | e676767 | 2014-01-27 15:52:47 -0600 | [diff] [blame] | 172 | ucode_updates = (void *)((char *)ucode_updates + update_size); |
Alexandru Gagniuc | b1ae030 | 2013-12-08 16:30:07 -0600 | [diff] [blame] | 173 | microcode_len -= update_size; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 174 | } |
| 175 | |
Elyes HAOUAS | 9612a3c | 2019-12-16 05:46:16 +0100 | [diff] [blame] | 176 | return NULL; |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | void intel_update_microcode_from_cbfs(void) |
| 180 | { |
| 181 | const void *patch = intel_microcode_find(); |
| 182 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 183 | spin_lock(µcode_lock); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 184 | |
| 185 | intel_microcode_load_unlocked(patch); |
| 186 | |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 187 | spin_unlock(µcode_lock); |
Aaron Durbin | 98ffb42 | 2013-01-15 15:15:32 -0600 | [diff] [blame] | 188 | } |
Rizwan Qureshi | 30b755b | 2015-07-23 22:31:51 +0530 | [diff] [blame] | 189 | |
| 190 | #if ENV_RAMSTAGE |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 191 | __weak int soc_skip_ucode_update(u32 currrent_patch_id, |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 192 | u32 new_patch_id) |
Rizwan Qureshi | 30b755b | 2015-07-23 22:31:51 +0530 | [diff] [blame] | 193 | { |
| 194 | return 0; |
| 195 | } |
| 196 | #endif |