Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | #include <arch/io.h> |
| 20 | #include <string.h> |
| 21 | #include <types.h> |
| 22 | #include <console/console.h> |
| 23 | #include <delay.h> |
| 24 | #include "addressmap.h" |
| 25 | #include "clock.h" |
| 26 | #include "sdram.h" |
| 27 | #include "grf.h" |
huang lin | 82ba4d0 | 2014-08-16 10:49:32 +0800 | [diff] [blame^] | 28 | #include "soc.h" |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 29 | #include "pmu.h" |
| 30 | |
| 31 | struct rk3288_ddr_pctl_regs { |
| 32 | u32 scfg; |
| 33 | u32 sctl; |
| 34 | u32 stat; |
| 35 | u32 intrstat; |
| 36 | u32 reserved0[12]; |
| 37 | u32 mcmd; |
| 38 | u32 powctl; |
| 39 | u32 powstat; |
| 40 | u32 cmdtstat; |
| 41 | u32 tstaten; |
| 42 | u32 reserved1[3]; |
| 43 | u32 mrrcfg0; |
| 44 | u32 mrrstat0; |
| 45 | u32 mrrstat1; |
| 46 | u32 reserved2[4]; |
| 47 | u32 mcfg1; |
| 48 | u32 mcfg; |
| 49 | u32 ppcfg; |
| 50 | u32 mstat; |
| 51 | u32 lpddr2zqcfg; |
| 52 | u32 reserved3; |
| 53 | u32 dtupdes; |
| 54 | u32 dtuna; |
| 55 | u32 dtune; |
| 56 | u32 dtuprd0; |
| 57 | u32 dtuprd1; |
| 58 | u32 dtuprd2; |
| 59 | u32 dtuprd3; |
| 60 | u32 dtuawdt; |
| 61 | u32 reserved4[3]; |
| 62 | u32 togcnt1u; |
| 63 | u32 tinit; |
| 64 | u32 trsth; |
| 65 | u32 togcnt100n; |
| 66 | u32 trefi; |
| 67 | u32 tmrd; |
| 68 | u32 trfc; |
| 69 | u32 trp; |
| 70 | u32 trtw; |
| 71 | u32 tal; |
| 72 | u32 tcl; |
| 73 | u32 tcwl; |
| 74 | u32 tras; |
| 75 | u32 trc; |
| 76 | u32 trcd; |
| 77 | u32 trrd; |
| 78 | u32 trtp; |
| 79 | u32 twr; |
| 80 | u32 twtr; |
| 81 | u32 texsr; |
| 82 | u32 txp; |
| 83 | u32 txpdll; |
| 84 | u32 tzqcs; |
| 85 | u32 tzqcsi; |
| 86 | u32 tdqs; |
| 87 | u32 tcksre; |
| 88 | u32 tcksrx; |
| 89 | u32 tcke; |
| 90 | u32 tmod; |
| 91 | u32 trstl; |
| 92 | u32 tzqcl; |
| 93 | u32 tmrr; |
| 94 | u32 tckesr; |
| 95 | u32 tdpd; |
| 96 | u32 reserved5[14]; |
| 97 | u32 ecccfg; |
| 98 | u32 ecctst; |
| 99 | u32 eccclr; |
| 100 | u32 ecclog; |
| 101 | u32 reserved6[28]; |
| 102 | u32 dtuwactl; |
| 103 | u32 dturactl; |
| 104 | u32 dtucfg; |
| 105 | u32 dtuectl; |
| 106 | u32 dtuwd0; |
| 107 | u32 dtuwd1; |
| 108 | u32 dtuwd2; |
| 109 | u32 dtuwd3; |
| 110 | u32 dtuwdm; |
| 111 | u32 dturd0; |
| 112 | u32 dturd1; |
| 113 | u32 dturd2; |
| 114 | u32 dturd3; |
| 115 | u32 dtulfsrwd; |
| 116 | u32 dtulfsrrd; |
| 117 | u32 dtueaf; |
| 118 | u32 dfitctrldelay; |
| 119 | u32 dfiodtcfg; |
| 120 | u32 dfiodtcfg1; |
| 121 | u32 dfiodtrankmap; |
| 122 | u32 dfitphywrdata; |
| 123 | u32 dfitphywrlat; |
| 124 | u32 reserved7[2]; |
| 125 | u32 dfitrddataen; |
| 126 | u32 dfitphyrdlat; |
| 127 | u32 reserved8[2]; |
| 128 | u32 dfitphyupdtype0; |
| 129 | u32 dfitphyupdtype1; |
| 130 | u32 dfitphyupdtype2; |
| 131 | u32 dfitphyupdtype3; |
| 132 | u32 dfitctrlupdmin; |
| 133 | u32 dfitctrlupdmax; |
| 134 | u32 dfitctrlupddly; |
| 135 | u32 reserved9; |
| 136 | u32 dfiupdcfg; |
| 137 | u32 dfitrefmski; |
| 138 | u32 dfitctrlupdi; |
| 139 | u32 reserved10[4]; |
| 140 | u32 dfitrcfg0; |
| 141 | u32 dfitrstat0; |
| 142 | u32 dfitrwrlvlen; |
| 143 | u32 dfitrrdlvlen; |
| 144 | u32 dfitrrdlvlgateen; |
| 145 | u32 dfiststat0; |
| 146 | u32 dfistcfg0; |
| 147 | u32 dfistcfg1; |
| 148 | u32 reserved11; |
| 149 | u32 dfitdramclken; |
| 150 | u32 dfitdramclkdis; |
| 151 | u32 dfistcfg2; |
| 152 | u32 dfistparclr; |
| 153 | u32 dfistparlog; |
| 154 | u32 reserved12[3]; |
| 155 | u32 dfilpcfg0; |
| 156 | u32 reserved13[3]; |
| 157 | u32 dfitrwrlvlresp0; |
| 158 | u32 dfitrwrlvlresp1; |
| 159 | u32 dfitrwrlvlresp2; |
| 160 | u32 dfitrrdlvlresp0; |
| 161 | u32 dfitrrdlvlresp1; |
| 162 | u32 dfitrrdlvlresp2; |
| 163 | u32 dfitrwrlvldelay0; |
| 164 | u32 dfitrwrlvldelay1; |
| 165 | u32 dfitrwrlvldelay2; |
| 166 | u32 dfitrrdlvldelay0; |
| 167 | u32 dfitrrdlvldelay1; |
| 168 | u32 dfitrrdlvldelay2; |
| 169 | u32 dfitrrdlvlgatedelay0; |
| 170 | u32 dfitrrdlvlgatedelay1; |
| 171 | u32 dfitrrdlvlgatedelay2; |
| 172 | u32 dfitrcmd; |
| 173 | u32 reserved14[46]; |
| 174 | u32 ipvr; |
| 175 | u32 iptr; |
| 176 | }; |
| 177 | check_member(rk3288_ddr_pctl_regs, iptr, 0x03fc); |
| 178 | |
| 179 | struct rk3288_ddr_publ_datx { |
| 180 | u32 dxgcr; |
| 181 | u32 dxgsr[2]; |
| 182 | u32 dxdllcr; |
| 183 | u32 dxdqtr; |
| 184 | u32 dxdqstr; |
| 185 | u32 reserved[10]; |
| 186 | }; |
| 187 | |
| 188 | struct rk3288_ddr_publ_regs { |
| 189 | u32 ridr; |
| 190 | u32 pir; |
| 191 | u32 pgcr; |
| 192 | u32 pgsr; |
| 193 | u32 dllgcr; |
| 194 | u32 acdllcr; |
| 195 | u32 ptr[3]; |
| 196 | u32 aciocr; |
| 197 | u32 dxccr; |
| 198 | u32 dsgcr; |
| 199 | u32 dcr; |
| 200 | u32 dtpr[3]; |
| 201 | u32 mr[4]; |
| 202 | u32 odtcr; |
| 203 | u32 dtar; |
| 204 | u32 dtdr[2]; |
| 205 | u32 reserved1[24]; |
| 206 | u32 dcuar; |
| 207 | u32 dcudr; |
| 208 | u32 dcurr; |
| 209 | u32 dculr; |
| 210 | u32 dcugcr; |
| 211 | u32 dcutpr; |
| 212 | u32 dcusr[2]; |
| 213 | u32 reserved2[8]; |
| 214 | u32 bist[17]; |
| 215 | u32 reserved3[15]; |
| 216 | u32 zq0cr[2]; |
| 217 | u32 zq0sr[2]; |
| 218 | u32 zq1cr[2]; |
| 219 | u32 zq1sr[2]; |
| 220 | u32 zq2cr[2]; |
| 221 | u32 zq2sr[2]; |
| 222 | u32 zq3cr[2]; |
| 223 | u32 zq3sr[2]; |
| 224 | struct rk3288_ddr_publ_datx datx8[4]; |
| 225 | }; |
| 226 | check_member(rk3288_ddr_publ_regs, datx8[3].dxdqstr, 0x0294); |
| 227 | |
| 228 | struct rk3288_msch_regs { |
| 229 | u32 coreid; |
| 230 | u32 revisionid; |
| 231 | u32 ddrconf; |
| 232 | u32 ddrtiming; |
| 233 | u32 ddrmode; |
| 234 | u32 readlatency; |
| 235 | u32 reserved1[8]; |
| 236 | u32 activate; |
| 237 | u32 devtodev; |
| 238 | }; |
| 239 | check_member(rk3288_msch_regs, devtodev, 0x003c); |
| 240 | |
| 241 | static struct rk3288_ddr_pctl_regs * const rk3288_ddr_pctl[2] = { |
| 242 | (void *)DDR_PCTL0_BASE, (void *)DDR_PCTL1_BASE}; |
| 243 | static struct rk3288_ddr_publ_regs * const rk3288_ddr_publ[2] = { |
| 244 | (void *)DDR_PUBL0_BASE, (void *)DDR_PUBL1_BASE}; |
| 245 | static struct rk3288_msch_regs * const rk3288_msch[2] = { |
| 246 | (void *)SERVICE_BUS_BASE, (void *)SERVICE_BUS_BASE + 0x80}; |
| 247 | |
| 248 | /* PCT_DFISTCFG0 */ |
| 249 | #define DFI_INIT_START (1 << 0) |
| 250 | |
| 251 | /* PCT_DFISTCFG1 */ |
| 252 | #define DFI_DRAM_CLK_SR_EN (1 << 0) |
| 253 | #define DFI_DRAM_CLK_DPD_EN (1 << 1) |
| 254 | |
| 255 | /* PCT_DFISTCFG2 */ |
| 256 | #define DFI_PARITY_INTR_EN (1 << 0) |
| 257 | #define DFI_PARITY_EN (1 << 1) |
| 258 | |
| 259 | /* PCT_DFILPCFG0 */ |
| 260 | #define TLP_RESP_TIME(n) (n << 16) |
| 261 | #define LP_SR_EN (1 << 8) |
| 262 | #define LP_PD_EN (1 << 0) |
| 263 | |
| 264 | /* PCT_DFITCTRLDELAY */ |
| 265 | #define TCTRL_DELAY_TIME(n) (n << 0) |
| 266 | |
| 267 | /* PCT_DFITPHYWRDATA */ |
| 268 | #define TPHY_WRDATA_TIME(n) (n << 0) |
| 269 | |
| 270 | /* PCT_DFITPHYRDLAT */ |
| 271 | #define TPHY_RDLAT_TIME(n) (n << 0) |
| 272 | |
| 273 | /* PCT_DFITDRAMCLKDIS */ |
| 274 | #define TDRAM_CLK_DIS_TIME(n) (n << 0) |
| 275 | |
| 276 | /* PCT_DFITDRAMCLKEN */ |
| 277 | #define TDRAM_CLK_EN_TIME(n) (n << 0) |
| 278 | |
| 279 | /* PCTL_DFIODTCFG */ |
| 280 | #define RANK0_ODT_WRITE_SEL (1 << 3) |
| 281 | #define RANK1_ODT_WRITE_SEL (1 << 11) |
| 282 | |
| 283 | /* PCTL_DFIODTCFG1 */ |
| 284 | #define ODT_LEN_BL8_W(n) (n<<16) |
| 285 | |
| 286 | /* PUBL_ACDLLCR */ |
| 287 | #define ACDLLCR_DLLDIS (1 << 31) |
| 288 | #define ACDLLCR_DLLSRST (1 << 30) |
| 289 | |
| 290 | /* PUBL_DXDLLCR */ |
| 291 | #define DXDLLCR_DLLDIS (1 << 31) |
| 292 | #define DXDLLCR_DLLSRST (1 << 30) |
| 293 | |
| 294 | /* PUBL_DLLGCR */ |
| 295 | #define DLLGCR_SBIAS (1 << 30) |
| 296 | |
| 297 | /* PUBL_DXGCR */ |
| 298 | #define DQSRTT (1 << 9) |
| 299 | #define DQRTT (1 << 10) |
| 300 | |
| 301 | /* PIR */ |
| 302 | #define PIR_INIT (1 << 0) |
| 303 | #define PIR_DLLSRST (1 << 1) |
| 304 | #define PIR_DLLLOCK (1 << 2) |
| 305 | #define PIR_ZCAL (1 << 3) |
| 306 | #define PIR_ITMSRST (1 << 4) |
| 307 | #define PIR_DRAMRST (1 << 5) |
| 308 | #define PIR_DRAMINIT (1 << 6) |
| 309 | #define PIR_QSTRN (1 << 7) |
| 310 | #define PIR_RVTRN (1 << 8) |
| 311 | #define PIR_ICPC (1 << 16) |
| 312 | #define PIR_DLLBYP (1 << 17) |
| 313 | #define PIR_CTLDINIT (1 << 18) |
| 314 | #define PIR_CLRSR (1 << 28) |
| 315 | #define PIR_LOCKBYP (1 << 29) |
| 316 | #define PIR_ZCALBYP (1 << 30) |
| 317 | #define PIR_INITBYP (1u << 31) |
| 318 | |
| 319 | /* PGCR */ |
| 320 | #define PGCR_DFTLMT(n) ((n) << 3) |
| 321 | #define PGCR_DFTCMP(n) ((n) << 2) |
| 322 | #define PGCR_DQSCFG(n) ((n) << 1) |
| 323 | #define PGCR_ITMDMD(n) ((n) << 0) |
| 324 | |
| 325 | /* PGSR */ |
| 326 | #define PGSR_IDONE (1 << 0) |
| 327 | #define PGSR_DLDONE (1 << 1) |
| 328 | #define PGSR_ZCDONE (1 << 2) |
| 329 | #define PGSR_DIDONE (1 << 3) |
| 330 | #define PGSR_DTDONE (1 << 4) |
| 331 | #define PGSR_DTERR (1 << 5) |
| 332 | #define PGSR_DTIERR (1 << 6) |
| 333 | #define PGSR_DFTERR (1 << 7) |
| 334 | #define PGSR_RVERR (1 << 8) |
| 335 | #define PGSR_RVEIRR (1 << 9) |
| 336 | |
| 337 | /* PTR0 */ |
| 338 | #define PRT_ITMSRST(n) ((n) << 18) |
| 339 | #define PRT_DLLLOCK(n) ((n) << 6) |
| 340 | #define PRT_DLLSRST(n) ((n) << 0) |
| 341 | |
| 342 | /* PTR1 */ |
| 343 | #define PRT_DINIT1(n) ((n) << 19) |
| 344 | #define PRT_DINIT0(n) ((n) << 0) |
| 345 | |
| 346 | /* PTR2 */ |
| 347 | #define PRT_DINIT3(n) ((n) << 17) |
| 348 | #define PRT_DINIT2(n) ((n) << 0) |
| 349 | |
| 350 | /* DCR */ |
| 351 | #define DDRMD_LPDDR 0 |
| 352 | #define DDRMD_DDR 1 |
| 353 | #define DDRMD_DDR2 2 |
| 354 | #define DDRMD_DDR3 3 |
| 355 | #define DDRMD_LPDDR2_LPDDR3 4 |
| 356 | #define DDRMD_MSK (7 << 0) |
| 357 | #define DDRMD_CFG(n) ((n) << 0) |
| 358 | #define PDQ_MSK (7 << 4) |
| 359 | #define PDQ_CFG(n) ((n) << 4) |
| 360 | |
| 361 | /* DXCCR */ |
| 362 | #define DQSNRES_MSK (0x0f << 8) |
| 363 | #define DQSNRES_CFG(n) ((n) << 8) |
| 364 | #define DQSRES_MSK (0x0f << 4) |
| 365 | #define DQSRES_CFG(n) ((n) << 4) |
| 366 | |
| 367 | /* DTPR */ |
| 368 | #define TDQSCKMAX_VAL(n) (((n) >> 27) & 7) |
| 369 | #define TDQSCK_VAL(n) (((n) >> 24) & 7) |
| 370 | |
| 371 | /* DSGCR */ |
| 372 | #define DQSGX_MSK (0x07 << 5) |
| 373 | #define DQSGX_CFG(n) ((n) << 5) |
| 374 | #define DQSGE_MSK (0x07 << 8) |
| 375 | #define DQSGE_CFG(n) ((n) << 8) |
| 376 | |
| 377 | /* SCTL */ |
| 378 | #define INIT_STATE (0) |
| 379 | #define CFG_STATE (1) |
| 380 | #define GO_STATE (2) |
| 381 | #define SLEEP_STATE (3) |
| 382 | #define WAKEUP_STATE (4) |
| 383 | |
| 384 | /* STAT */ |
| 385 | #define LP_TRIG_VAL(n) (((n) >> 4) & 7) |
| 386 | #define PCTL_STAT_MSK (7) |
| 387 | #define INIT_MEM (0) |
| 388 | #define CONFIG (1) |
| 389 | #define CONFIG_REQ (2) |
| 390 | #define ACCESS (3) |
| 391 | #define ACCESS_REQ (4) |
| 392 | #define LOW_POWER (5) |
| 393 | #define LOW_POWER_ENTRY_REQ (6) |
| 394 | #define LOW_POWER_EXIT_REQ (7) |
| 395 | |
| 396 | /* ZQCR*/ |
| 397 | #define PD_OUTPUT(n) ((n) << 0) |
| 398 | #define PU_OUTPUT(n) ((n) << 5) |
| 399 | #define PD_ONDIE(n) ((n) << 10) |
| 400 | #define PU_ONDIE(n) ((n) << 15) |
| 401 | #define ZDEN(n) ((n) << 28) |
| 402 | |
| 403 | /* DDLGCR */ |
| 404 | #define SBIAS_BYPASS (1 << 23) |
| 405 | |
| 406 | /* MCFG */ |
| 407 | #define MDDR_LPDDR2_CLK_STOP_IDLE(n) ((n) << 24) |
| 408 | #define PD_IDLE(n) ((n) << 8) |
| 409 | #define MDDR_EN (2 << 22) |
| 410 | #define LPDDR2_EN (3 << 22) |
| 411 | #define DDR2_EN (0 << 5) |
| 412 | #define DDR3_EN (1 << 5) |
| 413 | #define LPDDR2_S2 (0 << 6) |
| 414 | #define LPDDR2_S4 (1 << 6) |
| 415 | #define MDDR_LPDDR2_BL_2 (0 << 20) |
| 416 | #define MDDR_LPDDR2_BL_4 (1 << 20) |
| 417 | #define MDDR_LPDDR2_BL_8 (2 << 20) |
| 418 | #define MDDR_LPDDR2_BL_16 (3 << 20) |
| 419 | #define DDR2_DDR3_BL_4 (0) |
| 420 | #define DDR2_DDR3_BL_8 (1) |
| 421 | #define TFAW_CFG(n) (((n)-4) << 18) |
| 422 | #define PD_EXIT_SLOW (0 << 17) |
| 423 | #define PD_EXIT_FAST (1 << 17) |
| 424 | #define PD_TYPE(n) ((n) << 16) |
| 425 | #define BURSTLENGTH_CFG(n) (((n) >> 1) << 20) |
| 426 | |
| 427 | /* POWCTL */ |
| 428 | #define POWER_UP_START (1 << 0) |
| 429 | |
| 430 | /* POWSTAT */ |
| 431 | #define POWER_UP_DONE (1 << 0) |
| 432 | |
| 433 | /* MCMD */ |
| 434 | #define DESELECT_CMD (0) |
| 435 | #define PREA_CMD (1) |
| 436 | #define REF_CMD (2) |
| 437 | #define MRS_CMD (3) |
| 438 | #define ZQCS_CMD (4) |
| 439 | #define ZQCL_CMD (5) |
| 440 | #define RSTL_CMD (6) |
| 441 | #define MRR_CMD (8) |
| 442 | #define DPDE_CMD (9) |
| 443 | |
| 444 | #define LPDDR2_MA(n) (((n) & 0xff) << 4) |
| 445 | |
| 446 | #define START_CMD (1u << 31) |
| 447 | |
| 448 | /* DEVTODEV */ |
| 449 | #define BUSWRTORD(n) ((n) << 4) |
| 450 | #define BUSRDTOWR(n) ((n) << 2) |
| 451 | #define BUSRDTORD(n) ((n) << 0) |
| 452 | |
| 453 | /* GRF_SOC_CON0 */ |
| 454 | #define MSCH_MAINDDR3(ch, n) (((n) << (3 + (ch))) \ |
| 455 | | ((1 << (3 + (ch))) << 16)) |
| 456 | |
| 457 | /* GRF_SOC_CON2 */ |
| 458 | #define PUBL_LPDDR3_EN(ch, n) RK_CLRSETBITS(1 << (10 + (3 * (ch))), \ |
| 459 | (n) << (10 + (3 * (ch)))) |
| 460 | #define PCTL_LPDDR3_ODT_EN(ch, n) RK_CLRSETBITS(1 << (9 + (3 * (ch))), \ |
| 461 | (n) << (9 + (3 * (ch)))) |
| 462 | #define PCTL_BST_DISABLE(ch, n) RK_CLRSETBITS(1 << (8 + (3 * (ch))), \ |
| 463 | (n) << (8 + (3 * (ch)))) |
| 464 | |
| 465 | /* mr1 for ddr3 */ |
| 466 | #define DDR3_DLL_ENABLE (0) |
| 467 | #define DDR3_DLL_DISABLE (1) |
| 468 | |
| 469 | /* |
| 470 | * sys_reg bitfield struct |
| 471 | * [31] row_3_4_ch1 |
| 472 | * [30] row_3_4_ch0 |
| 473 | * [29:28] chinfo |
| 474 | * [27] rank_ch1 |
| 475 | * [26:25] col_ch1 |
| 476 | * [24] bk_ch1 |
| 477 | * [23:22] cs0_row_ch1 |
| 478 | * [21:20] cs1_row_ch1 |
| 479 | * [19:18] bw_ch1 |
| 480 | * [17:16] dbw_ch1; |
| 481 | * [15:13] ddrtype |
| 482 | * [12] channelnum |
| 483 | * [11] rank_ch0 |
| 484 | * [10:9] col_ch0 |
| 485 | * [8] bk_ch0 |
| 486 | * [7:6] cs0_row_ch0 |
| 487 | * [5:4] cs1_row_ch0 |
| 488 | * [3:2] bw_ch0 |
| 489 | * [1:0] dbw_ch0 |
| 490 | */ |
| 491 | #define SYS_REG_DDRTYPE(n) ((n) << 13) |
| 492 | #define SYS_REG_NUM_CH(n) (((n) - 1) << 12) |
| 493 | #define SYS_REG_ROW_3_4(n, ch) ((n) << (30 + (ch))) |
| 494 | #define SYS_REG_CHINFO(ch) (1 << (28 + (ch))) |
| 495 | #define SYS_REG_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16))) |
| 496 | #define SYS_REG_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) |
| 497 | #define SYS_REG_BK(n, ch) (((n) == 3 ? 0 : 1) \ |
| 498 | << (8 + ((ch) * 16))) |
| 499 | #define SYS_REG_CS0_ROW(n, ch) (((n) - 13) << (6 + ((ch) * 16))) |
| 500 | #define SYS_REG_CS1_ROW(n, ch) (((n) - 13) << (4 + ((ch) * 16))) |
| 501 | #define SYS_REG_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) |
| 502 | #define SYS_REG_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16))) |
| 503 | |
| 504 | static void copy_to_reg(u32 *dest, const u32 *src, u32 n) |
| 505 | { |
| 506 | int i; |
| 507 | for (i = 0; i < n / sizeof(u32); i++) { |
| 508 | writel(*src, dest); |
| 509 | src++; |
| 510 | dest++; |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, |
| 515 | u32 channel) |
| 516 | { |
| 517 | int i; |
| 518 | rkclk_ddr_reset(channel, 1, 1); |
| 519 | udelay(1); |
| 520 | clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); |
| 521 | for (i = 0; i < 4; i++) |
| 522 | clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); |
| 523 | |
| 524 | udelay(10); |
| 525 | setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); |
| 526 | for (i = 0; i < 4; i++) |
| 527 | setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); |
| 528 | |
| 529 | udelay(10); |
| 530 | rkclk_ddr_reset(channel, 1, 0); |
| 531 | udelay(10); |
| 532 | rkclk_ddr_reset(channel, 0, 0); |
| 533 | udelay(1); |
| 534 | } |
| 535 | |
| 536 | static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, |
| 537 | u32 freq) |
| 538 | { |
| 539 | int i; |
| 540 | if (freq <= 250000000) { |
| 541 | if (freq <= 150000000) |
| 542 | clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); |
| 543 | else |
| 544 | setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); |
| 545 | setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); |
| 546 | for (i = 0; i < 4; i++) |
| 547 | setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, |
| 548 | DXDLLCR_DLLDIS); |
| 549 | |
| 550 | setbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); |
| 551 | } else { |
| 552 | clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); |
| 553 | clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); |
| 554 | for (i = 0; i < 4; i++) |
| 555 | clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, |
| 556 | DXDLLCR_DLLDIS); |
| 557 | |
| 558 | clrbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | static void dfi_cfg(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 dramtype) |
| 563 | { |
| 564 | writel(DFI_INIT_START, &ddr_pctl_regs->dfistcfg0); |
| 565 | writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, |
| 566 | &ddr_pctl_regs->dfistcfg1); |
| 567 | writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &ddr_pctl_regs->dfistcfg2); |
| 568 | writel(TLP_RESP_TIME(7) | LP_SR_EN | LP_PD_EN, |
| 569 | &ddr_pctl_regs->dfilpcfg0); |
| 570 | |
| 571 | writel(TCTRL_DELAY_TIME(2), &ddr_pctl_regs->dfitctrldelay); |
| 572 | writel(TPHY_WRDATA_TIME(1), &ddr_pctl_regs->dfitphywrdata); |
| 573 | writel(TPHY_RDLAT_TIME(0xf), &ddr_pctl_regs->dfitphyrdlat); |
| 574 | writel(TDRAM_CLK_DIS_TIME(2), &ddr_pctl_regs->dfitdramclkdis); |
| 575 | writel(TDRAM_CLK_EN_TIME(2), &ddr_pctl_regs->dfitdramclken); |
| 576 | writel(0x1, &ddr_pctl_regs->dfitphyupdtype0); |
| 577 | |
| 578 | /* cs0 and cs1 write odt enable */ |
| 579 | writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), |
| 580 | &ddr_pctl_regs->dfiodtcfg); |
| 581 | /* odt write length */ |
| 582 | writel(ODT_LEN_BL8_W(7), &ddr_pctl_regs->dfiodtcfg1); |
| 583 | /* phyupd and ctrlupd disabled */ |
| 584 | writel(0, &ddr_pctl_regs->dfiupdcfg); |
| 585 | } |
| 586 | |
| 587 | static void pctl_cfg(u32 channel, |
| 588 | const struct rk3288_sdram_params *sdram_params) |
| 589 | { |
| 590 | unsigned int burstlen; |
| 591 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel]; |
| 592 | burstlen = (sdram_params->noc_timing >> 18) & 0x7; |
| 593 | copy_to_reg(&ddr_pctl_regs->togcnt1u, |
| 594 | &(sdram_params->pctl_timing.togcnt1u), |
| 595 | sizeof(sdram_params->pctl_timing)); |
| 596 | switch (sdram_params->dramtype) { |
| 597 | case LPDDR3: |
| 598 | writel(sdram_params->pctl_timing.tcl - 1, |
| 599 | &ddr_pctl_regs->dfitrddataen); |
| 600 | writel(sdram_params->pctl_timing.tcwl, |
| 601 | &ddr_pctl_regs->dfitphywrlat); |
| 602 | writel(LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN |
| 603 | | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST |
| 604 | | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg); |
| 605 | writel(MSCH_MAINDDR3(channel, 0), &rk3288_grf->soc_con0); |
| 606 | |
| 607 | writel(PUBL_LPDDR3_EN(channel, 1) |
| 608 | | PCTL_BST_DISABLE(channel, 1) |
| 609 | | PCTL_LPDDR3_ODT_EN(channel, 1), |
| 610 | &rk3288_grf->soc_con2); |
| 611 | |
| 612 | break; |
| 613 | case DDR3: |
| 614 | if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) |
| 615 | writel(sdram_params->pctl_timing.tcl - 3, |
| 616 | &ddr_pctl_regs->dfitrddataen); |
| 617 | else |
| 618 | writel(sdram_params->pctl_timing.tcl - 2, |
| 619 | &ddr_pctl_regs->dfitrddataen); |
| 620 | writel(sdram_params->pctl_timing.tcwl - 1, |
| 621 | &ddr_pctl_regs->dfitphywrlat); |
| 622 | writel(MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN |
| 623 | | DDR2_DDR3_BL_8 | TFAW_CFG(5) | PD_EXIT_SLOW |
| 624 | | PD_TYPE(1) | PD_IDLE(0), &ddr_pctl_regs->mcfg); |
| 625 | writel(MSCH_MAINDDR3(channel, 1), &rk3288_grf->soc_con0); |
| 626 | |
| 627 | writel(PUBL_LPDDR3_EN(channel, 0) |
| 628 | | PCTL_BST_DISABLE(channel, 0) |
| 629 | | PCTL_LPDDR3_ODT_EN(channel, 0), |
| 630 | &rk3288_grf->soc_con2); |
| 631 | |
| 632 | break; |
| 633 | } |
| 634 | |
| 635 | setbits_le32(&ddr_pctl_regs->scfg, 1); |
| 636 | } |
| 637 | |
| 638 | static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) |
| 639 | { |
| 640 | u32 i; |
| 641 | struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel]; |
| 642 | struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; |
| 643 | |
| 644 | /* DDR PHY Timing */ |
| 645 | copy_to_reg(&ddr_publ_regs->dtpr[0], |
| 646 | &(sdram_params->phy_timing.dtpr0), |
| 647 | sizeof(sdram_params->phy_timing)); |
| 648 | writel(sdram_params->noc_timing, &msch_regs->ddrtiming); |
| 649 | writel(0x3f, &msch_regs->readlatency); |
| 650 | writel(sdram_params->noc_activate, &msch_regs->activate); |
| 651 | writel(BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1), |
| 652 | &msch_regs->devtodev); |
| 653 | writel(PRT_ITMSRST(8) | PRT_DLLLOCK(2750) | PRT_DLLSRST(27), |
| 654 | &ddr_publ_regs->ptr[0]); |
| 655 | /* tDINIT1=400ns (533MHz), tDINIT0=500us (533MHz) */ |
| 656 | writel(PRT_DINIT1(213) | PRT_DINIT0(266525), &ddr_publ_regs->ptr[1]); |
| 657 | /* tDINIT3=1us (533MHz), tDINIT2=200us (533MHz) */ |
| 658 | writel(PRT_DINIT3(534) | PRT_DINIT2(106610), &ddr_publ_regs->ptr[2]); |
| 659 | |
| 660 | switch (sdram_params->dramtype) { |
| 661 | case LPDDR3: |
| 662 | clrsetbits_le32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) |
| 663 | | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0)); |
| 664 | /* DDRMODE select LPDDR3 */ |
| 665 | clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, |
| 666 | DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); |
| 667 | clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, |
| 668 | DQSRES_CFG(4) | DQSNRES_CFG(0xc)); |
| 669 | i = TDQSCKMAX_VAL(readl(&ddr_publ_regs->dtpr[1])) |
| 670 | - TDQSCK_VAL(readl(&ddr_publ_regs->dtpr[1])); |
| 671 | clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, |
| 672 | DQSGE_CFG(i) | DQSGX_CFG(i)); |
| 673 | break; |
| 674 | case DDR3: |
| 675 | clrbits_le32(&ddr_publ_regs->pgcr, 0x1f); |
| 676 | clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, |
| 677 | DDRMD_CFG(DDRMD_DDR3)); |
| 678 | break; |
| 679 | } |
| 680 | if (sdram_params->odt) { |
| 681 | /*dynamic RTT enable */ |
| 682 | for (i = 0; i < 4; i++) |
| 683 | setbits_le32(&ddr_publ_regs->datx8[i].dxgcr, |
| 684 | DQSRTT | DQRTT); |
| 685 | } else { |
| 686 | /*dynamic RTT disable */ |
| 687 | for (i = 0; i < 4; i++) |
| 688 | clrbits_le32(&ddr_publ_regs->datx8[i].dxgcr, |
| 689 | DQSRTT | DQRTT); |
| 690 | |
| 691 | } |
| 692 | } |
| 693 | |
| 694 | static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) |
| 695 | { |
| 696 | setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST |
| 697 | | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); |
| 698 | udelay(1); |
| 699 | while ((readl(&ddr_publ_regs->pgsr) & |
| 700 | (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != |
| 701 | (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) |
| 702 | ; |
| 703 | } |
| 704 | |
| 705 | static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, |
| 706 | u32 cmd, u32 arg) |
| 707 | { |
| 708 | writel((START_CMD | (rank << 20) | arg | cmd), &ddr_pctl_regs->mcmd); |
| 709 | udelay(1); |
| 710 | while (readl(&ddr_pctl_regs->mcmd) & START_CMD) |
| 711 | ; |
| 712 | } |
| 713 | |
| 714 | static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, |
| 715 | u32 dramtype) |
| 716 | { |
| 717 | setbits_le32(&ddr_publ_regs->pir, |
| 718 | (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP |
| 719 | | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC |
| 720 | | (dramtype == DDR3 ? PIR_DRAMRST : 0))); |
| 721 | udelay(1); |
| 722 | while ((readl(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) |
| 723 | != (PGSR_IDONE | PGSR_DLDONE)) |
| 724 | ; |
| 725 | } |
| 726 | |
| 727 | static void move_to_config_state(struct rk3288_ddr_publ_regs *ddr_publ_regs, |
| 728 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs) |
| 729 | { |
| 730 | unsigned int state; |
| 731 | |
| 732 | while (1) { |
| 733 | state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; |
| 734 | |
| 735 | switch (state) { |
| 736 | case LOW_POWER: |
| 737 | writel(WAKEUP_STATE, &ddr_pctl_regs->sctl); |
| 738 | while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) |
| 739 | != ACCESS) |
| 740 | ; |
| 741 | /* wait DLL lock */ |
| 742 | while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE) |
| 743 | != PGSR_DLDONE) |
| 744 | ; |
| 745 | /* if at low power state,need wakeup first, |
| 746 | * and then enter the config |
| 747 | * so here no break. |
| 748 | */ |
| 749 | case ACCESS: |
| 750 | case INIT_MEM: |
| 751 | writel(CFG_STATE, &ddr_pctl_regs->sctl); |
| 752 | while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) |
| 753 | != CONFIG) |
| 754 | ; |
| 755 | break; |
| 756 | case CONFIG: |
| 757 | return; |
| 758 | default: |
| 759 | break; |
| 760 | } |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | static void set_bandwidth_ratio(u32 channel, u32 n) |
| 765 | { |
| 766 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel]; |
| 767 | struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel]; |
| 768 | struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; |
| 769 | |
| 770 | if (n == 1) { |
| 771 | setbits_le32(&ddr_pctl_regs->ppcfg, 1); |
| 772 | writel(RK_SETBITS(1 << (8 + channel)), |
| 773 | &rk3288_grf->soc_con0); |
| 774 | setbits_le32(&msch_regs->ddrtiming, 1 << 31); |
| 775 | /* Data Byte disable*/ |
| 776 | clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); |
| 777 | clrbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); |
| 778 | /*disable DLL */ |
| 779 | setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, |
| 780 | DXDLLCR_DLLDIS); |
| 781 | setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, |
| 782 | DXDLLCR_DLLDIS); |
| 783 | } else { |
| 784 | clrbits_le32(&ddr_pctl_regs->ppcfg, 1); |
| 785 | writel(RK_CLRBITS(1 << (8 + channel)), |
| 786 | &rk3288_grf->soc_con0); |
| 787 | clrbits_le32(&msch_regs->ddrtiming, 1 << 31); |
| 788 | /* Data Byte enable*/ |
| 789 | setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); |
| 790 | setbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); |
| 791 | |
| 792 | /*enable DLL */ |
| 793 | clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, |
| 794 | DXDLLCR_DLLDIS); |
| 795 | clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, |
| 796 | DXDLLCR_DLLDIS); |
| 797 | /* reset DLL */ |
| 798 | clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, |
| 799 | DXDLLCR_DLLSRST); |
| 800 | clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, |
| 801 | DXDLLCR_DLLSRST); |
| 802 | udelay(10); |
| 803 | setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, |
| 804 | DXDLLCR_DLLSRST); |
| 805 | setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, |
| 806 | DXDLLCR_DLLSRST); |
| 807 | } |
| 808 | setbits_le32(&ddr_pctl_regs->dfistcfg0, 1 << 2); |
| 809 | |
| 810 | } |
| 811 | |
| 812 | static int data_training(u32 channel, |
| 813 | const struct rk3288_sdram_params *sdram_params) |
| 814 | { |
| 815 | unsigned int j; |
| 816 | int ret = 0; |
| 817 | u32 rank; |
| 818 | int i; |
| 819 | u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; |
| 820 | struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel]; |
| 821 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[channel]; |
| 822 | |
| 823 | /* disable auto refresh */ |
| 824 | writel(0, &ddr_pctl_regs->trefi); |
| 825 | |
| 826 | if (sdram_params->dramtype != LPDDR3) |
| 827 | setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); |
| 828 | rank = sdram_params->ch[channel].rank | 1; |
| 829 | for (j = 0; j < ARRAY_SIZE(step); j++) { |
| 830 | /* |
| 831 | * trigger QSTRN and RVTRN |
| 832 | * clear DTDONE status |
| 833 | */ |
| 834 | setbits_le32(&ddr_publ_regs->pir, PIR_CLRSR); |
| 835 | |
| 836 | /* trigger DTT */ |
| 837 | setbits_le32(&ddr_publ_regs->pir, |
| 838 | PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | |
| 839 | PIR_CLRSR); |
| 840 | udelay(1); |
| 841 | /* wait echo byte DTDONE */ |
| 842 | while ((readl(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) |
| 843 | != rank) |
| 844 | ; |
| 845 | while ((readl(&ddr_publ_regs->datx8[1].dxgsr[0]) & rank) |
| 846 | != rank) |
| 847 | ; |
| 848 | if (!(readl(&ddr_pctl_regs->ppcfg) & 1)) { |
| 849 | while ((readl(&ddr_publ_regs->datx8[2].dxgsr[0]) |
| 850 | & rank) != rank) |
| 851 | ; |
| 852 | while ((readl(&ddr_publ_regs->datx8[3].dxgsr[0]) |
| 853 | & rank) != rank) |
| 854 | ; |
| 855 | } |
| 856 | if (readl(&ddr_publ_regs->pgsr) & |
| 857 | (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { |
| 858 | ret = -1; |
| 859 | break; |
| 860 | } |
| 861 | } |
| 862 | /* send some auto refresh to complement the lost while DTT */ |
| 863 | for (i = 0; i < (rank > 1 ? 4 : 2); i++) |
| 864 | send_command(ddr_pctl_regs, rank, REF_CMD, 0); |
| 865 | |
| 866 | if (sdram_params->dramtype != LPDDR3) |
| 867 | clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); |
| 868 | |
| 869 | /* resume auto refresh */ |
| 870 | writel(sdram_params->pctl_timing.trefi, &ddr_pctl_regs->trefi); |
| 871 | |
| 872 | return ret; |
| 873 | } |
| 874 | |
| 875 | static void move_to_access_state(u32 chnum) |
| 876 | { |
| 877 | struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[chnum]; |
| 878 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs = rk3288_ddr_pctl[chnum]; |
| 879 | |
| 880 | unsigned int state; |
| 881 | |
| 882 | while (1) { |
| 883 | state = readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK; |
| 884 | |
| 885 | switch (state) { |
| 886 | case LOW_POWER: |
| 887 | if (LP_TRIG_VAL(readl(&ddr_pctl_regs->stat)) == 1) |
| 888 | return; |
| 889 | |
| 890 | writel(WAKEUP_STATE, &ddr_pctl_regs->sctl); |
| 891 | while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) |
| 892 | != ACCESS) |
| 893 | ; |
| 894 | /* wait DLL lock */ |
| 895 | while ((readl(&ddr_publ_regs->pgsr) & PGSR_DLDONE) |
| 896 | != PGSR_DLDONE) |
| 897 | ; |
| 898 | break; |
| 899 | case INIT_MEM: |
| 900 | writel(CFG_STATE, &ddr_pctl_regs->sctl); |
| 901 | while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) |
| 902 | != CONFIG) |
| 903 | ; |
| 904 | case CONFIG: |
| 905 | writel(GO_STATE, &ddr_pctl_regs->sctl); |
| 906 | while ((readl(&ddr_pctl_regs->stat) & PCTL_STAT_MSK) |
| 907 | == CONFIG) |
| 908 | ; |
| 909 | break; |
| 910 | case ACCESS: |
| 911 | return; |
| 912 | default: |
| 913 | break; |
| 914 | } |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | static void dram_cfg_rbc(u32 chnum, |
| 919 | const struct rk3288_sdram_params *sdram_params) |
| 920 | { |
| 921 | struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[chnum]; |
| 922 | struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum]; |
| 923 | |
| 924 | if (sdram_params->ch[chnum].bk == 3) |
| 925 | clrsetbits_le32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); |
| 926 | else |
| 927 | clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); |
| 928 | |
| 929 | writel(sdram_params->ddrconfig, &msch_regs->ddrconf); |
| 930 | } |
| 931 | |
| 932 | static void dram_all_config(const struct rk3288_sdram_params *sdram_params) |
| 933 | { |
| 934 | u32 sys_reg = 0; |
| 935 | unsigned int channel; |
| 936 | |
| 937 | sys_reg |= SYS_REG_DDRTYPE(sdram_params->dramtype); |
| 938 | sys_reg |= SYS_REG_NUM_CH(sdram_params->num_channels); |
| 939 | for (channel = 0; channel < sdram_params->num_channels; channel++) { |
| 940 | const struct rk3288_sdram_channel *info = |
| 941 | &(sdram_params->ch[channel]); |
| 942 | sys_reg |= SYS_REG_ROW_3_4(info->row_3_4, channel); |
| 943 | sys_reg |= SYS_REG_CHINFO(channel); |
| 944 | sys_reg |= SYS_REG_RANK(info->rank, channel); |
| 945 | sys_reg |= SYS_REG_COL(info->col, channel); |
| 946 | sys_reg |= SYS_REG_BK(info->bk, channel); |
| 947 | sys_reg |= SYS_REG_CS0_ROW(info->cs0_row, channel); |
| 948 | sys_reg |= SYS_REG_CS1_ROW(info->cs1_row, channel); |
| 949 | sys_reg |= SYS_REG_BW(info->bw, channel); |
| 950 | sys_reg |= SYS_REG_DBW(info->dbw, channel); |
| 951 | |
| 952 | dram_cfg_rbc(channel, sdram_params); |
| 953 | } |
| 954 | writel(sys_reg, &rk3288_pmu->sys_reg[2]); |
| 955 | writel(RK_CLRSETBITS(0x1F, sdram_params->stride), |
| 956 | &rk3288_sgrf->soc_con2); |
| 957 | } |
| 958 | |
| 959 | void sdram_init(const struct rk3288_sdram_params *sdram_params) |
| 960 | { |
| 961 | int channel; |
| 962 | int zqcr; |
| 963 | printk(BIOS_INFO, "Starting SDRAM initialization...\n"); |
| 964 | |
| 965 | if (sdram_params->ddr_freq > 533000000) |
| 966 | die("SDRAM frequency is to high!"); |
| 967 | |
| 968 | rkclk_configure_ddr(sdram_params->ddr_freq); |
| 969 | |
| 970 | for (channel = 0; channel < sdram_params->num_channels; channel++) { |
| 971 | struct rk3288_ddr_pctl_regs *ddr_pctl_regs = |
| 972 | rk3288_ddr_pctl[channel]; |
| 973 | struct rk3288_ddr_publ_regs *ddr_publ_regs = |
| 974 | rk3288_ddr_publ[channel]; |
| 975 | |
| 976 | phy_pctrl_reset(ddr_publ_regs, channel); |
| 977 | phy_dll_bypass_set(ddr_publ_regs, sdram_params->ddr_freq); |
| 978 | |
| 979 | dfi_cfg(ddr_pctl_regs, sdram_params->dramtype); |
| 980 | |
| 981 | pctl_cfg(channel, sdram_params); |
| 982 | |
| 983 | phy_cfg(channel, sdram_params); |
| 984 | |
| 985 | phy_init(ddr_publ_regs); |
| 986 | |
| 987 | writel(POWER_UP_START, &ddr_pctl_regs->powctl); |
| 988 | while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE)) |
| 989 | ; |
| 990 | send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0); |
| 991 | udelay(1); |
| 992 | send_command(ddr_pctl_regs, 3, PREA_CMD, 0); |
| 993 | |
| 994 | memory_init(ddr_publ_regs, sdram_params->dramtype); |
| 995 | move_to_config_state(ddr_publ_regs, ddr_pctl_regs); |
| 996 | set_bandwidth_ratio(channel, sdram_params->ch[channel].bw); |
| 997 | /* |
| 998 | * set cs |
| 999 | * CS0, n=1 |
| 1000 | * CS1, n=2 |
| 1001 | * CS0 & CS1, n = 3 |
| 1002 | */ |
| 1003 | clrsetbits_le32(&ddr_publ_regs->pgcr, 0xF << 18, |
| 1004 | (sdram_params->ch[channel].rank | 1) << 18); |
| 1005 | /* DS=40ohm,ODT=155ohm */ |
| 1006 | zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) |
| 1007 | | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); |
| 1008 | writel(zqcr, &ddr_publ_regs->zq1cr[0]); |
| 1009 | writel(zqcr, &ddr_publ_regs->zq0cr[0]); |
| 1010 | |
| 1011 | if (sdram_params->dramtype == LPDDR3) { |
| 1012 | /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ |
| 1013 | udelay(10); |
| 1014 | if (channel == 0) { |
| 1015 | writel(0, &ddr_pctl_regs->mrrcfg0); |
| 1016 | send_command(ddr_pctl_regs, 1, MRR_CMD, |
| 1017 | LPDDR2_MA(0x8)); |
| 1018 | /* S8 */ |
| 1019 | if ((readl(&ddr_pctl_regs->mrrstat0) & 0x3) |
| 1020 | != 3) |
| 1021 | die("SDRAM initialization failed!"); |
| 1022 | } |
| 1023 | } |
| 1024 | |
| 1025 | if (-1 == data_training(channel, sdram_params)) { |
| 1026 | if (sdram_params->dramtype == LPDDR3) { |
| 1027 | rkclk_ddr_phy_ctl_reset(channel, 1); |
| 1028 | udelay(10); |
| 1029 | rkclk_ddr_phy_ctl_reset(channel, 0); |
| 1030 | udelay(10); |
| 1031 | } |
| 1032 | die("SDRAM initialization failed!"); |
| 1033 | } |
| 1034 | |
| 1035 | if (sdram_params->dramtype == LPDDR3) { |
| 1036 | u32 i; |
| 1037 | writel(0, &ddr_pctl_regs->mrrcfg0); |
| 1038 | for (i = 0; i < 17; i++) |
| 1039 | send_command(ddr_pctl_regs, 1, MRR_CMD, |
| 1040 | LPDDR2_MA(i)); |
| 1041 | } |
| 1042 | move_to_access_state(channel); |
| 1043 | } |
| 1044 | dram_all_config(sdram_params); |
| 1045 | printk(BIOS_INFO, "Finish SDRAM initialization...\n"); |
| 1046 | } |