jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __SOC_ROCKCHIP_RK3288_GRF_H__ |
| 21 | #define __SOC_ROCKCHIP_RK3288_GRF_H__ |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 22 | |
| 23 | #include <types.h> |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 24 | #include "addressmap.h" |
huang lin | 82ba4d0 | 2014-08-16 10:49:32 +0800 | [diff] [blame^] | 25 | #include "soc.h" |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 26 | |
| 27 | struct rk3288_grf_gpio_lh { |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 28 | u32 l; |
| 29 | u32 h; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 30 | }; |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 31 | check_member(rk3288_grf_gpio_lh, h, 0x4); |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 32 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 33 | struct rk3288_grf_regs { |
| 34 | u32 reserved[3]; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 35 | union { |
| 36 | u32 gpio1d_iomux; |
| 37 | u32 iomux_lcdc; |
| 38 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 39 | u32 gpio2a_iomux; |
| 40 | u32 gpio2b_iomux; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 41 | union { |
| 42 | u32 gpio2c_iomux; |
| 43 | u32 iomux_i2c3; |
| 44 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 45 | u32 reserved2; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 46 | union { |
| 47 | u32 gpio3a_iomux; |
| 48 | u32 iomux_emmcdata; |
| 49 | }; |
| 50 | union { |
| 51 | u32 gpio3b_iomux; |
| 52 | u32 iomux_emmcpwren; |
| 53 | }; |
| 54 | union { |
| 55 | u32 gpio3c_iomux; |
| 56 | u32 iomux_emmccmd; |
| 57 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 58 | u32 gpio3dl_iomux; |
| 59 | u32 gpio3dh_iomux; |
| 60 | u32 gpio4al_iomux; |
| 61 | u32 gpio4ah_iomux; |
| 62 | u32 gpio4bl_iomux; |
| 63 | u32 reserved3; |
| 64 | u32 gpio4c_iomux; |
| 65 | u32 gpio4d_iomux; |
| 66 | u32 reserved4; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 67 | union { |
| 68 | u32 gpio5b_iomux; |
| 69 | u32 iomux_spi0; |
| 70 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 71 | u32 gpio5c_iomux; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 72 | u32 reserved5; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 73 | union { |
| 74 | u32 gpio6a_iomux; |
| 75 | u32 iomux_i2s; |
| 76 | }; |
| 77 | union { |
| 78 | u32 gpio6b_iomux; |
| 79 | u32 iomux_i2c2; |
| 80 | u32 iomux_i2sclk; |
| 81 | }; |
| 82 | union { |
| 83 | u32 gpio6c_iomux; |
| 84 | u32 iomux_sdmmc0; |
| 85 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 86 | u32 reserved6; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 87 | union { |
| 88 | u32 gpio7a_iomux; |
| 89 | u32 iomux_pwm0; |
| 90 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 91 | u32 gpio7b_iomux; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 92 | union { |
| 93 | u32 gpio7cl_iomux; |
| 94 | u32 iomux_i2c5sda; |
| 95 | u32 iomux_i2c4; |
| 96 | }; |
| 97 | union { |
| 98 | u32 gpio7ch_iomux; |
| 99 | u32 iomux_uart2; |
| 100 | u32 iomux_i2c5scl; |
| 101 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 102 | u32 reserved7; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 103 | union { |
| 104 | u32 gpio8a_iomux; |
| 105 | u32 iomux_spi2csclk; |
| 106 | u32 iomux_i2c1; |
| 107 | }; |
| 108 | union { |
| 109 | u32 gpio8b_iomux; |
| 110 | u32 iomux_spi2txrx; |
| 111 | }; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 112 | u32 reserved8[30]; |
| 113 | struct rk3288_grf_gpio_lh gpio_sr[8]; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 114 | u32 gpio1_p[8][4]; |
| 115 | u32 gpio1_e[8][4]; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 116 | u32 gpio_smt; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 117 | u32 soc_con0; |
| 118 | u32 soc_con1; |
| 119 | u32 soc_con2; |
| 120 | u32 soc_con3; |
| 121 | u32 soc_con4; |
| 122 | u32 soc_con5; |
| 123 | u32 soc_con6; |
| 124 | u32 soc_con7; |
| 125 | u32 soc_con8; |
| 126 | u32 soc_con9; |
| 127 | u32 soc_con10; |
| 128 | u32 soc_con11; |
| 129 | u32 soc_con12; |
| 130 | u32 soc_con13; |
| 131 | u32 soc_con14; |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 132 | u32 soc_status[22]; |
| 133 | u32 reserved9[2]; |
| 134 | u32 peridmac_con[4]; |
| 135 | u32 ddrc0_con0; |
| 136 | u32 ddrc1_con0; |
| 137 | u32 cpu_con[5]; |
| 138 | u32 reserved10[3]; |
| 139 | u32 cpu_status0; |
| 140 | u32 reserved11; |
| 141 | u32 uoc0_con[5]; |
| 142 | u32 uoc1_con[5]; |
| 143 | u32 uoc2_con[4]; |
| 144 | u32 uoc3_con[2]; |
| 145 | u32 uoc4_con[2]; |
| 146 | u32 pvtm_con[3]; |
| 147 | u32 pvtm_status[3]; |
| 148 | u32 io_vsel; |
| 149 | u32 saradc_testbit; |
| 150 | u32 tsadc_testbit_l; |
| 151 | u32 tsadc_testbit_h; |
| 152 | u32 os_reg[4]; |
| 153 | u32 reserved12; |
| 154 | u32 soc_con15; |
| 155 | u32 soc_con16; |
| 156 | }; |
| 157 | check_member(rk3288_grf_regs, soc_con16, 0x3a8); |
| 158 | |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 159 | struct rk3288_sgrf_regs { |
| 160 | u32 soc_con0; |
| 161 | u32 soc_con1; |
| 162 | u32 soc_con2; |
| 163 | u32 soc_con3; |
| 164 | u32 soc_con4; |
| 165 | u32 soc_con5; |
| 166 | u32 reserved1[(0x20-0x18)/4]; |
| 167 | u32 busdmac_con[2]; |
| 168 | u32 reserved2[(0x40-0x28)/4]; |
| 169 | u32 cpu_con[3]; |
| 170 | u32 reserved3[(0x50-0x4c)/4]; |
| 171 | u32 soc_con6; |
| 172 | u32 soc_con7; |
| 173 | u32 soc_con8; |
| 174 | u32 soc_con9; |
| 175 | u32 soc_con10; |
| 176 | u32 soc_con11; |
| 177 | u32 soc_con12; |
| 178 | u32 soc_con13; |
| 179 | u32 soc_con14; |
| 180 | u32 soc_con15; |
| 181 | u32 soc_con16; |
| 182 | u32 soc_con17; |
| 183 | u32 soc_con18; |
| 184 | u32 soc_con19; |
| 185 | u32 soc_con20; |
| 186 | u32 soc_con21; |
| 187 | u32 reserved4[(0x100-0x90)/4]; |
| 188 | u32 soc_status[2]; |
| 189 | u32 reserved5[(0x120-0x108)/4]; |
| 190 | u32 fast_boot_addr; |
| 191 | }; |
| 192 | check_member(rk3288_sgrf_regs, fast_boot_addr, 0x0120); |
| 193 | |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 194 | static struct rk3288_grf_regs * const rk3288_grf = (void *)GRF_BASE; |
huang lin | 5a9b8f6 | 2014-08-26 17:30:40 +0800 | [diff] [blame] | 195 | static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE; |
| 196 | |
| 197 | #define IOMUX_I2C1 RK_CLRSETBITS(3 << 10 | 3 << 8, 1 << 10 | 1 << 8) |
| 198 | #define IOMUX_I2C2 RK_SETBITS(1 << 4 | 1 << 2) |
| 199 | #define IOMUX_I2C3 RK_SETBITS(1 << 2 | 1 << 0) |
| 200 | #define IOMUX_I2C4 RK_SETBITS(1 << 8 | 1 << 4) |
| 201 | #define IOMUX_I2C5SDA RK_CLRSETBITS(3 << 12, 1 << 12) |
| 202 | #define IOMUX_I2C5SCL RK_CLRSETBITS(3 << 0, 1 << 0) |
| 203 | #define IOMUX_SPI0 RK_CLRSETBITS(0xff << 8, 1 << 14 | 1 << 12 | \ |
| 204 | 1 << 10 | 1 << 8) |
| 205 | #define IOMUX_SPI2_CSCLK RK_CLRSETBITS(3 << 14 | 3 << 12, 1 << 14 | 1 << 12) |
| 206 | #define IOMUX_SPI2_TXRX RK_CLRSETBITS(3 << 2 | 3 << 0, 1 << 2 | 1 << 0) |
| 207 | #define IOMUX_I2S RK_SETBITS(1 << 8 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) |
| 208 | #define IOMUX_I2SCLK RK_SETBITS(1 << 0) |
| 209 | #define IOMUX_UART2 RK_CLRSETBITS(7 << 12 | 3 << 8, 1 << 12 | 1 << 8) |
| 210 | #define IOMUX_LCDC RK_SETBITS(1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) |
| 211 | #define IOMUX_SDMMC0 RK_CLRSETBITS(0x17ff, 1 << 12 | 1 << 10 | 1 << 8 |\ |
| 212 | 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0) |
| 213 | #define IOMUX_EMMCDATA RK_CLRSETBITS(0xffff, 2 << 14 | 2 << 12 | 2 << 10 |\ |
| 214 | 2 << 8 | 2 << 6 | 2 << 4 |\ |
| 215 | 2 << 2 | 2 << 0) |
| 216 | #define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2) |
| 217 | #define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0) |
jinkun.hong | 503d121 | 2014-07-31 14:50:49 +0800 | [diff] [blame] | 218 | #endif |