Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 4 | * Copyright 2013 Google Inc. |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <types.h> |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 21 | #include <stdlib.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 22 | |
| 23 | #include <armv7.h> |
| 24 | #include <cbfs.h> |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 25 | #include <cbmem.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 26 | |
| 27 | #include <arch/cache.h> |
| 28 | #include <cpu/samsung/exynos5420/i2c.h> |
| 29 | #include <cpu/samsung/exynos5420/clk.h> |
| 30 | #include <cpu/samsung/exynos5420/cpu.h> |
| 31 | #include <cpu/samsung/exynos5420/dmc.h> |
| 32 | #include <cpu/samsung/exynos5420/gpio.h> |
| 33 | #include <cpu/samsung/exynos5420/setup.h> |
| 34 | #include <cpu/samsung/exynos5420/periph.h> |
| 35 | #include <cpu/samsung/exynos5420/power.h> |
| 36 | #include <cpu/samsung/exynos5420/wakeup.h> |
| 37 | #include <console/console.h> |
| 38 | #include <arch/stages.h> |
| 39 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 40 | #include <drivers/maxim/max77802/max77802.h> |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 41 | #include <device/i2c.h> |
| 42 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 43 | #define PMIC_I2C_BUS 4 |
| 44 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 45 | struct pmic_write |
| 46 | { |
| 47 | int or_orig; // Whether to or in the original value. |
| 48 | uint8_t reg; // Register to write. |
| 49 | uint8_t val; // Value to write. |
| 50 | }; |
| 51 | |
| 52 | /* |
| 53 | * Use read-modify-write for MAX77802 control registers and clobber the |
| 54 | * output voltage setting (BUCK?DVS?) registers. |
| 55 | */ |
| 56 | struct pmic_write pmic_writes[] = |
| 57 | { |
| 58 | { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, |
| 59 | { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, |
| 60 | { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | |
| 61 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame] | 62 | { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1_2625V }, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 63 | { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 64 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 65 | { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, |
| 66 | { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 67 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 68 | { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, |
| 69 | { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | |
| 70 | MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, |
| 71 | { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, |
| 72 | { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | |
Ronald G. Minnich | 88ac9b5 | 2013-06-26 17:28:52 -0700 | [diff] [blame] | 73 | MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, |
David Hendricks | 1f9f04e | 2013-08-01 18:57:52 -0700 | [diff] [blame] | 74 | /* Disable Boost(bypass) OUTPUT */ |
| 75 | { 0, MAX77802_REG_PMIC_BOOSTCTRL, MAX77802_BOOSTCTRL_OFF}, |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 76 | }; |
| 77 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 78 | static int setup_power(int is_resume) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 79 | { |
| 80 | int error = 0; |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 81 | int i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 82 | |
| 83 | power_init(); |
| 84 | |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 85 | if (is_resume) { |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 86 | return 0; |
Hung-Te Lin | da7b8e4 | 2013-06-28 17:27:17 +0800 | [diff] [blame] | 87 | } |
| 88 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 89 | /* Initialize I2C bus to configure PMIC. */ |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 90 | exynos_pinmux_i2c4(); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 91 | i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 92 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 93 | for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { |
| 94 | uint8_t data = 0; |
| 95 | uint8_t reg = pmic_writes[i].reg; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 96 | |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 97 | if (pmic_writes[i].or_orig) |
| 98 | error |= i2c_read(4, MAX77802_I2C_ADDR, |
| 99 | reg, sizeof(reg), |
| 100 | &data, sizeof(data)); |
| 101 | data |= pmic_writes[i].val; |
| 102 | error |= i2c_write(4, MAX77802_I2C_ADDR, |
| 103 | reg, sizeof(reg), |
| 104 | &data, sizeof(data)); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 105 | } |
David Hendricks | 1e3e2c5 | 2013-06-14 16:08:05 -0700 | [diff] [blame] | 106 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 107 | return error; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 108 | } |
| 109 | |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 110 | static void setup_ec(void) |
| 111 | { |
| 112 | /* SPI2 (EC) is slower and needs to work in half-duplex mode with |
| 113 | * single byte bus width. */ |
Gabe Black | 9801809 | 2013-07-24 06:18:20 -0700 | [diff] [blame] | 114 | clock_set_rate(PERIPH_ID_SPI2, 5000000); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 115 | exynos_pinmux_spi2(); |
| 116 | } |
| 117 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 118 | static void setup_gpio(void) |
| 119 | { |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 120 | gpio_direction_input(GPIO_X30); // WP_GPIO |
| 121 | gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 122 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 123 | gpio_direction_input(GPIO_X07); // RECMODE_GPIO |
| 124 | gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 125 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 126 | gpio_direction_input(GPIO_X34); // LID_GPIO |
| 127 | gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 128 | |
Gabe Black | 63bb610 | 2013-06-19 03:29:45 -0700 | [diff] [blame] | 129 | gpio_direction_input(GPIO_X12); // POWER_GPIO |
| 130 | gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | static void setup_memory(struct mem_timings *mem, int is_resume) |
| 134 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 135 | printk(BIOS_SPEW, "manufacturer: 0x%x type: 0x%x, div: 0x%x, mhz: %d\n", |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 136 | mem->mem_manuf, |
| 137 | mem->mem_type, |
| 138 | mem->mpll_mdiv, |
| 139 | mem->frequency_mhz); |
| 140 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 141 | if (ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, !is_resume)) { |
| 142 | die("Failed to initialize memory controller.\n"); |
| 143 | } |
| 144 | } |
| 145 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 146 | #define PRIMITIVE_MEM_TEST 0 |
| 147 | #if PRIMITIVE_MEM_TEST |
| 148 | static unsigned long primitive_mem_test(void) |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 149 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 150 | unsigned long *l = (void *)0x40000000; |
| 151 | int bad = 0; |
| 152 | unsigned long i; |
| 153 | for(i = 0; i < 256*1048576; i++){ |
| 154 | if (! (i%1048576)) |
| 155 | printk(BIOS_SPEW, "%lu ...", i); |
| 156 | l[i] = 0xffffffff - i; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 157 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 158 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 159 | for(i = 0; i < 256*1048576; i++){ |
| 160 | if (! (i%1048576)) |
| 161 | printk(BIOS_SPEW, "%lu ...", i); |
| 162 | if (l[i] != (0xffffffff - i)){ |
| 163 | printk(BIOS_SPEW, "%p: want %08lx got %08lx\n", l, l[i], 0xffffffff - i); |
| 164 | bad++; |
| 165 | } |
| 166 | } |
Gabe Black | 5420e09 | 2013-05-17 11:29:22 -0700 | [diff] [blame] | 167 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 168 | printk(BIOS_SPEW, "%d errors\n", bad); |
| 169 | |
| 170 | return bad; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 171 | } |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 172 | #else |
| 173 | #define primitive_mem_test() |
| 174 | #endif |
| 175 | |
| 176 | #define SIMPLE_SPI_TEST 0 |
| 177 | #if SIMPLE_SPI_TEST |
| 178 | /* here is a simple SPI debug test, known to fid trouble */ |
| 179 | static void simple_spi_test(void) |
| 180 | { |
| 181 | struct cbfs_media default_media, *media; |
| 182 | int i, amt = 4 * MiB, errors = 0; |
| 183 | //u32 *data = (void *)0x40000000; |
| 184 | u32 data[1024]; |
| 185 | u32 in; |
| 186 | |
| 187 | amt = sizeof(data); |
| 188 | media = &default_media; |
| 189 | if (init_default_cbfs_media(media) != 0) { |
| 190 | printk(BIOS_SPEW, "Failed to initialize default media.\n"); |
| 191 | return; |
| 192 | } |
| 193 | |
| 194 | |
| 195 | media->open(media); |
| 196 | if (media->read(media, data, (size_t) 0, amt) < amt){ |
| 197 | printk(BIOS_SPEW, "simple_spi_test fails\n"); |
| 198 | return; |
| 199 | } |
| 200 | |
| 201 | |
| 202 | for(i = 0; i < amt; i += 4){ |
| 203 | if (media->read(media, &in, (size_t) i, 4) < 1){ |
| 204 | printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); |
| 205 | return; |
| 206 | } |
| 207 | if (data[i/4] != in){ |
| 208 | errors++; |
| 209 | printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 210 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 211 | /* reread it to see which is wrong. */ |
| 212 | if (media->read(media, &in, (size_t) i, 4) < 1){ |
| 213 | printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); |
| 214 | return; |
| 215 | } |
| 216 | printk(BIOS_SPEW, "RTRY at %d(%p):\nRAM %08lx\nSPI %08lx\n", |
| 217 | i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); |
| 218 | } |
| 219 | |
| 220 | } |
| 221 | printk(BIOS_SPEW, "%d errors\n", errors); |
| 222 | } |
| 223 | #else |
| 224 | #define simple_spi_test() |
| 225 | #endif |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 226 | |
| 227 | void main(void) |
| 228 | { |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 229 | |
| 230 | extern struct mem_timings mem_timings; |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 231 | void *entry; |
| 232 | int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 233 | int power_init_failed; |
| 234 | |
Hung-Te Lin | 0682cfe | 2013-08-06 20:37:55 +0800 | [diff] [blame] | 235 | exynos5420_config_smp(); |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 236 | power_init_failed = setup_power(is_resume); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 237 | |
| 238 | /* Clock must be initialized before console_init, otherwise you may need |
| 239 | * to re-initialize serial console drivers again. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 240 | system_clock_init(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 241 | |
Gabe Black | 136e709 | 2013-08-09 00:31:09 -0700 | [diff] [blame] | 242 | exynos_pinmux_uart3(); |
Stefan Reinauer | 998ab0d | 2013-05-20 12:29:37 -0700 | [diff] [blame] | 243 | console_init(); |
| 244 | |
David Hendricks | 77acf42 | 2013-08-05 21:04:16 -0700 | [diff] [blame] | 245 | if (power_init_failed) |
| 246 | die("Failed to intialize power.\n"); |
| 247 | |
| 248 | /* re-initialize PMIC I2C channel after (re-)setting system clocks */ |
| 249 | i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ |
| 250 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 251 | setup_memory(&mem_timings, is_resume); |
| 252 | |
| 253 | primitive_mem_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 254 | |
| 255 | if (is_resume) { |
| 256 | wakeup(); |
| 257 | } |
| 258 | |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 259 | setup_gpio(); |
Hung-Te Lin | c357aed | 2013-06-24 20:02:01 +0800 | [diff] [blame] | 260 | setup_ec(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 261 | |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 262 | simple_spi_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 263 | /* Set SPI (primary CBFS media) clock to 50MHz. */ |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 264 | /* if this is uncommented SPI will not work correctly. */ |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 265 | clock_set_rate(PERIPH_ID_SPI1, 50000000); |
Julius Werner | 45d2ff3 | 2013-08-12 18:04:06 -0700 | [diff] [blame] | 266 | exynos_pinmux_spi1(); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 267 | simple_spi_test(); |
Stefan Reinauer | 80e6293 | 2013-07-29 15:52:23 -0700 | [diff] [blame] | 268 | |
| 269 | cbmem_initialize_empty(); |
| 270 | |
Furquan Shaikh | 20f25dd | 2014-04-22 10:41:05 -0700 | [diff] [blame] | 271 | entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); |
Ronald G. Minnich | e6af929 | 2013-06-03 13:03:50 -0700 | [diff] [blame] | 272 | simple_spi_test(); |
Gabe Black | d3163ab | 2013-05-16 05:53:40 -0700 | [diff] [blame] | 273 | stage_exit(entry); |
| 274 | } |