Tim Crawford | 8093b77c | 2024-05-29 16:31:17 -0600 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 3 | chip soc/intel/tigerlake |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 4 | # Power limits |
| 5 | register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ |
| 6 | .tdp_pl1_override = 20, |
| 7 | .tdp_pl2_override = 30, |
| 8 | }" |
| 9 | register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ |
| 10 | .tdp_pl1_override = 20, |
| 11 | .tdp_pl2_override = 30, |
| 12 | }" |
| 13 | |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 14 | # GPE configuration |
| 15 | register "pmc_gpe0_dw0" = "PMC_GPP_R" |
| 16 | register "pmc_gpe0_dw1" = "PMC_GPP_B" |
| 17 | register "pmc_gpe0_dw2" = "PMC_GPP_D" |
| 18 | |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 19 | device domain 0 on |
| 20 | subsystemid 0x1558 0x14a1 inherit |
| 21 | |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 22 | device ref peg on |
| 23 | # PCIe PEG0 x4, Clock 3 (SSD1) |
| 24 | # Despite the name, SSD2_CLKREQ# is used for SSD1 |
| 25 | register "PcieClkSrcUsage[3]" = "0x40" |
| 26 | register "PcieClkSrcClkReq[3]" = "3" |
| 27 | chip soc/intel/common/block/pcie/rtd3 |
| 28 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN# |
| 29 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly) |
Tim Crawford | 2a404b5 | 2022-01-07 14:12:34 -0700 | [diff] [blame] | 30 | register "srcclk_pin" = "3" # SSD2_CLKREQ# |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 31 | device generic 0 on end |
| 32 | end |
| 33 | end |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 34 | device ref north_xhci on # J_TYPEC1 |
| 35 | register "UsbTcPortEn" = "1" |
| 36 | register "TcssXhciEn" = "1" |
| 37 | chip drivers/usb/acpi |
| 38 | device ref tcss_root_hub on |
| 39 | chip drivers/usb/acpi |
| 40 | register "desc" = ""USB3 J_TYPEC1"" |
| 41 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 42 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 43 | device ref tcss_usb3_port1 on end |
| 44 | end |
| 45 | end |
| 46 | end |
| 47 | end |
| 48 | device ref tbt_dma0 on # J_TYPEC1 |
| 49 | chip drivers/intel/usb4/retimer |
| 50 | register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" |
| 51 | use tcss_usb3_port1 as dfp[0].typec_port |
| 52 | device generic 0 on end |
| 53 | end |
| 54 | end |
| 55 | |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 56 | device ref south_xhci on |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame] | 57 | register "usb2_ports" = "{ |
| 58 | [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */ |
| 59 | [1] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */ |
| 60 | [2] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */ |
| 61 | [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| 62 | [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 63 | }" |
| 64 | register "usb3_ports" = "{ |
| 65 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */ |
| 66 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */ |
| 67 | }" |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 68 | # ACPI |
| 69 | chip drivers/usb/acpi |
| 70 | device ref xhci_root_hub on |
| 71 | chip drivers/usb/acpi |
| 72 | register "desc" = ""USB2 J_USB3_1"" |
| 73 | register "type" = "UPC_TYPE_A" |
| 74 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 75 | device ref usb2_port1 on end |
| 76 | end |
| 77 | chip drivers/usb/acpi |
| 78 | register "desc" = ""USB2 J_USB3_2"" |
| 79 | register "type" = "UPC_TYPE_A" |
| 80 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 81 | device ref usb2_port2 on end |
| 82 | end |
| 83 | chip drivers/usb/acpi |
| 84 | register "desc" = ""USB2 J_TYPEC1"" |
| 85 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 86 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 87 | device ref usb2_port3 on end |
| 88 | end |
| 89 | chip drivers/usb/acpi |
| 90 | register "desc" = ""USB2 Camera"" |
| 91 | register "type" = "UPC_TYPE_INTERNAL" |
| 92 | device ref usb2_port7 on end |
| 93 | end |
| 94 | chip drivers/usb/acpi |
| 95 | register "desc" = ""USB2 Bluetooth"" |
| 96 | register "type" = "UPC_TYPE_INTERNAL" |
| 97 | device ref usb2_port10 on end |
| 98 | end |
| 99 | chip drivers/usb/acpi |
| 100 | register "desc" = ""USB3 J_USB3_1"" |
| 101 | register "type" = "UPC_TYPE_A" |
| 102 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 103 | device ref usb3_port1 on end |
| 104 | end |
| 105 | chip drivers/usb/acpi |
| 106 | register "desc" = ""USB3 J_USB3_2"" |
| 107 | register "type" = "UPC_TYPE_A" |
| 108 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 109 | device ref usb3_port2 on end |
| 110 | end |
| 111 | end |
| 112 | end |
| 113 | end |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 114 | device ref sata on |
| 115 | # SATA1 (SSD2) |
| 116 | register "SataPortsEnable[1]" = "1" |
| 117 | register "SataPortsDevSlp[1]" = "1" |
| 118 | register "SataPortsEnableDitoConfig[1]" = "1" |
| 119 | register "SataSalpSupport" = "1" |
| 120 | end |
| 121 | device ref pcie_rp3 on |
| 122 | # PCIe root port #3 x1, Clock 1 (WLAN) |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 123 | register "PcieRpLtrEnable[2]" = "1" |
| 124 | register "PcieClkSrcUsage[1]" = "2" |
| 125 | register "PcieClkSrcClkReq[1]" = "1" |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 126 | register "PcieRpSlotImplemented[2]" = "1" |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 127 | end |
| 128 | device ref pcie_rp6 on |
| 129 | # PCIe root port #6 x1, Clock 2 (CARD) |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 130 | register "PcieRpLtrEnable[5]" = "1" |
| 131 | register "PcieClkSrcUsage[2]" = "5" |
| 132 | register "PcieClkSrcClkReq[2]" = "2" |
| 133 | end |
| 134 | device ref pcie_rp9 on |
| 135 | # PCIe root port #9 x4, Clock 0 (SSD2) |
| 136 | # Despite the name, SSD1_CLKREQ# is used for SSD2 |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 137 | register "PcieRpLtrEnable[8]" = "1" |
| 138 | register "PcieClkSrcUsage[0]" = "8" |
| 139 | register "PcieClkSrcClkReq[0]" = "0" |
Michael Niewöhner | 45b6080 | 2022-01-08 20:47:11 +0100 | [diff] [blame] | 140 | register "PcieRpSlotImplemented[8]" = "1" |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 141 | chip soc/intel/common/block/pcie/rtd3 |
| 142 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN# |
| 143 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly) |
| 144 | register "srcclk_pin" = "0" |
| 145 | device generic 0 on end |
| 146 | end |
| 147 | end |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 148 | device ref pmc hidden |
| 149 | # The pmc_mux chip driver is a placeholder for the |
| 150 | # PMC.MUX device in the ACPI hierarchy. |
| 151 | chip drivers/intel/pmc_mux |
| 152 | device generic 0 on |
| 153 | chip drivers/intel/pmc_mux/conn |
| 154 | # J_TYPEC1 |
Reka Norman | d448f8c | 2021-12-09 12:09:27 +1100 | [diff] [blame] | 155 | use usb2_port3 as usb2_port |
| 156 | use tcss_usb3_port1 as usb3_port |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 157 | # SBU & HSL follow CC |
| 158 | device generic 0 alias conn0 on end |
| 159 | end |
| 160 | end |
| 161 | end |
| 162 | end |
Tim Crawford | 4dcee4f | 2021-04-13 09:46:12 -0600 | [diff] [blame] | 163 | end |
| 164 | end |