Tim Crawford | 8093b77c | 2024-05-29 16:31:17 -0600 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Tim Crawford | 6875231 | 2023-07-14 10:11:07 -0600 | [diff] [blame] | 3 | chip soc/intel/alderlake |
| 4 | register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ |
| 5 | .tdp_pl1_override = 20, |
| 6 | .tdp_pl2_override = 56, |
| 7 | }" |
| 8 | |
| 9 | device domain 0 on |
| 10 | subsystemid 0x1558 0x51b1 inherit |
| 11 | |
| 12 | device ref pcie4_0 on |
| 13 | # CPU RP#1 x4, Clock 0 (SSD2) |
| 14 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 15 | .clk_src = 0, |
| 16 | .clk_req = 0, |
| 17 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 18 | }" |
Tim Crawford | 3a4e139 | 2024-05-21 15:38:23 -0600 | [diff] [blame] | 19 | chip soc/intel/common/block/pcie/rtd3 |
| 20 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST# |
| 21 | register "srcclk_pin" = "0" # SSD2_CLKREQ# |
| 22 | device generic 0 on end |
| 23 | end |
Tim Crawford | 6875231 | 2023-07-14 10:11:07 -0600 | [diff] [blame] | 24 | end |
| 25 | device ref pcie4_1 on |
| 26 | # CPU RP#3 x4, Clock 4 (SSD1) |
| 27 | register "cpu_pcie_rp[CPU_RP(3)]" = "{ |
| 28 | .clk_src = 4, |
| 29 | .clk_req = 4, |
| 30 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 31 | }" |
Tim Crawford | 3a4e139 | 2024-05-21 15:38:23 -0600 | [diff] [blame] | 32 | chip soc/intel/common/block/pcie/rtd3 |
| 33 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# |
| 34 | register "srcclk_pin" = "4" # SSD1_CLKREQ# |
| 35 | device generic 0 on end |
| 36 | end |
Tim Crawford | 6875231 | 2023-07-14 10:11:07 -0600 | [diff] [blame] | 37 | end |
| 38 | device ref tbt_pcie_rp0 on end |
| 39 | device ref tcss_xhci on |
| 40 | register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" |
| 41 | end |
| 42 | device ref tcss_dma0 on end |
| 43 | device ref xhci on |
Felix Singer | 983b169 | 2023-10-26 16:14:34 +0200 | [diff] [blame] | 44 | register "usb2_ports" = "{ |
| 45 | [0] = USB2_PORT_MID(OC_SKIP), /* Type-A */ |
| 46 | [1] = USB2_PORT_MID(OC_SKIP), /* Type-A */ |
| 47 | [2] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 (USB-C) */ |
| 48 | [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ |
| 49 | [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 (Thunderbolt) */ |
| 50 | [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ |
| 51 | [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ |
| 52 | }" |
| 53 | register "usb3_ports" = "{ |
| 54 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A */ |
| 55 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */ |
| 56 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */ |
| 57 | }" |
Tim Crawford | 6875231 | 2023-07-14 10:11:07 -0600 | [diff] [blame] | 58 | end |
| 59 | device ref i2c0 on |
| 60 | # Touchpad I2C bus |
| 61 | register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" |
| 62 | chip drivers/i2c/hid |
| 63 | register "generic.hid" = ""ELAN0412"" |
| 64 | register "generic.desc" = ""ELAN Touchpad"" |
| 65 | register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" |
| 66 | register "generic.detect" = "1" |
| 67 | register "hid_desc_reg_offset" = "0x01" |
| 68 | device i2c 15 on end |
| 69 | end |
| 70 | chip drivers/i2c/hid |
| 71 | register "generic.hid" = ""FTCS1000"" |
| 72 | register "generic.desc" = ""FocalTech Touchpad"" |
| 73 | register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" |
| 74 | register "generic.detect" = "1" |
| 75 | register "hid_desc_reg_offset" = "0x01" |
| 76 | device i2c 38 on end |
| 77 | end |
| 78 | end |
| 79 | device ref sata off end |
| 80 | device ref pcie_rp5 on |
| 81 | # PCIe RP#5 x1, Clock 2 (WLAN) |
| 82 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 83 | .clk_src = 2, |
| 84 | .clk_req = 2, |
| 85 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 86 | }" |
| 87 | end |
| 88 | device ref pcie_rp6 on |
| 89 | # PCIe RP#6 x1, Clock 5 (CARD) |
| 90 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 91 | .clk_src = 5, |
| 92 | .clk_req = 5, |
| 93 | .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, |
| 94 | }" |
| 95 | end |
| 96 | device ref pcie_rp8 on |
| 97 | # PCIe RP#8 x1, Clock 6 (GLAN) |
| 98 | register "pch_pcie_rp[PCH_RP(8)]" = "{ |
| 99 | .clk_src = 6, |
| 100 | .clk_req = 6, |
| 101 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 102 | }" |
| 103 | end |
| 104 | end |
| 105 | end |