Tim Crawford | 8093b77c | 2024-05-29 16:31:17 -0600 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
Jeremy Soller | 9037f0a | 2021-04-09 10:51:31 -0600 | [diff] [blame] | 3 | chip soc/intel/skylake |
| 4 | # Send an extra VR mailbox command for the PS4 exit issue |
| 5 | register "SendVrMbxCmd" = "2" |
| 6 | |
| 7 | # Power limit |
| 8 | register "power_limits_config" = "{ |
| 9 | .tdp_pl1_override = 20, |
| 10 | .tdp_pl2_override = 30, |
| 11 | }" |
| 12 | |
| 13 | # Enable Enhanced Intel SpeedStep |
| 14 | register "eist_enable" = "1" |
| 15 | |
| 16 | # Serial I/O |
| 17 | register "SerialIoDevMode" = "{ |
| 18 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART |
| 19 | }" |
| 20 | |
| 21 | # Serial IRQ |
| 22 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 23 | |
| 24 | # Power |
| 25 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 26 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 27 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 28 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 29 | |
| 30 | # FSP Configuration |
| 31 | register "SkipExtGfxScan" = "1" |
| 32 | register "SaGv" = "SaGv_Enabled" |
| 33 | |
| 34 | # VR Settings Configuration for 4 Domains |
| 35 | #+----------------+-----------+-----------+-------------+----------+ |
| 36 | #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| 37 | #+----------------+-----------+-----------+-------------+----------+ |
| 38 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 39 | #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| 40 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 41 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 42 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 43 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 44 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 45 | #| IccMax | 5A | 64A | 31A | 31A | |
| 46 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 47 | #+----------------+-----------+-----------+-------------+----------+ |
| 48 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 49 | .vr_config_enable = 1, |
| 50 | .psi1threshold = VR_CFG_AMP(20), |
| 51 | .psi2threshold = VR_CFG_AMP(4), |
| 52 | .psi3threshold = VR_CFG_AMP(1), |
| 53 | .psi3enable = 0, |
| 54 | .psi4enable = 0, |
| 55 | .imon_slope = 0x0, |
| 56 | .imon_offset = 0x0, |
| 57 | .icc_max = VR_CFG_AMP(5), |
| 58 | .voltage_limit = 1520, |
| 59 | .ac_loadline = 1030, |
| 60 | .dc_loadline = 1030, |
| 61 | }" |
| 62 | |
| 63 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 64 | .vr_config_enable = 1, |
| 65 | .psi1threshold = VR_CFG_AMP(20), |
| 66 | .psi2threshold = VR_CFG_AMP(5), |
| 67 | .psi3threshold = VR_CFG_AMP(1), |
| 68 | .psi3enable = 0, |
| 69 | .psi4enable = 0, |
| 70 | .imon_slope = 0x0, |
| 71 | .imon_offset = 0x0, |
| 72 | .icc_max = VR_CFG_AMP(64), |
| 73 | .voltage_limit = 1520, |
| 74 | .ac_loadline = 240, |
| 75 | .dc_loadline = 240, |
| 76 | }" |
| 77 | |
| 78 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 79 | .vr_config_enable = 1, |
| 80 | .psi1threshold = VR_CFG_AMP(20), |
| 81 | .psi2threshold = VR_CFG_AMP(5), |
| 82 | .psi3threshold = VR_CFG_AMP(1), |
| 83 | .psi3enable = 0, |
| 84 | .psi4enable = 0, |
| 85 | .imon_slope = 0x0, |
| 86 | .imon_offset = 0x0, |
| 87 | .icc_max = VR_CFG_AMP(31), |
| 88 | .voltage_limit = 1520, |
| 89 | .ac_loadline = 310, |
| 90 | .dc_loadline = 310, |
| 91 | }" |
| 92 | |
| 93 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 94 | .vr_config_enable = 1, |
| 95 | .psi1threshold = VR_CFG_AMP(20), |
| 96 | .psi2threshold = VR_CFG_AMP(5), |
| 97 | .psi3threshold = VR_CFG_AMP(1), |
| 98 | .psi3enable = 0, |
| 99 | .psi4enable = 0, |
| 100 | .imon_slope = 0x0, |
| 101 | .imon_offset = 0x0, |
| 102 | .icc_max = VR_CFG_AMP(31), |
| 103 | .voltage_limit = 1520, |
| 104 | .ac_loadline = 310, |
| 105 | .dc_loadline = 310, |
| 106 | }" |
| 107 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 108 | device cpu_cluster 0 on end |
Jeremy Soller | 9037f0a | 2021-04-09 10:51:31 -0600 | [diff] [blame] | 109 | |
| 110 | device domain 0 on |
| 111 | device ref system_agent on end |
| 112 | device ref igpu on end |
| 113 | device ref sa_thermal on end |
| 114 | device ref south_xhci on |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame] | 115 | register "usb2_ports" = "{ |
| 116 | [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port right */ |
| 117 | [1] = USB2_PORT_FLEX(OC_SKIP), /* 3G / LTE */ |
| 118 | [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */ |
| 119 | [3] = USB2_PORT_FLEX(OC_SKIP), /* Camera */ |
| 120 | [4] = USB2_PORT_FLEX(OC_SKIP), /* Bluetooth */ |
| 121 | [6] = USB2_PORT_FLEX(OC_SKIP), /* Type-A port left */ |
| 122 | [7] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */ |
| 123 | }" |
| 124 | register "usb3_ports" = "{ |
| 125 | [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port right */ |
| 126 | [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */ |
| 127 | [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type C port right */ |
| 128 | [3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port left */ |
| 129 | }" |
Jeremy Soller | 9037f0a | 2021-04-09 10:51:31 -0600 | [diff] [blame] | 130 | end |
| 131 | device ref thermal on end |
| 132 | device ref sata on |
| 133 | register "SataSalpSupport" = "0" |
Jeremy Soller | 9037f0a | 2021-04-09 10:51:31 -0600 | [diff] [blame] | 134 | register "SataSpeedLimit" = "2" |
Felix Singer | ee1fd54 | 2023-10-26 15:42:16 +0200 | [diff] [blame] | 135 | register "SataPortsEnable" = "{ |
| 136 | [0] = 1, |
| 137 | [2] = 1, |
| 138 | }" |
Jeremy Soller | 9037f0a | 2021-04-09 10:51:31 -0600 | [diff] [blame] | 139 | end |
| 140 | device ref pcie_rp1 on |
| 141 | # Root port #1 x4 (TBT) |
| 142 | register "PcieRpEnable[0]" = "1" |
| 143 | register "PcieRpClkReqSupport[0]" = "1" |
| 144 | register "PcieRpClkReqNumber[0]" = "4" |
| 145 | register "PcieRpClkSrcNumber[0]" = "4" |
| 146 | register "PcieRpAdvancedErrorReporting[0]" = "1" |
| 147 | register "PcieRpLtrEnable[0]" = "1" |
| 148 | register "PcieRpHotPlug[0]" = "1" |
| 149 | end |
| 150 | device ref pcie_rp5 on |
| 151 | # Root port #5 x1 (LAN) |
| 152 | register "PcieRpEnable[4]" = "1" |
| 153 | register "PcieRpClkReqSupport[4]" = "1" |
| 154 | register "PcieRpClkReqNumber[4]" = "3" |
| 155 | register "PcieRpClkSrcNumber[4]" = "3" |
| 156 | register "PcieRpAdvancedErrorReporting[4]" = "1" |
| 157 | register "PcieRpLtrEnable[4]" = "1" |
| 158 | end |
| 159 | device ref pcie_rp6 on |
| 160 | # Root port #6 x1 (WLAN) |
| 161 | register "PcieRpEnable[5]" = "1" |
| 162 | register "PcieRpClkReqSupport[5]" = "1" |
| 163 | register "PcieRpClkReqNumber[5]" = "2" |
| 164 | register "PcieRpClkSrcNumber[5]" = "2" |
| 165 | register "PcieRpAdvancedErrorReporting[5]" = "1" |
| 166 | register "PcieRpLtrEnable[5]" = "1" |
| 167 | end |
| 168 | device ref pcie_rp9 on |
| 169 | # Root port #9 x4 (NVMe) |
| 170 | register "PcieRpEnable[8]" = "1" |
| 171 | register "PcieRpClkReqSupport[8]" = "1" |
| 172 | register "PcieRpClkReqNumber[8]" = "5" |
| 173 | register "PcieRpClkSrcNumber[8]" = "5" |
| 174 | register "PcieRpAdvancedErrorReporting[8]" = "1" |
| 175 | register "PcieRpLtrEnable[8]" = "1" |
| 176 | end |
| 177 | device ref lpc_espi on |
| 178 | register "gen1_dec" = "0x000c0681" |
| 179 | register "gen2_dec" = "0x000c1641" |
| 180 | register "gen3_dec" = "0x00040069" |
| 181 | chip drivers/pc80/tpm |
| 182 | device pnp 0c31.0 on end |
| 183 | end |
| 184 | end |
| 185 | device ref p2sb off end |
| 186 | device ref pmc on |
| 187 | register "gpe0_dw0" = "GPP_C" |
| 188 | register "gpe0_dw1" = "GPP_D" |
| 189 | register "gpe0_dw2" = "GPP_E" |
| 190 | end |
| 191 | device ref hda on end |
| 192 | device ref smbus on end |
| 193 | device ref fast_spi on end |
| 194 | end |
| 195 | end |