Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2009 Vipin Kumar, ST Microelectronics |
| 5 | * Copyright 2016 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 17 | #include <arch/acpigen.h> |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 18 | #include <arch/io.h> |
| 19 | #include <commonlib/helpers.h> |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/i2c.h> |
Duncan Laurie | 222381e | 2016-06-21 10:41:19 -0700 | [diff] [blame] | 23 | #include <string.h> |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 24 | #include <timer.h> |
| 25 | #include "lpss_i2c.h" |
| 26 | |
| 27 | struct lpss_i2c_regs { |
| 28 | uint32_t control; |
| 29 | uint32_t target_addr; |
| 30 | uint32_t slave_addr; |
| 31 | uint32_t master_addr; |
| 32 | uint32_t cmd_data; |
| 33 | uint32_t ss_scl_hcnt; |
| 34 | uint32_t ss_scl_lcnt; |
| 35 | uint32_t fs_scl_hcnt; |
| 36 | uint32_t fs_scl_lcnt; |
| 37 | uint32_t hs_scl_hcnt; |
| 38 | uint32_t hs_scl_lcnt; |
| 39 | uint32_t intr_stat; |
| 40 | uint32_t intr_mask; |
| 41 | uint32_t raw_intr_stat; |
| 42 | uint32_t rx_thresh; |
| 43 | uint32_t tx_thresh; |
| 44 | uint32_t clear_intr; |
| 45 | uint32_t clear_rx_under_intr; |
| 46 | uint32_t clear_rx_over_intr; |
| 47 | uint32_t clear_tx_over_intr; |
| 48 | uint32_t clear_rd_req_intr; |
| 49 | uint32_t clear_tx_abrt_intr; |
| 50 | uint32_t clear_rx_done_intr; |
| 51 | uint32_t clear_activity_intr; |
| 52 | uint32_t clear_stop_det_intr; |
| 53 | uint32_t clear_start_det_intr; |
| 54 | uint32_t clear_gen_call_intr; |
| 55 | uint32_t enable; |
| 56 | uint32_t status; |
| 57 | uint32_t tx_level; |
| 58 | uint32_t rx_level; |
| 59 | uint32_t sda_hold; |
| 60 | uint32_t tx_abort_source; |
| 61 | } __attribute__((packed)); |
| 62 | |
| 63 | /* Use a ~2ms timeout for various operations */ |
| 64 | #define LPSS_I2C_TIMEOUT_US 2000 |
| 65 | |
| 66 | /* High and low times in different speed modes (in ns) */ |
| 67 | enum { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 68 | /* SDA Hold Time */ |
| 69 | DEFAULT_SDA_HOLD_TIME = 300, |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 70 | /* Standard Speed */ |
| 71 | MIN_SS_SCL_HIGHTIME = 4000, |
| 72 | MIN_SS_SCL_LOWTIME = 4700, |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 73 | /* Fast Speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 74 | MIN_FS_SCL_HIGHTIME = 600, |
| 75 | MIN_FS_SCL_LOWTIME = 1300, |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 76 | /* Fast Plus Speed */ |
| 77 | MIN_FP_SCL_HIGHTIME = 260, |
| 78 | MIN_FP_SCL_LOWTIME = 500, |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 79 | /* High Speed */ |
| 80 | MIN_HS_SCL_HIGHTIME = 60, |
| 81 | MIN_HS_SCL_LOWTIME = 160, |
| 82 | }; |
| 83 | |
| 84 | /* Control register definitions */ |
| 85 | enum { |
| 86 | CONTROL_MASTER_MODE = (1 << 0), |
| 87 | CONTROL_SPEED_SS = (1 << 1), |
| 88 | CONTROL_SPEED_FS = (1 << 2), |
| 89 | CONTROL_SPEED_HS = (3 << 1), |
| 90 | CONTROL_SPEED_MASK = (3 << 1), |
| 91 | CONTROL_10BIT_SLAVE = (1 << 3), |
| 92 | CONTROL_10BIT_MASTER = (1 << 4), |
| 93 | CONTROL_RESTART_ENABLE = (1 << 5), |
| 94 | CONTROL_SLAVE_DISABLE = (1 << 6), |
| 95 | }; |
| 96 | |
| 97 | /* Command/Data register definitions */ |
| 98 | enum { |
| 99 | CMD_DATA_CMD = (1 << 8), |
| 100 | CMD_DATA_STOP = (1 << 9), |
| 101 | }; |
| 102 | |
| 103 | /* Status register definitions */ |
| 104 | enum { |
| 105 | STATUS_ACTIVITY = (1 << 0), |
| 106 | STATUS_TX_FIFO_NOT_FULL = (1 << 1), |
| 107 | STATUS_TX_FIFO_EMPTY = (1 << 2), |
| 108 | STATUS_RX_FIFO_NOT_EMPTY = (1 << 3), |
| 109 | STATUS_RX_FIFO_FULL = (1 << 4), |
| 110 | STATUS_MASTER_ACTIVITY = (1 << 5), |
| 111 | STATUS_SLAVE_ACTIVITY = (1 << 6), |
| 112 | }; |
| 113 | |
| 114 | /* Enable register definitions */ |
| 115 | enum { |
| 116 | ENABLE_CONTROLLER = (1 << 0), |
| 117 | }; |
| 118 | |
| 119 | /* Interrupt status register definitions */ |
| 120 | enum { |
| 121 | INTR_STAT_RX_UNDER = (1 << 0), |
| 122 | INTR_STAT_RX_OVER = (1 << 1), |
| 123 | INTR_STAT_RX_FULL = (1 << 2), |
| 124 | INTR_STAT_TX_OVER = (1 << 3), |
| 125 | INTR_STAT_TX_EMPTY = (1 << 4), |
| 126 | INTR_STAT_RD_REQ = (1 << 5), |
| 127 | INTR_STAT_TX_ABORT = (1 << 6), |
| 128 | INTR_STAT_RX_DONE = (1 << 7), |
| 129 | INTR_STAT_ACTIVITY = (1 << 8), |
| 130 | INTR_STAT_STOP_DET = (1 << 9), |
| 131 | INTR_STAT_START_DET = (1 << 10), |
| 132 | INTR_STAT_GEN_CALL = (1 << 11), |
| 133 | }; |
| 134 | |
| 135 | /* Enable this I2C controller */ |
| 136 | static void lpss_i2c_enable(struct lpss_i2c_regs *regs) |
| 137 | { |
| 138 | uint32_t enable = read32(®s->enable); |
| 139 | |
| 140 | if (!(enable & ENABLE_CONTROLLER)) |
| 141 | write32(®s->enable, enable | ENABLE_CONTROLLER); |
| 142 | } |
| 143 | |
| 144 | /* Disable this I2C controller */ |
| 145 | static int lpss_i2c_disable(struct lpss_i2c_regs *regs) |
| 146 | { |
| 147 | uint32_t enable = read32(®s->enable); |
| 148 | |
| 149 | if (enable & ENABLE_CONTROLLER) { |
| 150 | struct stopwatch sw; |
| 151 | |
| 152 | write32(®s->enable, enable & ~ENABLE_CONTROLLER); |
| 153 | |
| 154 | /* Wait for enable bit to clear */ |
| 155 | stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); |
| 156 | while (read32(®s->enable) & ENABLE_CONTROLLER) |
| 157 | if (stopwatch_expired(&sw)) |
| 158 | return -1; |
| 159 | } |
| 160 | |
| 161 | return 0; |
| 162 | } |
| 163 | |
| 164 | /* Wait for this I2C controller to go idle for transmit */ |
| 165 | static int lpss_i2c_wait_for_bus_idle(struct lpss_i2c_regs *regs) |
| 166 | { |
| 167 | struct stopwatch sw; |
| 168 | |
| 169 | /* Start timeout for up to 16 bytes in FIFO */ |
| 170 | stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); |
| 171 | |
| 172 | while (!stopwatch_expired(&sw)) { |
| 173 | uint32_t status = read32(®s->status); |
| 174 | |
| 175 | /* Check for master activity and keep waiting */ |
| 176 | if (status & STATUS_MASTER_ACTIVITY) |
| 177 | continue; |
| 178 | |
| 179 | /* Check for TX FIFO empty to indicate TX idle */ |
| 180 | if (status & STATUS_TX_FIFO_EMPTY) |
| 181 | return 0; |
| 182 | } |
| 183 | |
| 184 | /* Timed out while waiting for bus to go idle */ |
| 185 | return -1; |
| 186 | } |
| 187 | |
| 188 | /* Transfer one byte of one segment, sending stop bit if requested */ |
| 189 | static int lpss_i2c_transfer_byte(struct lpss_i2c_regs *regs, |
| 190 | struct i2c_seg *segment, |
| 191 | size_t byte, int send_stop) |
| 192 | { |
| 193 | struct stopwatch sw; |
| 194 | uint32_t cmd = CMD_DATA_CMD; /* Read op */ |
| 195 | |
| 196 | stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); |
| 197 | |
| 198 | if (!segment->read) { |
| 199 | /* Write op only: Wait for FIFO not full */ |
| 200 | while (!(read32(®s->status) & STATUS_TX_FIFO_NOT_FULL)) { |
| 201 | if (stopwatch_expired(&sw)) { |
| 202 | printk(BIOS_ERR, "I2C transmit timeout\n"); |
| 203 | return -1; |
| 204 | } |
| 205 | } |
| 206 | cmd = segment->buf[byte]; |
| 207 | } |
| 208 | |
| 209 | /* Send stop on last byte, if desired */ |
| 210 | if (send_stop && byte == segment->len - 1) |
| 211 | cmd |= CMD_DATA_STOP; |
| 212 | |
| 213 | write32(®s->cmd_data, cmd); |
| 214 | |
| 215 | if (segment->read) { |
| 216 | /* Read op only: Wait for FIFO data and store it */ |
| 217 | while (!(read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY)) { |
| 218 | if (stopwatch_expired(&sw)) { |
| 219 | printk(BIOS_ERR, "I2C receive timeout\n"); |
| 220 | return -1; |
| 221 | } |
| 222 | } |
| 223 | segment->buf[byte] = read32(®s->cmd_data); |
| 224 | } |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | /* Global I2C bus handler, defined in include/i2c.h */ |
| 230 | int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) |
| 231 | { |
| 232 | struct stopwatch sw; |
| 233 | struct lpss_i2c_regs *regs; |
| 234 | size_t byte; |
| 235 | |
| 236 | if (count <= 0 || !segments) |
| 237 | return -1; |
| 238 | |
| 239 | regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); |
| 240 | if (!regs) { |
| 241 | printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); |
| 242 | return -1; |
| 243 | } |
| 244 | |
| 245 | if (!(read32(®s->enable) & ENABLE_CONTROLLER)) { |
| 246 | printk(BIOS_ERR, "I2C bus %u not initialized\n", bus); |
| 247 | return -1; |
| 248 | } |
| 249 | |
| 250 | if (lpss_i2c_wait_for_bus_idle(regs)) { |
| 251 | printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); |
| 252 | return -1; |
| 253 | } |
| 254 | |
| 255 | /* Process each segment */ |
| 256 | while (count--) { |
| 257 | /* Set target slave address */ |
| 258 | write32(®s->target_addr, segments->chip); |
| 259 | |
| 260 | /* Read or write each byte in segment */ |
| 261 | for (byte = 0; byte < segments->len; byte++) { |
| 262 | /* |
| 263 | * Set stop condition on final segment only. |
| 264 | * Repeated start will be automatically generated |
| 265 | * by the controller on R->W or W->R switch. |
| 266 | */ |
| 267 | if (lpss_i2c_transfer_byte(regs, segments, byte, |
| 268 | count == 0) < 0) { |
| 269 | printk(BIOS_ERR, "I2C %s failed: bus %u " |
| 270 | "addr 0x%02x\n", segments->read ? |
| 271 | "read" : "write", bus, segments->chip); |
| 272 | return -1; |
| 273 | } |
| 274 | } |
| 275 | segments++; |
| 276 | } |
| 277 | |
| 278 | /* Wait for interrupt status to indicate transfer is complete */ |
| 279 | stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); |
| 280 | while (!(read32(®s->raw_intr_stat) & INTR_STAT_STOP_DET)) { |
| 281 | if (stopwatch_expired(&sw)) { |
| 282 | printk(BIOS_ERR, "I2C stop bit not received\n"); |
| 283 | return -1; |
| 284 | } |
| 285 | } |
| 286 | |
| 287 | /* Read to clear INTR_STAT_STOP_DET */ |
| 288 | read32(®s->clear_stop_det_intr); |
| 289 | |
| 290 | /* Wait for the bus to go idle */ |
| 291 | if (lpss_i2c_wait_for_bus_idle(regs)) { |
| 292 | printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); |
| 293 | return -1; |
| 294 | } |
| 295 | |
| 296 | /* Flush the RX FIFO in case it is not empty */ |
| 297 | stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); |
| 298 | while (read32(®s->status) & STATUS_RX_FIFO_NOT_EMPTY) { |
| 299 | if (stopwatch_expired(&sw)) { |
| 300 | printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n"); |
| 301 | return -1; |
| 302 | } |
| 303 | read32(®s->cmd_data); |
| 304 | } |
| 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
Duncan Laurie | 222381e | 2016-06-21 10:41:19 -0700 | [diff] [blame] | 309 | /* |
| 310 | * Write ACPI object to describe speed configuration. |
| 311 | * |
| 312 | * ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold } |
| 313 | * |
| 314 | * SSCN: I2C_SPEED_STANDARD |
| 315 | * FMCN: I2C_SPEED_FAST |
| 316 | * FPCN: I2C_SPEED_FAST_PLUS |
| 317 | * HSCN: I2C_SPEED_HIGH |
| 318 | */ |
| 319 | static void lpss_i2c_acpi_write_speed_config( |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 320 | const struct lpss_i2c_speed_config *config) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 321 | { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 322 | if (!config) |
| 323 | return; |
| 324 | if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 325 | return; |
| 326 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 327 | if (config->speed >= I2C_SPEED_HIGH) |
| 328 | acpigen_write_name("HSCN"); |
| 329 | else if (config->speed >= I2C_SPEED_FAST_PLUS) |
| 330 | acpigen_write_name("FPCN"); |
| 331 | else if (config->speed >= I2C_SPEED_FAST) |
| 332 | acpigen_write_name("FMCN"); |
| 333 | else |
| 334 | acpigen_write_name("SSCN"); |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 335 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 336 | /* Package () { scl_lcnt, scl_hcnt, sda_hold } */ |
| 337 | acpigen_write_package(3); |
| 338 | acpigen_write_word(config->scl_hcnt); |
| 339 | acpigen_write_word(config->scl_lcnt); |
| 340 | acpigen_write_dword(config->sda_hold); |
| 341 | acpigen_pop_len(); |
| 342 | } |
| 343 | |
Duncan Laurie | 222381e | 2016-06-21 10:41:19 -0700 | [diff] [blame] | 344 | void lpss_i2c_acpi_fill_ssdt(const struct lpss_i2c_speed_config *override) |
| 345 | { |
| 346 | const struct lpss_i2c_speed_config *sptr; |
| 347 | struct lpss_i2c_speed_config sgen; |
| 348 | enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = { |
| 349 | I2C_SPEED_STANDARD, |
| 350 | I2C_SPEED_FAST, |
| 351 | I2C_SPEED_FAST_PLUS, |
| 352 | I2C_SPEED_HIGH, |
| 353 | }; |
| 354 | int i; |
| 355 | |
| 356 | /* Report timing values for the OS driver */ |
| 357 | for (i = 0; i < LPSS_I2C_SPEED_CONFIG_COUNT; i++) { |
| 358 | /* Generate speed config for default case */ |
| 359 | if (lpss_i2c_gen_speed_config(speeds[i], &sgen) < 0) |
| 360 | continue; |
| 361 | |
| 362 | /* Apply board specific override for this speed if found */ |
| 363 | for (sptr = override; sptr && sptr->speed; sptr++) { |
| 364 | if (sptr->speed == speeds[i]) { |
| 365 | memcpy(&sgen, sptr, sizeof(sgen)); |
| 366 | break; |
| 367 | } |
| 368 | } |
| 369 | |
| 370 | /* Generate ACPI based on selected speed config */ |
| 371 | lpss_i2c_acpi_write_speed_config(&sgen); |
| 372 | } |
| 373 | } |
| 374 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 375 | int lpss_i2c_set_speed_config(unsigned bus, |
| 376 | const struct lpss_i2c_speed_config *config) |
| 377 | { |
| 378 | struct lpss_i2c_regs *regs; |
| 379 | void *hcnt_reg, *lcnt_reg; |
| 380 | |
| 381 | regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); |
| 382 | if (!regs || !config) |
| 383 | return -1; |
| 384 | |
| 385 | /* Nothing to do if no values are set */ |
| 386 | if (!config->scl_lcnt && !config->scl_hcnt && !config->sda_hold) |
| 387 | return 0; |
| 388 | |
| 389 | if (config->speed >= I2C_SPEED_FAST_PLUS) { |
| 390 | /* Fast-Plus and High speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 391 | hcnt_reg = ®s->hs_scl_hcnt; |
| 392 | lcnt_reg = ®s->hs_scl_lcnt; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 393 | } else if (config->speed >= I2C_SPEED_FAST) { |
| 394 | /* Fast speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 395 | hcnt_reg = ®s->fs_scl_hcnt; |
| 396 | lcnt_reg = ®s->fs_scl_lcnt; |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 397 | } else { |
| 398 | /* Standard speed */ |
| 399 | hcnt_reg = ®s->ss_scl_hcnt; |
| 400 | lcnt_reg = ®s->ss_scl_lcnt; |
| 401 | } |
| 402 | |
| 403 | /* SCL count must be set after the speed is selected */ |
| 404 | if (config->scl_hcnt) |
| 405 | write32(hcnt_reg, config->scl_hcnt); |
| 406 | if (config->scl_lcnt) |
| 407 | write32(lcnt_reg, config->scl_lcnt); |
| 408 | |
| 409 | /* Set SDA Hold Time register */ |
| 410 | if (config->sda_hold) |
| 411 | write32(®s->sda_hold, config->sda_hold); |
| 412 | |
| 413 | return 0; |
| 414 | } |
| 415 | |
| 416 | int lpss_i2c_gen_speed_config(enum i2c_speed speed, |
| 417 | struct lpss_i2c_speed_config *config) |
| 418 | { |
| 419 | const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ; |
| 420 | uint16_t hcnt_min, lcnt_min; |
| 421 | |
| 422 | /* Clock must be provided by Kconfig */ |
| 423 | if (!ic_clk || !config) |
| 424 | return -1; |
| 425 | |
| 426 | if (speed >= I2C_SPEED_HIGH) { |
| 427 | /* High speed */ |
| 428 | hcnt_min = MIN_HS_SCL_HIGHTIME; |
| 429 | lcnt_min = MIN_HS_SCL_LOWTIME; |
| 430 | } else if (speed >= I2C_SPEED_FAST_PLUS) { |
| 431 | /* Fast-Plus speed */ |
| 432 | hcnt_min = MIN_FP_SCL_HIGHTIME; |
| 433 | lcnt_min = MIN_FP_SCL_LOWTIME; |
| 434 | } else if (speed >= I2C_SPEED_FAST) { |
| 435 | /* Fast speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 436 | hcnt_min = MIN_FS_SCL_HIGHTIME; |
| 437 | lcnt_min = MIN_FS_SCL_LOWTIME; |
| 438 | } else { |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 439 | /* Standard speed */ |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 440 | hcnt_min = MIN_SS_SCL_HIGHTIME; |
| 441 | lcnt_min = MIN_SS_SCL_LOWTIME; |
| 442 | } |
| 443 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 444 | config->speed = speed; |
| 445 | config->scl_hcnt = ic_clk * hcnt_min / KHz; |
| 446 | config->scl_lcnt = ic_clk * lcnt_min / KHz; |
| 447 | config->sda_hold = ic_clk * DEFAULT_SDA_HOLD_TIME / KHz; |
| 448 | |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | int lpss_i2c_set_speed(unsigned bus, enum i2c_speed speed) |
| 453 | { |
| 454 | struct lpss_i2c_regs *regs; |
| 455 | struct lpss_i2c_speed_config config; |
| 456 | uint32_t control; |
| 457 | |
| 458 | /* Clock must be provided by Kconfig */ |
| 459 | regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); |
| 460 | if (!regs || !speed) |
| 461 | return -1; |
| 462 | |
| 463 | control = read32(®s->control); |
| 464 | control &= ~CONTROL_SPEED_MASK; |
| 465 | |
| 466 | if (speed >= I2C_SPEED_FAST_PLUS) { |
| 467 | /* High and Fast-Plus speed share config registers */ |
| 468 | control |= CONTROL_SPEED_HS; |
| 469 | } else if (speed >= I2C_SPEED_FAST) { |
| 470 | /* Fast speed */ |
| 471 | control |= CONTROL_SPEED_FS; |
| 472 | } else { |
| 473 | /* Standard speed */ |
| 474 | control |= CONTROL_SPEED_SS; |
| 475 | } |
| 476 | |
| 477 | /* Generate speed config based on clock */ |
| 478 | if (lpss_i2c_gen_speed_config(speed, &config) < 0) |
| 479 | return -1; |
| 480 | |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 481 | /* Select this speed in the control register */ |
| 482 | write32(®s->control, control); |
| 483 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 484 | /* Write the speed config that was generated earlier */ |
| 485 | lpss_i2c_set_speed_config(bus, &config); |
| 486 | |
| 487 | return 0; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 488 | } |
| 489 | |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 490 | int lpss_i2c_init(unsigned bus, enum i2c_speed speed) |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 491 | { |
| 492 | struct lpss_i2c_regs *regs; |
| 493 | |
| 494 | regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); |
| 495 | if (!regs) { |
| 496 | printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 497 | return -1; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 498 | } |
| 499 | |
| 500 | if (lpss_i2c_disable(regs) < 0) { |
| 501 | printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 502 | return -1; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | /* Put controller in master mode with restart enabled */ |
| 506 | write32(®s->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE | |
| 507 | CONTROL_RESTART_ENABLE); |
| 508 | |
| 509 | /* Set bus speed to FAST by default */ |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 510 | if (lpss_i2c_set_speed(bus, speed ? : I2C_SPEED_FAST) < 0) { |
| 511 | printk(BIOS_ERR, "I2C failed to set speed for bus %u\n", bus); |
| 512 | return -1; |
| 513 | } |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 514 | |
| 515 | /* Set RX/TX thresholds to smallest values */ |
| 516 | write32(®s->rx_thresh, 0); |
| 517 | write32(®s->tx_thresh, 0); |
| 518 | |
| 519 | /* Enable stop detection interrupt */ |
| 520 | write32(®s->intr_mask, INTR_STAT_STOP_DET); |
| 521 | |
| 522 | lpss_i2c_enable(regs); |
| 523 | |
| 524 | printk(BIOS_INFO, "LPSS I2C bus %u at 0x%p (%u KHz)\n", |
| 525 | bus, regs, (speed ? : I2C_SPEED_FAST) / KHz); |
Duncan Laurie | 88a1f14 | 2016-06-13 10:28:36 -0700 | [diff] [blame] | 526 | |
| 527 | return 0; |
Duncan Laurie | 8a14c39 | 2016-06-07 13:40:11 -0700 | [diff] [blame] | 528 | } |