Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 806fa2463f16d32f98cff6437576a5efe2874ece / . / src / soc / intel / common / Kconfig
blob: a32252edd85d056b1bb0e4510552333248c3222e [file] [log] [blame]
Stefan Reinauer9616f3c2015-04-29 10:45:22 -0700[diff] [blame]1config SOC_INTEL_COMMON
2 bool
3 help
4 common code for Intel SOCs
5
Lee Leahy0946ec32015-04-20 15:24:54 -0700[diff] [blame]6if SOC_INTEL_COMMON
7
Duncan Lauried8c4f2b2014-04-22 10:46:06 -0700[diff] [blame]8config CACHE_MRC_SETTINGS
9 bool "Save cached MRC settings"
10 default n
11
12if CACHE_MRC_SETTINGS
13
14config MRC_SETTINGS_CACHE_BASE
15 hex
Alexandru Gagniucbc140cf2015-08-28 14:28:35 -0400[diff] [blame]16 default 0xfffe0000
Duncan Lauried8c4f2b2014-04-22 10:46:06 -0700[diff] [blame]17
18config MRC_SETTINGS_CACHE_SIZE
19 hex
20 default 0x10000
21
Duncan Lauriea32b6b92015-01-15 15:49:07 -0800[diff] [blame]22config MRC_SETTINGS_PROTECT
23 bool "Enable protection on MRC settings"
24 default n
25
Duncan Lauried8c4f2b2014-04-22 10:46:06 -0700[diff] [blame]26endif # CACHE_MRC_SETTINGS
27
Lee Leahy0946ec32015-04-20 15:24:54 -0700[diff] [blame]28config DISPLAY_MTRRS
Martin Roth5fe62ef2015-06-24 19:04:16 -0600[diff] [blame]29 bool "MTRRs: Display the MTRR settings"
Lee Leahy0946ec32015-04-20 15:24:54 -0700[diff] [blame]30 default n
31
32config DISPLAY_SMM_MEMORY_MAP
33 bool "SMM: Display the SMM memory map"
34 default n
35
Lee Leahy14ecb542015-02-09 21:16:14 -0800[diff] [blame]36config SOC_INTEL_COMMON_RESET
37 bool
38 default n
Lee Leahy0946ec32015-04-20 15:24:54 -0700[diff] [blame]39
Duncan Laurie63ebc802015-09-08 16:09:28 -0700[diff] [blame]40config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
41 bool
42 default n
43
Duncan Laurie8a14c392016-06-07 13:40:11 -0700[diff] [blame]44config SOC_INTEL_COMMON_LPSS_I2C
45 bool
46 default n
47 help
48 This driver supports the Intel Low Power Subsystem (LPSS) I2C
49 controllers that are based on Synopsys DesignWare IP.
50
51config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
52 int
53 depends on SOC_INTEL_COMMON_LPSS_I2C
54 help
55 The clock speed that the I2C controller is running at, in MHz.
56 No default is set here as this is an SOC-specific value and must
57 be provided by the SOC when it selects this driver.
58
Pratik Prajapatib90b94d2015-09-11 13:51:38 -0700[diff] [blame]59config MMA
Martin Rothdde96fb2015-11-25 22:33:20 -0700[diff] [blame]60 bool "enable MMA (Memory Margin Analysis) support"
61 default n
62 help
63 Set this option to y to enable MMA (Memory Margin Analysis) support
Pratik Prajapatib90b94d2015-09-11 13:51:38 -0700[diff] [blame]64
65config MMA_BLOBS_PATH
Martin Rothdde96fb2015-11-25 22:33:20 -0700[diff] [blame]66 string "Path to MMA blobs"
67 depends on MMA
68 default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
Pratik Prajapatib90b94d2015-09-11 13:51:38 -0700[diff] [blame]69
Andrey Petrov060b2152016-05-13 15:27:42 -0700[diff] [blame]70config ADD_VBT_DATA_FILE
71 bool "Add a Video Bios Table (VBT) binary to CBFS"
72 help
73 Add a VBT file data file to CBFS. The VBT describes the integrated
74 GPU and connections, and is needed by FSP in order to initialize the
75 display.
76
77config VBT_FILE
78 string "VBT binary path and filename"
79 depends on ADD_VBT_DATA_FILE
80 help
81 The path and filename of the VBT binary.
82
Andrey Petrovdc4ae112016-05-12 19:10:11 -0700[diff] [blame]83config SOC_INTEL_COMMON_GFX_OPREGION
84 bool
85 default n
86
Hannah Williamsba0fc472016-05-04 18:15:49 -0700[diff] [blame]87config SOC_INTEL_COMMON_SMI
88 bool
89 default n
90
Hannah Williamsf8daa372016-04-18 13:40:04 -0700[diff] [blame]91config SOC_INTEL_COMMON_ACPI
92 bool
93 default n
94
Aaron Durbinc14a1a92016-06-28 15:41:07 -0500[diff] [blame]95config SOC_INTEL_COMMON_NHLT
96 bool
97 default n
98
Lee Leahy0946ec32015-04-20 15:24:54 -0700[diff] [blame]99endif # SOC_INTEL_COMMON