| Duncan Laurie | 8d2b49f | 2015-12-22 17:15:29 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | // Use simple device model for this file even in ramstage |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <console/console.h> |
| 22 | #include <device/pci_ehci.h> |
| 23 | #include <device/pci_def.h> |
| 24 | |
| 25 | pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) |
| 26 | { |
| 27 | u32 class; |
| 28 | pci_devfn_t dev = PCI_DEV(0, 0x1d, 0); |
| 29 | |
| 30 | class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; |
| 31 | if (class != PCI_EHCI_CLASSCODE) |
| 32 | return 0; |
| 33 | |
| 34 | return dev; |
| 35 | } |
| 36 | |
| 37 | void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) |
| 38 | { |
| 39 | /* Hardcoded to physical port 1 */ |
| 40 | } |
| 41 | |
| 42 | void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) |
| 43 | { |
| 44 | u32 tmp32; |
| 45 | |
| 46 | if (!dev) |
| 47 | return; |
| 48 | |
| 49 | /* Set the EHCI BAR address. */ |
| 50 | pci_write_config32(dev, EHCI_BAR_INDEX, base); |
| 51 | |
| 52 | /* Enable access to the EHCI memory space registers. */ |
| 53 | pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); |
| 54 | |
| 55 | /* Force ownership of hte Debug Port to the EHCI controller. */ |
| 56 | tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET)); |
| 57 | tmp32 |= (1 << 30); |
| 58 | write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32); |
| 59 | } |