Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 21 | #include <soc/gpio.h> |
| 22 | #include <soc/iomap.h> |
| 23 | #include <soc/pm.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * This function will return a number that indicates which PIRQ |
| 27 | * this GPIO maps to. If this is not a PIRQ capable GPIO then |
| 28 | * it will return -1. The GPIO to PIRQ mapping is not linear. |
| 29 | */ |
| 30 | static int gpio_to_pirq(int gpio) |
| 31 | { |
| 32 | switch (gpio) { |
| 33 | case 8: return 0; /* PIRQI */ |
| 34 | case 9: return 1; /* PIRQJ */ |
| 35 | case 10: return 2; /* PIRQK */ |
| 36 | case 13: return 3; /* PIRQL */ |
| 37 | case 14: return 4; /* PIRQM */ |
| 38 | case 45: return 5; /* PIRQN */ |
| 39 | case 46: return 6; /* PIRQO */ |
| 40 | case 47: return 7; /* PIRQP */ |
| 41 | case 48: return 8; /* PIRQQ */ |
| 42 | case 49: return 9; /* PIRQR */ |
| 43 | case 50: return 10; /* PIRQS */ |
| 44 | case 51: return 11; /* PIRQT */ |
| 45 | case 52: return 12; /* PIRQU */ |
| 46 | case 53: return 13; /* PIRQV */ |
| 47 | case 54: return 14; /* PIRQW */ |
| 48 | case 55: return 15; /* PIRQX */ |
| 49 | default: return -1; |
| 50 | }; |
| 51 | } |
| 52 | |
| 53 | void init_one_gpio(int gpio_num, struct gpio_config *config) |
| 54 | { |
| 55 | u32 owner, route, irqen, reset; |
| 56 | int set, bit; |
| 57 | |
| 58 | if (gpio_num > MAX_GPIO_NUMBER || !config) |
| 59 | return; |
| 60 | |
| 61 | outl(config->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); |
| 62 | outl(config->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio_num)); |
| 63 | |
| 64 | /* Determine set and bit based on GPIO number */ |
| 65 | set = gpio_num >> 5; |
| 66 | bit = gpio_num % 32; |
| 67 | |
| 68 | /* Save settings from current GPIO config */ |
| 69 | owner = inl(GPIO_BASE_ADDRESS + GPIO_OWNER(set)); |
| 70 | route = inl(GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); |
| 71 | irqen = inl(GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); |
| 72 | reset = inl(GPIO_BASE_ADDRESS + GPIO_RESET(set)); |
| 73 | |
| 74 | owner |= config->owner << bit; |
| 75 | route |= config->route << bit; |
| 76 | irqen |= config->irqen << bit; |
| 77 | reset |= config->reset << bit; |
| 78 | |
| 79 | outl(owner, GPIO_BASE_ADDRESS + GPIO_OWNER(set)); |
| 80 | outl(route, GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); |
| 81 | outl(irqen, GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); |
| 82 | outl(reset, GPIO_BASE_ADDRESS + GPIO_RESET(set)); |
| 83 | |
| 84 | if (set == 0) { |
| 85 | u32 blink = inl(GPIO_BASE_ADDRESS + GPIO_BLINK); |
| 86 | blink |= config->blink << bit; |
| 87 | outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); |
| 88 | } |
| 89 | |
| 90 | /* PIRQ to IO-APIC map */ |
| 91 | if (config->pirq == GPIO_PIRQ_APIC_ROUTE) { |
| 92 | u32 pirq2apic = inl(GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); |
| 93 | set = gpio_to_pirq(gpio_num); |
| 94 | if (set >= 0) { |
| 95 | pirq2apic |= 1 << set; |
| 96 | outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); |
| 97 | } |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | void init_gpios(const struct gpio_config config[]) |
| 102 | { |
| 103 | const struct gpio_config *entry; |
| 104 | u32 owner[3] = {0}; |
| 105 | u32 route[3] = {0}; |
| 106 | u32 irqen[3] = {0}; |
| 107 | u32 reset[3] = {0}; |
| 108 | u32 blink = 0; |
| 109 | u16 pirq2apic = 0; |
| 110 | int set, bit, gpio = 0; |
| 111 | |
| 112 | for (entry = config; entry->conf0 != GPIO_LIST_END; entry++, gpio++) { |
| 113 | if (gpio > MAX_GPIO_NUMBER) |
| 114 | break; |
| 115 | |
| 116 | /* Setup Configuration registers 1 and 2 */ |
| 117 | outl(entry->conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio)); |
| 118 | outl(entry->conf1, GPIO_BASE_ADDRESS + GPIO_CONFIG1(gpio)); |
| 119 | |
| 120 | /* Determine set and bit based on GPIO number */ |
| 121 | set = gpio >> 5; |
| 122 | bit = gpio % 32; |
| 123 | |
| 124 | /* Apply settings to set specific bits */ |
| 125 | owner[set] |= entry->owner << bit; |
| 126 | route[set] |= entry->route << bit; |
| 127 | irqen[set] |= entry->irqen << bit; |
| 128 | reset[set] |= entry->reset << bit; |
| 129 | |
| 130 | if (set == 0) |
| 131 | blink |= entry->blink << bit; |
| 132 | |
| 133 | /* PIRQ to IO-APIC map */ |
| 134 | if (entry->pirq == GPIO_PIRQ_APIC_ROUTE) { |
| 135 | set = gpio_to_pirq(gpio); |
| 136 | if (set >= 0) |
| 137 | pirq2apic |= 1 << set; |
| 138 | } |
| 139 | } |
| 140 | |
| 141 | for (set = 0; set <= 2; set++) { |
| 142 | outl(owner[set], GPIO_BASE_ADDRESS + GPIO_OWNER(set)); |
| 143 | outl(route[set], GPIO_BASE_ADDRESS + GPIO_ROUTE(set)); |
| 144 | outl(irqen[set], GPIO_BASE_ADDRESS + GPIO_IRQ_IE(set)); |
| 145 | outl(reset[set], GPIO_BASE_ADDRESS + GPIO_RESET(set)); |
| 146 | } |
| 147 | |
| 148 | outl(blink, GPIO_BASE_ADDRESS + GPIO_BLINK); |
| 149 | outl(pirq2apic, GPIO_BASE_ADDRESS + GPIO_PIRQ_APIC_EN); |
| 150 | } |
| 151 | |
| 152 | int get_gpio(int gpio_num) |
| 153 | { |
| 154 | if (gpio_num > MAX_GPIO_NUMBER) |
| 155 | return 0; |
| 156 | |
| 157 | return !!(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); |
| 158 | } |
| 159 | |
| 160 | /* |
| 161 | * get a number comprised of multiple GPIO values. gpio_num_array points to |
| 162 | * the array of gpio pin numbers to scan, terminated by -1. |
| 163 | */ |
| 164 | unsigned get_gpios(const int *gpio_num_array) |
| 165 | { |
| 166 | int gpio; |
| 167 | unsigned bitmask = 1; |
| 168 | unsigned vector = 0; |
| 169 | |
| 170 | while (bitmask && |
| 171 | ((gpio = *gpio_num_array++) != -1)) { |
| 172 | if (get_gpio(gpio)) |
| 173 | vector |= bitmask; |
| 174 | bitmask <<= 1; |
| 175 | } |
| 176 | return vector; |
| 177 | } |
| 178 | |
| 179 | void set_gpio(int gpio_num, int value) |
| 180 | { |
| 181 | u32 conf0; |
| 182 | |
| 183 | if (gpio_num > MAX_GPIO_NUMBER) |
| 184 | return; |
| 185 | |
| 186 | conf0 = inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); |
| 187 | conf0 &= ~GPO_LEVEL_MASK; |
| 188 | conf0 |= value << GPO_LEVEL_SHIFT; |
| 189 | outl(conf0, GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)); |
| 190 | } |
| 191 | |
| 192 | int gpio_is_native(int gpio_num) |
| 193 | { |
| 194 | return !(inl(GPIO_BASE_ADDRESS + GPIO_CONFIG0(gpio_num)) & 1); |
| 195 | } |