Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ |
| 18 | #define _SOC_INTEL_BROADWELL_CHIP_H_ |
| 19 | |
| 20 | struct soc_intel_broadwell_config { |
| 21 | /* |
| 22 | * Interrupt Routing configuration |
| 23 | * If bit7 is 1, the interrupt is disabled. |
| 24 | */ |
| 25 | uint8_t pirqa_routing; |
| 26 | uint8_t pirqb_routing; |
| 27 | uint8_t pirqc_routing; |
| 28 | uint8_t pirqd_routing; |
| 29 | uint8_t pirqe_routing; |
| 30 | uint8_t pirqf_routing; |
| 31 | uint8_t pirqg_routing; |
| 32 | uint8_t pirqh_routing; |
| 33 | |
| 34 | /* GPE configuration */ |
| 35 | uint32_t gpe0_en_1; |
| 36 | uint32_t gpe0_en_2; |
| 37 | uint32_t gpe0_en_3; |
| 38 | uint32_t gpe0_en_4; |
| 39 | |
| 40 | /* GPIO SMI configuration */ |
| 41 | uint32_t alt_gp_smi_en; |
| 42 | |
| 43 | /* IDE configuration */ |
| 44 | uint8_t sata_port_map; |
| 45 | uint32_t sata_port0_gen3_tx; |
| 46 | uint32_t sata_port1_gen3_tx; |
| 47 | uint32_t sata_port0_gen3_dtle; |
| 48 | uint32_t sata_port1_gen3_dtle; |
| 49 | |
| 50 | /* |
| 51 | * SATA DEVSLP Mux |
| 52 | * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 |
| 53 | * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 |
| 54 | */ |
| 55 | uint8_t sata_devslp_mux; |
| 56 | |
| 57 | /* |
| 58 | * DEVSLP Disable |
| 59 | * 0: DEVSLP is enabled |
| 60 | * 1: DEVSLP is disabled |
| 61 | */ |
| 62 | uint8_t sata_devslp_disable; |
| 63 | |
| 64 | /* Generic IO decode ranges */ |
| 65 | uint32_t gen1_dec; |
| 66 | uint32_t gen2_dec; |
| 67 | uint32_t gen3_dec; |
| 68 | uint32_t gen4_dec; |
| 69 | |
| 70 | /* Enable linear PCIe Root Port function numbers starting at zero */ |
| 71 | uint8_t pcie_port_coalesce; |
| 72 | |
| 73 | /* Force root port ASPM configuration with port bitmap */ |
| 74 | uint8_t pcie_port_force_aspm; |
| 75 | |
| 76 | /* Put SerialIO devices into ACPI mode instead of a PCI device */ |
| 77 | uint8_t sio_acpi_mode; |
| 78 | |
| 79 | /* I2C voltage select: 0=3.3V 1=1.8V */ |
| 80 | uint8_t sio_i2c0_voltage; |
| 81 | uint8_t sio_i2c1_voltage; |
| 82 | |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 83 | /* Enable ADSP power gating features */ |
| 84 | uint8_t adsp_d3_pg_enable; |
| 85 | uint8_t adsp_sram_pg_enable; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 86 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 87 | /* |
| 88 | * Clock Disable Map: |
| 89 | * [21:16] = CLKOUT_PCIE# 5-0 |
| 90 | * [24] = CLKOUT_ITPXDP |
| 91 | */ |
| 92 | uint32_t icc_clock_disable; |
| 93 | |
| 94 | /* |
| 95 | * Digital Port Hotplug Enable: |
| 96 | * 0x04 = Enabled, 2ms short pulse |
| 97 | * 0x05 = Enabled, 4.5ms short pulse |
| 98 | * 0x06 = Enabled, 6ms short pulse |
| 99 | * 0x07 = Enabled, 100ms short pulse |
| 100 | */ |
| 101 | u8 gpu_dp_b_hotplug; |
| 102 | u8 gpu_dp_c_hotplug; |
| 103 | u8 gpu_dp_d_hotplug; |
| 104 | |
| 105 | /* Panel power sequence timings */ |
| 106 | u8 gpu_panel_port_select; |
| 107 | u8 gpu_panel_power_cycle_delay; |
| 108 | u16 gpu_panel_power_up_delay; |
| 109 | u16 gpu_panel_power_down_delay; |
| 110 | u16 gpu_panel_power_backlight_on_delay; |
| 111 | u16 gpu_panel_power_backlight_off_delay; |
| 112 | |
| 113 | /* Panel backlight settings */ |
| 114 | u32 gpu_cpu_backlight; |
| 115 | u32 gpu_pch_backlight; |
| 116 | |
| 117 | /* |
| 118 | * Graphics CD Clock Frequency |
| 119 | * 0 = 337.5MHz |
| 120 | * 1 = 450MHz |
| 121 | * 2 = 540MHz |
| 122 | * 3 = 675MHz |
| 123 | */ |
| 124 | int cdclk; |
| 125 | |
| 126 | /* Enable S0iX support */ |
| 127 | int s0ix_enable; |
| 128 | |
Duncan Laurie | ff0f460 | 2015-01-20 07:53:27 -0800 | [diff] [blame] | 129 | /* |
| 130 | * Minimum voltage for C6/C7 state: |
| 131 | * 0x67 = 1.6V (full swing) |
| 132 | * ... |
| 133 | * 0x79 = 1.7V |
| 134 | * ... |
| 135 | * 0x83 = 1.8V (no swing) |
| 136 | */ |
| 137 | int vr_cpu_min_vid; |
| 138 | |
| 139 | /* |
| 140 | * Set slow VR ramp rate on C-state exit: |
| 141 | * 0 = Fast VR ramp rate / 2 |
| 142 | * 1 = Fast VR ramp rate / 4 |
| 143 | * 2 = Fast VR ramp rate / 8 |
| 144 | * 3 = Fast VR ramp rate / 16 |
| 145 | */ |
| 146 | int vr_slow_ramp_rate_set; |
| 147 | |
| 148 | /* Enable slow VR ramp rate */ |
| 149 | int vr_slow_ramp_rate_enable; |
| 150 | |
Duncan Laurie | 446fb8e | 2014-08-08 09:59:43 -0700 | [diff] [blame] | 151 | /* Deep SX enable */ |
| 152 | int deep_sx_enable_ac; |
| 153 | int deep_sx_enable_dc; |
| 154 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 155 | /* TCC activation offset */ |
| 156 | int tcc_offset; |
| 157 | }; |
| 158 | |
| 159 | typedef struct soc_intel_broadwell_config config_t; |
| 160 | |
| 161 | extern struct chip_operations soc_ops; |
| 162 | |
| 163 | #endif |