Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <soc/gpio.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/iomap.h> |
| 19 | |
| 20 | #define SUSPEND_CYCLE 1 |
| 21 | #define RESUME_CYCLE 0 |
| 22 | #define LPC_FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO) |
| 23 | #define LPC_INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO) |
| 24 | #define LPC_GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \ |
| 25 | + (FAMILY_PAD_REGS_SIZE * LPC_FAMILY_NUMBER(gpio_pad) \ |
| 26 | + (GPIO_REGS_SIZE * LPC_INTERNAL_PAD_NUM(gpio_pad)))) |
| 27 | |
| 28 | #define LPC_AD2_MMIO_OFFSET LPC_GPIO_OFFSET(45) |
| 29 | #define LPC_CLKRUN_MMIO_OFFSET LPC_GPIO_OFFSET(46) |
| 30 | #define LPC_AD0_MMIO_OFFSET LPC_GPIO_OFFSET(47) |
| 31 | #define LPC_FRAME_MMIO_OFFSET LPC_GPIO_OFFSET(48) |
| 32 | #define LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50) |
| 33 | #define LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52) |
| 34 | |
| 35 | |
| 36 | /* Value written into pad control reg 0 in early init */ |
| 37 | #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \ |
| 38 | | PAD_GPIOFG_HI_Z \ |
| 39 | | PAD_MODE_SELECTION(mode) | PAD_PULL(term)) |
| 40 | |
| 41 | #define PAD_CFG0_NATIVE_PU20K(mode) PAD_CFG0_NATIVE(mode, 9, 0) /* PU 20K */ |
| 42 | #define PAD_CFG0_NATIVE_PD20K(mode) PAD_CFG0_NATIVE(mode, 1, 0) /* PD 20K */ |
| 43 | #define PAD_CFG0_NATIVE_M1 PAD_CFG0_NATIVE(1, 0, 0) /* no pull */ |
| 44 | |
| 45 | /* |
| 46 | * Configure value in LPC GPIO PADCFG0 registers. This function would be called |
| 47 | * to configure for low power/restore LPC GPIO lines |
| 48 | */ |
| 49 | static void lpc_gpio_config(u32 cycle) |
| 50 | { |
| 51 | if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ |
| 52 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 53 | LPC_FRAME_MMIO_OFFSET), |
| 54 | PAD_CFG0_NATIVE_PU20K(1)); |
| 55 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 56 | LPC_AD0_MMIO_OFFSET), |
| 57 | PAD_CFG0_NATIVE_PU20K(1)); |
| 58 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 59 | LPC_AD1_MMIO_OFFSET), |
| 60 | PAD_CFG0_NATIVE_PU20K(1)); |
| 61 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 62 | LPC_AD2_MMIO_OFFSET), |
| 63 | PAD_CFG0_NATIVE_PU20K(1)); |
| 64 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 65 | LPC_AD3_MMIO_OFFSET), |
| 66 | PAD_CFG0_NATIVE_PU20K(1)); |
| 67 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 68 | LPC_CLKRUN_MMIO_OFFSET), |
| 69 | PAD_CFG0_NATIVE_PD20K(1)); |
| 70 | } else { /* Resume cycle */ |
| 71 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 72 | LPC_FRAME_MMIO_OFFSET), |
| 73 | PAD_CFG0_NATIVE_M1); |
| 74 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 75 | LPC_AD0_MMIO_OFFSET), |
| 76 | PAD_CFG0_NATIVE_PU20K(1)); |
| 77 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 78 | LPC_AD1_MMIO_OFFSET), |
| 79 | PAD_CFG0_NATIVE_PU20K(1)); |
| 80 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 81 | LPC_AD2_MMIO_OFFSET), |
| 82 | PAD_CFG0_NATIVE_PU20K(1)); |
| 83 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 84 | LPC_AD3_MMIO_OFFSET), |
| 85 | PAD_CFG0_NATIVE_PU20K(1)); |
| 86 | write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + |
| 87 | LPC_CLKRUN_MMIO_OFFSET), |
| 88 | PAD_CFG0_NATIVE_M1); |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | /* |
| 93 | * configure LPC GPIO lines for low power |
| 94 | */ |
| 95 | void lpc_set_low_power(void) |
| 96 | { |
| 97 | lpc_gpio_config(SUSPEND_CYCLE); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * Configure GPIO lines early during romstage. |
| 102 | */ |
| 103 | void lpc_init(void) |
| 104 | { |
| 105 | uint16_t pm1_sts; |
| 106 | uint32_t pm1_cnt; |
| 107 | int slp_type = 0; |
| 108 | |
| 109 | /* |
| 110 | * On S3 resume re-initialize GPIO lines which were |
| 111 | * configured for low power during S3 entry. |
| 112 | */ |
| 113 | pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); |
| 114 | pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); |
| 115 | |
| 116 | if (pm1_sts & WAK_STS) |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 117 | slp_type = acpi_sleep_from_pm1(pm1_cnt); |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 118 | |
Aaron Durbin | 1b6196d | 2016-07-13 23:20:26 -0500 | [diff] [blame] | 119 | if ((slp_type == ACPI_S3) || (slp_type == ACPI_S5)) |
Lee Leahy | acb9c0b | 2015-07-02 11:55:18 -0700 | [diff] [blame] | 120 | lpc_gpio_config(RESUME_CYCLE); |
| 121 | } |