Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 3 | #include <arch/io.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 5 | #include <console/uart.h> |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 6 | #include <cpu/x86/smm.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 7 | #include <device/pci.h> |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 8 | #include <drivers/uart/uart8250reg.h> |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 9 | #include <intelblocks/smihandler.h> |
| 10 | #include <soc/pci_devs.h> |
| 11 | #include <soc/pm.h> |
| 12 | |
Tim Chu | e27e1c1 | 2022-10-19 06:24:21 +0000 | [diff] [blame] | 13 | struct uart8250_state { |
| 14 | uint8_t IER, IIR, MCR, LCR, DLL, DLM; |
| 15 | }; |
| 16 | |
| 17 | static struct uart8250_state s_uart8250_state; |
| 18 | |
| 19 | static void uart8250_store(unsigned int base_port) |
| 20 | { |
| 21 | /* Save previous state for restoring later. */ |
| 22 | s_uart8250_state.IER = inb(base_port + UART8250_IER); |
| 23 | s_uart8250_state.IIR = inb(base_port + UART8250_FCR); |
| 24 | s_uart8250_state.MCR = inb(base_port + UART8250_MCR); |
| 25 | s_uart8250_state.LCR = inb(base_port + UART8250_LCR); |
| 26 | s_uart8250_state.DLL = inb(base_port + UART8250_DLL); |
| 27 | s_uart8250_state.DLM = inb(base_port + UART8250_DLM); |
| 28 | } |
| 29 | |
| 30 | void smm_soc_early_init(void) |
| 31 | { |
| 32 | if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) |
| 33 | uart8250_store(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); |
| 34 | } |
| 35 | |
| 36 | static void uart8250_restore(unsigned int base_port) |
| 37 | { |
| 38 | outb(s_uart8250_state.DLL, base_port + UART8250_DLL); |
| 39 | outb(s_uart8250_state.DLM, base_port + UART8250_DLM); |
| 40 | outb(s_uart8250_state.MCR, base_port + UART8250_MCR); |
| 41 | outb(s_uart8250_state.LCR, base_port + UART8250_LCR); |
| 42 | if ((s_uart8250_state.IIR & UART8250_IIR_FIFO_EN) == UART8250_IIR_FIFO_EN) |
| 43 | outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR); |
| 44 | outb(s_uart8250_state.IER, base_port + UART8250_IER); |
| 45 | } |
| 46 | |
| 47 | void smm_soc_exit(void) |
| 48 | { |
| 49 | if (CONFIG(DRIVERS_UART_8250IO) && CONFIG(DEBUG_SMI)) |
| 50 | uart8250_restore(uart_platform_base(CONFIG_UART_FOR_CONSOLE)); |
| 51 | } |
| 52 | |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 53 | /* |
| 54 | * Specific SOC SMI handler during ramstage finalize phase |
| 55 | */ |
| 56 | void smihandler_soc_at_finalize(void) |
| 57 | { |
| 58 | /* SMM_FEATURE_CONTROL can only be written within SMM. */ |
| 59 | printk(BIOS_DEBUG, "Lock SMM_FEATURE_CONTROL\n"); |
Tim Chu | 3ba1621 | 2022-12-14 11:27:52 +0000 | [diff] [blame] | 60 | pci_devfn_t pcie_offset = soc_get_ubox_pmon_dev(); |
| 61 | if (!pcie_offset) { |
| 62 | printk(BIOS_ERR, "UBOX PMON is not found, cannot lock SMM_FEATURE_CONTROL!\n"); |
| 63 | return; |
| 64 | } |
| 65 | |
| 66 | u32 val; |
| 67 | val = pci_s_read_config32(pcie_offset, SMM_FEATURE_CONTROL); |
| 68 | val |= (SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK); |
| 69 | pci_s_write_config32(pcie_offset, SMM_FEATURE_CONTROL, val); |
| 70 | } |
| 71 | |
| 72 | /* |
| 73 | * This is the generic entry for SOC SMIs |
| 74 | */ |
| 75 | void cpu_smi_handler(void) |
| 76 | { |
Marc Jones | 352ca5b | 2021-03-18 17:01:06 -0600 | [diff] [blame] | 77 | |
| 78 | } |
Rocky Phagura | 17a798b | 2020-10-08 13:32:41 -0700 | [diff] [blame] | 79 | |
| 80 | /* This is needed by common SMM code */ |
| 81 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
| 82 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 83 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 84 | #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) |
| 85 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
| 86 | #endif |
| 87 | }; |