Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <intelblocks/pcie_rp.h> |
| 6 | #include <stdint.h> |
| 7 | |
Furquan Shaikh | ea3e6b06cc | 2021-01-12 16:09:43 -0800 | [diff] [blame] | 8 | static uint32_t pcie_slot_enable_mask(const struct pcie_rp_group *group) |
Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 9 | { |
| 10 | uint32_t mask = 0; |
Furquan Shaikh | ea3e6b06cc | 2021-01-12 16:09:43 -0800 | [diff] [blame] | 11 | unsigned int fn; |
Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 12 | unsigned int i; |
| 13 | const struct device *dev; |
| 14 | |
Furquan Shaikh | ea3e6b06cc | 2021-01-12 16:09:43 -0800 | [diff] [blame] | 15 | for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) { |
| 16 | dev = pcidev_on_root(group->slot, fn); |
Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 17 | if (is_dev_enabled(dev)) |
| 18 | mask |= BIT(i); |
| 19 | } |
| 20 | |
| 21 | return mask; |
| 22 | } |
| 23 | |
| 24 | uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups) |
| 25 | { |
| 26 | uint32_t mask = 0; |
| 27 | uint32_t offset = 0; |
| 28 | const struct pcie_rp_group *group; |
| 29 | |
| 30 | for (group = groups; group->count; ++group) { |
| 31 | if (group->count + offset >= sizeof(mask) * 8) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 32 | printk(BIOS_ERR, "%s: Root port count greater than mask size!\n", |
Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 33 | __func__); |
| 34 | break; |
| 35 | } |
Furquan Shaikh | ea3e6b06cc | 2021-01-12 16:09:43 -0800 | [diff] [blame] | 36 | mask |= pcie_slot_enable_mask(group) << offset; |
Furquan Shaikh | d64d426 | 2020-12-28 13:49:28 -0800 | [diff] [blame] | 37 | offset += group->count; |
| 38 | } |
| 39 | |
| 40 | return mask; |
| 41 | } |