blob: 00bef42a79901ee6b0b055001ff8c513a803d2f8 [file] [log] [blame]
Furquan Shaikhd64d4262020-12-28 13:49:28 -08001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <console/console.h>
4#include <device/device.h>
5#include <intelblocks/pcie_rp.h>
6#include <stdint.h>
7
Furquan Shaikhea3e6b06cc2021-01-12 16:09:43 -08008static uint32_t pcie_slot_enable_mask(const struct pcie_rp_group *group)
Furquan Shaikhd64d4262020-12-28 13:49:28 -08009{
10 uint32_t mask = 0;
Furquan Shaikhea3e6b06cc2021-01-12 16:09:43 -080011 unsigned int fn;
Furquan Shaikhd64d4262020-12-28 13:49:28 -080012 unsigned int i;
13 const struct device *dev;
14
Furquan Shaikhea3e6b06cc2021-01-12 16:09:43 -080015 for (i = 0, fn = rp_start_fn(group); i < group->count; i++, fn++) {
16 dev = pcidev_on_root(group->slot, fn);
Furquan Shaikhd64d4262020-12-28 13:49:28 -080017 if (is_dev_enabled(dev))
18 mask |= BIT(i);
19 }
20
21 return mask;
22}
23
24uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups)
25{
26 uint32_t mask = 0;
27 uint32_t offset = 0;
28 const struct pcie_rp_group *group;
29
30 for (group = groups; group->count; ++group) {
31 if (group->count + offset >= sizeof(mask) * 8) {
Julius Wernere9665952022-01-21 17:06:20 -080032 printk(BIOS_ERR, "%s: Root port count greater than mask size!\n",
Furquan Shaikhd64d4262020-12-28 13:49:28 -080033 __func__);
34 break;
35 }
Furquan Shaikhea3e6b06cc2021-01-12 16:09:43 -080036 mask |= pcie_slot_enable_mask(group) << offset;
Furquan Shaikhd64d4262020-12-28 13:49:28 -080037 offset += group->count;
38 }
39
40 return mask;
41}