| Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 1 | config SOC_INTEL_COMMON_BLOCK_PCIE |
| 2 | bool |
| Subrata Banik | 87ca389 | 2018-11-19 16:23:01 +0530 | [diff] [blame] | 3 | select PCIEXP_COMMON_CLOCK |
| Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 4 | help |
| 5 | Intel Processor common PCIE support |
| 6 | |
| Christian Walter | 18d3159 | 2020-07-07 16:57:15 +0200 | [diff] [blame] | 7 | if SOC_INTEL_COMMON_BLOCK_PCIE |
| 8 | |
| Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 9 | source "src/soc/intel/common/block/pcie/*/Kconfig" |
| 10 | |
| Maximilian Brune | 16f5b54 | 2023-01-17 14:42:27 +0100 | [diff] [blame] | 11 | config PCIEXP_ASPM |
| 12 | default y |
| 13 | |
| Christian Walter | 18d3159 | 2020-07-07 16:57:15 +0200 | [diff] [blame] | 14 | config PCIEXP_CLK_PM |
| 15 | default y |
| 16 | |
| 17 | config PCIEXP_L1_SUB_STATE |
| 18 | default y |
| 19 | |
| Bora Guvendik | 396201c | 2023-03-30 13:54:36 -0700 | [diff] [blame] | 20 | config PCIE_LTR_MAX_SNOOP_LATENCY |
| 21 | hex |
| 22 | default 0x1003 |
| 23 | help |
| 24 | Latency tolerance reporting, max snoop latency value defaults to 3.14 ms. |
| 25 | |
| 26 | config PCIE_LTR_MAX_NO_SNOOP_LATENCY |
| 27 | hex |
| 28 | default 0x1003 |
| 29 | help |
| 30 | Latency tolerance reporting, max non-snoop latency value defaults to 3.14 ms. |
| 31 | |
| Christian Walter | 18d3159 | 2020-07-07 16:57:15 +0200 | [diff] [blame] | 32 | endif # SOC_INTEL_COMMON_BLOCK_PCIE |
| 33 | |
| Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 34 | config PCIE_DEBUG_INFO |
| 35 | bool |
| 36 | help |
| 37 | Enable debug logs in PCIe module. Allows debug information on memory |
| 38 | base and limit, prefetchable memory base and limit, prefetchable memory |
| 39 | base upper 32 bits and prefetchable memory limit upper 32 bits. |
| Kane Chen | fa77ac9 | 2023-07-06 16:05:42 +0800 | [diff] [blame] | 40 | |
| 41 | config PCIE_CLOCK_CONTROL_THROUGH_P2SB |
| 42 | bool |
| 43 | default n |
| 44 | depends on SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
| 45 | help |
| 46 | Enables PCIe CLK control (on/off) through P2SB. The mechanism is supported |
| 47 | starting from MTL platform. In older platforms like ADL & TGL, PCIe CLK is |
| 48 | controlled by sending IPC CMD to PMC. |
| 49 | |
| 50 | config IOE_DIE_CLOCK_START |
| 51 | int |
| 52 | depends on SOC_INTEL_COMMON_BLOCK_IOE_P2SB |
| 53 | default 0 |
| 54 | help |
| 55 | The beginning of IOE DIE pcie src clk number. IOE DIE is started from MTL. |