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Angel Pons6bc13742020-04-05 15:46:38 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Hannah Williamsd9c84ca2016-05-13 00:47:14 -07002
Hannah Williamsd9c84ca2016-05-13 00:47:14 -07003#include <cpu/x86/smm.h>
Kyösti Mälkkie31ec292019-08-10 17:27:01 +03004#include <cpu/intel/em64t100_save_state.h>
Dinesh Gehlot58cc96f2023-01-17 04:01:13 +00005#include <gpio.h>
Brandon Breitensteina86d1b82017-06-08 17:32:02 -07006#include <intelblocks/smihandler.h>
Hannah Williamsd9c84ca2016-05-13 00:47:14 -07007#include <soc/iomap.h>
8#include <soc/pci_devs.h>
Brandon Breitensteina86d1b82017-06-08 17:32:02 -07009#include <soc/pm.h>
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070010
Elyes HAOUASc8a649c2018-06-10 23:36:44 +020011int smihandler_soc_disable_busmaster(pci_devfn_t dev)
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070012{
Subrata Banik2ee54db2017-03-05 12:37:00 +053013 if (dev == PCH_DEV_PMC)
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070014 return 0;
15 return 1;
16}
17
18const struct smm_save_state_ops *get_smm_save_state_ops(void)
19{
20 return &em64t100_smm_ops;
21}
22
23const smi_handler_t southbridge_smi[32] = {
Subrata Banik4ab7ef92020-02-20 11:53:04 +053024 [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
25 [APM_STS_BIT] = smihandler_southbridge_apmc,
26 [PM1_STS_BIT] = smihandler_southbridge_pm1,
27 [GPIO_STS_BIT] = smihandler_southbridge_gpi,
Patrick Georgia7ec4262020-03-11 16:31:59 +010028#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
Subrata Banik4ab7ef92020-02-20 11:53:04 +053029 [TCO_STS_BIT] = smihandler_southbridge_tco,
Patrick Georgia7ec4262020-03-11 16:31:59 +010030#endif
Subrata Banik4ab7ef92020-02-20 11:53:04 +053031 [PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
Julius Wernercd49cce2019-03-05 16:53:33 -080032#if CONFIG(SOC_ESPI)
Shaunak Saha41cfd5ba2017-12-06 11:22:53 -080033 [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
34#endif
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070035};