| Hannah Williams | 067d38a | 2018-05-31 19:16:09 -0700 | [diff] [blame] | 1 | 0x00000000, 0x100000000, WB, # RAM |
| 2 | # Above entry is needed because below 4G allocated memory range is |
| 3 | # only known after FSP memory init completes. However, FSP migrates to memory |
| Elyes HAOUAS | ef90609 | 2020-02-20 19:41:17 +0100 | [diff] [blame] | 4 | # from cache as RAM before it exits FSP Memory Init. Hence we need to add |
| Hannah Williams | 067d38a | 2018-05-31 19:16:09 -0700 | [diff] [blame] | 5 | # page table entries for this entire range before FSP Memory Init. The |
| 6 | # overlapped MMIO ranges will be overridden by below entries. |
| Aaron Durbin | 5c9df70 | 2018-04-18 01:05:25 -0600 | [diff] [blame] | 7 | 0xd0000000, 0x100000000, UC, NX # All of MMIO |
| 8 | # Maximum 16MiB of mmio SPI flash decode. |
| 9 | 0xff000000, 0x100000000, WP, # memory-mapped SPI |
| 10 | # MMIO XIP bootblock C_ENV_BOOTBLOCK_SIZE |
| 11 | 0xffff8000, 0x100000000, WP, # XIP bootblock |
| 12 | # DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 13 | 0xfef00000, 0xff000000, WB, NX # CAR |
| 14 | # VERSTAGE_ADDR ~63KiB |
| 15 | 0xfef40000, 0xfefc0000, WB, # verstage |
| 16 | # ROMSTAGE_ADDR ~68KiB |
| 17 | 0xfef20000, 0xfefc0000, WB, # romstage |
| 18 | # FSP_M_ADDR ~408 KiB (non-debug) |
| 19 | 0xfef40000, 0xfefc0000, WB, # fsp-m |